Control Bits Research Articles

Artefacts Produced by Normal Saline When Used as a Holding Solution for Biopsy Tissues in Transit

Oral surgeons, surgeons and dentists carrying out small biopsy procedures on an out-patient basis have been frequently sending poorly stored biopsy tissues to the Departments of Oral Pathology of various dental colleges, wherein the tissues were being stored in normal saline and then transferred to formalin. Such tissues often show abnormal cellular and architectural changes, which pose a challenge to diagnosis, especially when the histopathologist is not aware that the tissue was stored in normal saline for some time. We wanted to know the extent of artefactually induced cellular and architectural changes in tissues that were transported in normal saline and received by us, based on the duration for which they were held in normal saline. Normal oral soft tissue was subjected to storage in normal saline for periods varying from 1 to 36h, before being fixed in 10% formalin. Soft tissue specimens were collected during routine surgical extractions and each was cut into six parts. One was transferred immediately to formalin as control and other bits kept in normal saline for intervals of 1, 3, 12, 24, and 36h before fixing in formalin. A comparative photographic analysis was carried out to analyze the histopathological changes. The tissues kept in normal saline before fixation underwent various changes. In no way should normal saline be used, even for a short time, to store and transport excised tissue; it is imperative that such tissues be placed immediately in a proper fixative like 10% formalin.

Deriving an NCD file from an FPGA bitstream: Methodology, architecture and evaluation

This paper demonstrates a reverse engineering method that takes a bitstream as input and produces an NCD (Native Circuit Description) file for a Xilinx FPGA chip. The work can be divided into two parts: mapping table generation and NCD generation. The mapping tables include the mapping relation among configurable points, configurable options, control bits and control values. An automatic distributed high performance analysis architecture and offset formula theory are developed to quickly generate the test cases, work out the mapping tables and verify their correctness. Based on the tables, we generate an XDL (Xilinx Design Language) file which is equivalent to the NCD file. Our work is the first which can rebuild the NCD file for a bitstream. We also evaluate our method with respect to time consumption and accuracy rate. Benchmarks using real circuits indicate that the accuracy rate on XC5VLX50T is above 88% even in the worst case. Our method is applicable to all series of Xilinx FPGA chips and the accuracy can be guaranteed if the scale of the chip is increased.

Design of Wireless Optical Access System using LED

This paper develops a prototype to demonstrate a full-duplex wireless visible light communication (VLC) system based on Universal Serial Bus (USB) port. Combing with a USB 2.0 port on one board, it can achieve up to 2 Mbps bit rates error free, which is mainly limited to the USB bridge circuit, between two computers for data transmission, such as text, audio and video. Hyper Terminal and self-written software are used to allow setting the transmission data rate, control bits, check bits and achieve real-time transmission between any two mobile devices with a USB port. The work is based on the research of VLC local access network. This paper also shows the experimental results and the relationship between system transmission eye diagram and bit rate.

Routing Protocol for Mobile Ad Hoc Network

Routing protocol is the act of moving information across an inter-network from a source to a destination. Routing directs forwarding by passing of packets from their source toward their ultimate destination through intermediary nodes. The routing process usually directs forwarding on the basis of routing tables within the routers, which maintain a record of the best routes to various network destinations. Thus the construction of routing tables becomes very important for efficient routing. In wireless ad hoc networks, all nodes are mobile and can be connected dynamically in an arbitrary manner. One way to enhance the performance of routing protocol is to improve the metrics used in the route selection. This paper aims to find a way to minimize the end to end delay in the event of congestion in the primary route path and increase throughput by using the least amount of control bits. The proposed protocol is solved the congestion by using an additional factor in selecting the best available path, this factor depends on the assessment of congestion on the primary path. This has been accomplished by using the stored routing information that is not used by the primary routing table in the selecting of an alternative route. The proposed protocol has been compared with the AODV protocol and OLSR protocol. The Experimental results suggest a remarkable E-DSDV's performance in an end-to-end delay, NRL and throughput metrics are better than OLSR and AODV.

An Accurate Fractional Period Delay Generation System

An all-digital technique is proposed for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A subsampling technique-based delay measurement unit (DMU) capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The proposed delay generation system periodically measures and corrects the error and maintains it at the minimum value without requiring any special calibration phase. Up to 40 improvement in accuracy is demonstrated for a commercial programmable delay generator chip. The time-precision trade-off feature of the DMU is utilized to reduce the locking time. Loop dynamics are adjusted to stabilize the delay after the minimum error is achieved, thus avoiding additional jitter. Measurement results from a high-end oscilloscope also validate the effectiveness of the proposed system in improving accuracy.

Design and simulation of novel TLG–SET based configurable logic cells

Single electron tunneling circuits seem to be promising candidates as basic circuit elements of the next generation ultra-dense VLSI and ULSI circuits for their ultra-low power consumption, ultra-small size, and rich functionality. In this paper, design and simulation of novel configurable logic cells (CLCs) using single electron tunneling (SET) technology based threshold logic gate (TLG) are presented. The proposed CLC can realize all Boolean logic functions by configuring the control bits without changing the structure of the circuit and the parameters of TLG–SET based design. The logic operation of the circuit is simulated using Monte Carlo simulation. According to the simulation results, the circuit operation based on the transfer of single electrons between adjacent islands is stable.

Non-Data-Aided Timing Acquisition for Asynchronous IDMA Systems

Sample-timing error can cause significant performance degradation for the interleave-division multiple-access systems (Wang et al. 2009). In this paper, we propose a non-data-aided timing acquisition scheme to mitigate sample-timing error due to the asynchronous transmission of random allocated user ends (UEs) on the uplink. A closed-loop timing control scheme is constructed for the asynchronous IDMA system in this paper. We use the extrinsic information generated during the iterative detection algorithm with signal noise ratio evolution to estimate the timing offset for the asynchronous uplink in the base station (BS) receiver. The BS receiver returns the timing control bits, which is generated with estimated timing offsets, to the corresponding UE. And the UE uses the timing control bits to adjust local transmission time to guarantee the sampling performance at the BS receiver. The simulation results show that the proposed acquisition scheme based on feedback loop can provide high acquisition probability and low false alarm probability. The proposed scheme can overcome the bit-error-rate performance bottleneck, which is caused by the sample-timing error in BS receiver due to the asynchronous signals in the uplink.

Virtual subdivision for GPU based collision detection of deformable objects using a uniform grid

We present an improved uniform subdivision based discrete and continuous collision detection approach for deformable objects consisting of triangle meshes without any assumption about triangle size. A previously proposed technique using control bits can effectively eliminate redundant object pairs appearing in multiple cells, but this scheme requires the grid cell size adapted to the largest object, and efficiency tends to be severely impaired when object size varies strongly. In this paper, we discuss an approach that virtually subdivides large triangles into a number of child triangles to enable the use of a smaller, better suited cell size, resulting in a considerable decrease in the number of collision tests in the broad phase, with a corresponding reduced memory requirement. The virtual subdivision is used only for the purpose of collision detection and is recomputed each frame, with the original mesh retained for collision response and physical simulation. Our method exploits the benefits of GPU architecture to accelerate the computationally intensive task for improved performance. The results show that the method provides speedups by comparing performance with existing methods.

A modified summation code for organizing control of combinatorial circuits

We propose a new modified summation code which has improved error detection characteristics as compared to the classical summation code. We define the properties of this code and propose methods to implement the generators of control bits.

Joint power control and beamforming codebook design for MISO channels under the outage criterion

This paper investigates the joint design of power control and beamforming codebooks for limited-feedback multiple-input single-output (MISO) wireless systems. The problem is formulated as the minimization of the outage probability subject to the transmit power constraint and cardinality constraints on the beamforming and power codebooks. We show that the two codebooks need to be designed jointly in this setup, and provide a numerical method for the joint optimization. For independent and identically distributed (i.i.d.) Rayleigh channel, we also propose a low-complexity approach of fixing a uniform beamforming codebook and optimizing the power codebook for that particular beamformer, and show that it performs very close to the optimum. Further, this paper investigates the optimal tradeoffs between beamforming and power codebook sizes. We show that as the outage probability decreases, optimal joint design should use more feedback bits for power control and fewer feedback bits for beamforming. The jointly optimized beamforming and power control modules combine the power gain of beamforming and diversity gain of power control, which enable it to approach the performance of the system with perfect channel state information as the feedback link capacity increases—something that is not possible with either beamforming or power control alone.

The way for guaranteed detecting four errors in binary symmetric channel by using of minimum control bits numbe

The way for guaranteed detecting four errors in binary symmetric channel by using of minimum control bits numbe

Robust quantum gates via a photon triggering electromagnetically induced transparency

We propose a scheme to achieve a parallelized controlled-NOT (c-not) gate based on electromagnetically induced transparency (EIT) and cavity-assisted photon scattering. By using the flying photon as the control bit, we can implement a conditional transfer between two logical states of an atom trapped in the cavity with high fidelity and on a microsecond time scale. Thanks to the fact that the photon is well suited for scalable quantum computation, a quantum c-not gate between the single-photon pulses and the nonlocal gate on remote atoms are obtained by reflecting the photon pulse from an optical cavity with a single-trapped atom. Our protocol is robust for spontaneous emission and works quite well in the bad-cavity limit, which makes it more applicable in the laboratory with current experimental techniques.

Bitstream decoding and SEU-induced failure analysis in SRAM-based FPGAs

Reconfigurable SRAM-based FPGAs are highly susceptible to radiation induced single-event upsets (SEUs) in space applications. The bit flip in FPGAs configuration memory may alter user circuit permanently without proper bitstream reparation, which is a completely different phenomenon from upsets in traditional memory devices. It is important to find the relationship between a programmable resource and corresponding control bit in order to understand the impact of this effect. In this paper, a method is proposed to decode the bitstream of FPGAs from Xilinx Corporation, and then an analysis program is developed to parse the netlist of a specific design to get the configuration state of occupied programmable logic and routings. After that, an SEU propagation rule is established according to the resource type to identify critical logic nodes and paths, which could destroy the circuit topological structure. The decoded relationship is stored in a database. The database is queried to get the sensitive bits of a specific design. The result can be used to represent the vulnerability of the system and predict the on orbit system failure rate. The analysis tool was validated through fault injection and accelerator irradiation experiment.

Influence of a Resilient, Hard‐Carbon Thin Film on Drilling Efficiency and Thermogenesis

To determine changes in drill bit performance attributable to application of a triaxially resilient, hard-carbon thin film. In vitro mechanical study. Five matched pairs of control bits and bits with a carbon nanofilm applied were tested in equine cortical bone and a synthetic bone substrate. Thirty sequential holes were drilled with each bit. Drilling time was recorded for all holes. Maximum substrate temperature was measured with infrared thermography for holes 1, 15, and 30. Drilling time, prolongation of drilling time over successive uses, and maximum substrate temperature were compared between control and test bits in each substrate. Drilling time was significantly reduced with test bits in both substrates. Drilling time over successive osteotomies increased more slowly with test bits than with control bits. Test bits generated significantly lower substrate temperatures during drilling. Bits with the carbon nanofilm completed osteotomy faster and generated less heat than control bits. Test bits also had less degradation of drilling performance with repeated use.

Wide division ratio range programmable frequency divider with close-to-50% output duty-cycle

A novel wide division ratio (DR) range programmable frequency divider is presented in this article, which is based on the proposed divide-by-2/3/4 cell. The divider's output is buffered by a divide-by-2 cell; hence, it can achieve the close-to-50% output duty-cycle. The DRs can be set via the convenient provisions of binary bits. When the DR is even, the output duty-cycle is exactly 50%. If the DR is odd, the output duty-cycle is k/(2 k + 1), where k is a natural number, therefore, it becomes close-to-50% with an increasing k. A divider with eight DR control bits, which can realise the DRs from 8 to 511, is implemented in standard 0.18 µm complementary metal-oxide semiconductor technology, the die area is 0.02 mm2. The measured results show that the divider can obtain 44.4–50% output duty-cycle which corroborates with the calculation.

A software solution to estimate the SEU-induced soft error rate for systems implemented on SRAM-based FPGAs

SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets (SEUs) in space applications. The failure mechanism in FPGA's configuration memory differs from those in traditional memory device. As a result, there is a growing demand for methodologies which could quantitatively evaluate the impact of this effect. Fault injection appears to meet such requirement. In this paper, we propose a new methodology to analyze the soft errors in SRAM-based FPGAs. This method is based on in depth understanding of the device architecture and failure mechanisms induced by configuration upsets. The developed programs read in the placed and routed netlist, search for critical logic nodes and paths that may destroy the circuit topological structure, and then query a database storing the decoded relationship of the configurable resources and corresponding control bit to get the sensitive bits. Accelerator irradiation test and fault injection experiments were carried out to validate this approach.

An Improved Rate Control Scheme for H.264 Based on Frame Complexity Estimation

The JVT-G012 rate control algorithm for H.264 video encoding can get high encoding efficiency. But the algorithm has disadvantage that the target bit allocation in the frame layer is uniform according to the buffer residual bits. This paper presents a new method which uses a content complexity quotiety of frame for allocating target bits in the frame layer more accurately. The content complexity quotiety is the combination of the average difference of gray histogram and mean absolute difference (MAD) ratio in the frame. Experimental results show that the bit rate maximum error of tested sequences in this algorithm is 1.38 percent and their average peak signal noise ratio (PSNR) is improved by 0.38 dB on average compared to the original JVT-G012 algorithm. Therefore, the proposed rate control algorithm can not only more accurately control bit rate, but also improve PSNR of video sequences. The video image quality is better and smoother.

GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses

Two main sources for power dissipation in parallel buses are data transitions on each wire and coupling between adjacent wires. So far, many techniques have been proposed for reducing the self and coupling powers. Most of these methods utilize one (or more) control bit(s) to manage the behavior of data transitions on the parallel bus. In this paper, we propose a new coding scheme, referred to as GPH, to reduce power dissipation of these control bits. GPH coding scheme employs partitioned Bus Invert and Odd Even Bus-Invert coding techniques. This method benefits from Particle Swarm Optimization (PSO) algorithm to efficiently partition the bus. In order to reduce self and coupling powers of the control bits, it finds partitions with similar transition behaviors and groups them together. One extra control bit is added to each group of partitions. Properly managing number of transitions on control bits of each partition and that of each group, GPH reduces total power consumption, including coupling power. It also locates control bits of each partition such that total power consumption is minimized. We evaluate the efficiency of the proposed method for coding data and address buses under various hardware platforms. Experimental results show 43% average power saving in coded data compared to the original one. We also show the prominence of our coding scheme over previously proposed techniques.

Rabbits' feet and four-leaf clovers

Rabbits' feet and four-leaf clovers

A Michelson controlled-not gate with a single-lens astigmatic mode converter

We propose and demonstrate experimentally a single lens design for an astigmatic mode converter that transforms the transverse mode of paraxial optical beams. As an application, we implement a controlled-not gate based on a Michelson interferometer in which the photon polarization is the control bit and the first order transverse mode is the target. As a further application, we also build a transverse mode parity sorter which can be useful for quantum information processing as a measurement device for the transverse mode qubit.