Continuous-time Linear Equalizer Research Articles

A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS

This paper presents a low-power, high-bandwidth wireline transceiver for chiplet. The transceiver uses a new technology of correlated non-return to zero (CNRZ) to improve the pin efficiency and reduce the noise of the common mode and crosstalk (CMN and XTALK). The transmitter adopts a 4:1 multiplexer (MUX) and a special voltage-mode driver [source series terminated (SST)] to improve the power efficiency. The receiver utilizes a low jitter clock-and-data alignment (CDA) based on high resolution phase interpolator (PI) and a MINI-PLL with differential filter based to improve the jitter performance of the receiver’s clock. In addition, a special continuous-time linear equalizer (CTLE) is introduced into the multiple-input compare (MIC) based decode circuit to reduce the receiver’s bit error rate (BER). This transceiver is designed with a 28 nm CMOS process technology and supplied with 0.9/1.2 V. Simulation results show that this transceiver can operate at 200 Gb/s with the 33.3 Gb/s single-wire data rate and a power consumption of 1.06 pJ/b. The transceiver’s BER is less than 1E-15 and eye-wide-opening is 12.02 ps (48.08% UI), which is under 10 dB channel loss at 20 GHz Nyquist frequency.

A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS

This article presents a 56-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter/receiver (TX/RX) chipset for optical link. The optical transmitter (TX) adopts a digital-to-analog converter (DAC)-based structure with a two-tap nonlinear PAM-4 feed-forward equalizer (FFE) implemented in the digital domain to compensate for the asymmetric responses from the vertical cavity surface-emitting laser (VCSEL). The 56-Gb/s PAM-4 receiver (RX) is connected to the photodiode (PD) and transimpedance amplifier (TIA) module for optical application. The interconnection loss from the RX chip to the PD+TIA module is compensated by the RX continuous-time linear equalizer (CTLE) and the one-tap decision-feedback equalizer (DFE). The pattern-filter-based bang-bang phase detector in the RX improves the jitter performance. Both TX and RX are fabricated in the 40-nm CMOS. The VCSEL TX demonstrates a 56-Gb/s compensated PAM-4 waveform with −0.9-dBm outer optical modulation amplitude (OMA) while consuming only 97 mW of power (1.73 pJ/b). The RX achieves 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> bit error rate (BER) with 0.08 UI margin under 10-dB interconnection loss while dissipating 278 mW of power (4.96 pJ/b).

A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process

This article presents a high-speed receiver for next-generation 8K ultra-high-definition TVs. The receiver supports error-free communication between the timing controller and the display driver integrated circuits (DDIs) across various channels. Because the receiver must be co-integrated with pixel drivers in the DDI, it must be implemented in a process with high-voltage devices, which poses significant challenges in achieving beyond 5-Gb/s operation. We propose techniques for overcoming such process-induced speed limitations. They include a level-shifting passive continuous-time linear equalizer (CTLE), an active CTLE with extended bandwidth using a negative capacitor, a speculative decision feedback equalizer with a down-sampled edge-sampling path, and a low-dropout regulator with parallel error amplifiers to achieve all-band power supply rejection. A reference-less clock and data recovery circuit with a new frequency detector is also described. Fabricated in a 180-nm CMOS process, the prototype receiver operates at 5.2 Gb/s and can compensate up to 29-dB channel loss while consuming 120 mA from a 1.8-V supply.

Optimal Optical Receivers in Nanoscale CMOS: A Tutorial

The integration of optical receivers in nanoscale CMOS technologies is challenging due to less intrinsic gain and more noise compared to SiGe BiCMOS technologies. Recent research revealed that low-noise, high-gain, and low-power CMOS optical receivers can be designed by limiting the bandwidth of the front-end followed by equalization techniques that benefit from good switching characteristics offered by CMOS technologies. In this tutorial brief, the operation of decision-feedback equalization, feed-forward equalization, and continuous-time linear equalization is reviewed in the context of high baud-rate 2-PAM and 4-PAM modulation. Recent advances and techniques in 4-PAM optical receivers are reviewed and compared in terms of speed, sensitivity, bandwidth, and efficiency.

Receiver Analog Front-End Cascading Transimpedance Amplifier and Continuous-Time Linear Equalizer for Signals of 5 to 30 Gb/s

A 5–30 Gb/s receiver analog front-end (AFE) cascading transimpedance amplifier (TIA) and continuous-time linear equalizer (CTLE) were implemented using a Taiwan Semiconductor 180 nm process. The system comprises a two-stage differential input pair CTLE, TIA, and a differential termination resistor Rm. A source-degenerated transconductance stage was adopted in the CTLE, and source follower and shunt feedback resistor stages were adopted in the TIA. The proposed CTLE could achieve high frequencies by altering the tail current with fixed degenerate capacitance CS and resistance RS. The proposed AFE achieved high bandwidth, and the use of a feedback resistor Rf and inductor Lf improved its high-frequency performance. Simulation results revealed that the CTLE can compensate for 16 dB of channel loss at a 3 GHz Nyquist frequency and can open closed eyes in a 6 Gb/s non-return-to-zero signal with a bit error rate of 0.16 × 10−12 for a 231 − 1 pseudorandom binary sequence input. The AFE could compensate for 12 dB of channel loss at a 15 GHz Nyquist frequency and can open closed eyes in a 30 Gb/s PAM4 signal from a pseudorandom binary sequence input; it consumed 27 mW of power at 1.8 V.

A 5-Gb/s Adaptive Continuous Time Linear Equalizer Using Ferroelectric Capacitor

This article presents a 5-Gb/s continuous-time linear equalizer (CTLE) for serial link interface where adaptive nature is achieved using a ferroelectric capacitor. This barium strontium titanate (BST)-based STPTIC-15G2 capacitor model from STMicroelectronics provides a smooth 5:1 tuning range for a voltage range of 0&#x2013;18 V and eliminates the use of blocking capacitor required in case of varactor diode. The tunability of the high-pass filter response of the proposed CTLE provides the flexibility to meet the allocated loss budget of any serial link more precisely than a design with a discrete value capacitor. Also, its design methodology is much simpler than conventional MOSFET-based CTLE. Moreover, it avoids the use of complex algorithms seen in the case of digital equalization. For validation, the design is implemented on an FR4 board. While studying the data rate tolerance and channel tolerance of the printed prototype, the measured results closely match the simulation results. The compensation level of the equalizer is verified for an FR4 channel by varying its length from <inline-formula> <tex-math notation="LaTeX">$7^{\prime \prime }$ </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">$28^{\prime \prime }$ </tex-math></inline-formula> which is equivalent to a change in insertion loss from 1.3 to 5.2 dB at 2.5 GHz, which is the Nyquist frequency for a 5-Gb/s signal. Also, for a <inline-formula> <tex-math notation="LaTeX">$28^{\prime \prime }$ </tex-math></inline-formula> FR4 channel, a channel loss requirement of 8&#x2013;9.5 dB is achievable by simply varying the applied bias to the ferroelectric capacitor from 0 to 10 V.

A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET

This article describes the design of a 1.24-pJ/b 112-Gb/s PAM4 transceiver test chip in 7-nm FinFET for in-package die-to-die communication. The receiver supports 0–1.2-V input common mode and utilizes a single-stage active inductor-based CMOS continuous-time linear equalizer (CTLE) with 12 data slicers and two error slicers. The quad-rate voltage-mode transmitter implements delay-based sub-UI two-tap FFE and digital I/Q and DCC clock calibration. A single-phase clock from a wideband <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> phase-locked loop (PLL) is distributed to eight transceiver channels. In each channel, an injection-locked oscillator (ILO) generates eight-phase clocks that feed an 8-bit CMOS phase interpolator (PI). The transceiver achieves < 1e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> bit error rate (BER) over 30-mm channel at 106.25 Gb/s and over 20-mm channel at 112 Gb/s.

A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS

This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates a continuous time linear equalizer, a variable gain amplifier, a phase interpolator-based clock and data recovery, and a 4-tap direct decision feedback equalizer (DFE) for moderate channel loss applications in wireline communication. A dynamic current-mode logic comparator (DCMLC) is proposed and employed in the DFE. The DCMLC, which adopts dynamic logic, breaks the trade-off between the bandwidth and the clock to Q delay in the traditional current-mode logic comparator (CMLC). Compared with the traditional CMLC, the DCMLC reduces the clock to Q delay by 36&#x0025;, which allows the implementation of a 4-tap direct DFE. Moreover, the first tap feedback signals are directly tapped from the output of the DCMLC, allowing the first tap feedback current to initiate 0.5UI before the decision clock. The PAM-4 receiver prototype is fabricated in a 65nm CMOS process. At a data rate of 56-Gbps, it can compensate for up to 20.17dB loss and achieve a bit error rate <inline-formula> <tex-math notation="LaTeX">$&lt; 1\text{E}$ </tex-math></inline-formula>-10 with a power efficiency of 4.75 pJ/bit.

A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End

An important issue in wireline receivers (RX) is minimizing the area and power consumption while overcoming the channel attenuation with an equalizer. The greater the compensation for channel loss at the analog front end (AFE) of the RX, the lower the number of decision feedback equalizer (DFE) taps. Power dissipation and area can be reduced by reducing the number of DFE taps. This brief presents a technology that compensates for the channel loss with the proposed AFE based on a two-stage continuous-time linear equalizer (CTLE), low and high bandwidth amplifiers, and a gain controller. It sufficiently reduces the DC gain and increases the peak gain of the AFE by using a feedforward equalizer (FFEQ) and feedback equalizer (FBEQ). These equalizers result in an increase in the difference between the peak and DC gains and the gain difference at the fundamental frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> ) and 2nd subharmonic frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/2</sub> ). The IC is fabricated in a 28 nm CMOS process, and the proposed architecture yields a BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> at 25.8 dB channel attenuation. At 25 Gb/s, the area and power efficiency of the proposed AFE are 1.19 pJ/bit and 0.01 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.

Accurate Characterization for Continuous-Time Linear Equalization in CMOS Optical Receivers

Recently published CMOS optical receivers consist of a limited-bandwidth first-stage transimpedance amplifier (TIA) followed by an equalizer. Limiting the TIA’s bandwidth improves the gain and reduces the noise but introduces a significant inter-symbol interference (ISI) that is dealt with by the subsequent equalizer. Continuous-time linear equalizer (CTLE) is a commonly used equalizer in both electrical and optical links. However, recent research reported different findings about CTLE-based optical receivers. Some research papers concluded that CTLEs boost high-frequency noise compared to a full-bandwidth design. Other publications reported that high-frequency noise remains unaffected while white noise is significantly reduced. This work aims to solve this discrepancy by presenting an accurate analysis for CTLE-based optical receivers considering noise, gain, and jitter. We show that the noise performance depends on the pole/zero locations of the limited-bandwidth (LBW)-TIA and the follow-on equalizer. A properly designed CTLE-based receiver achieves a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.5 \times $ </tex-math></inline-formula> higher gain and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.74\times $ </tex-math></inline-formula> better noise than the full-bandwidth design. The CTLE is also compared to the well-known decision feedback equalizer (DFE). The noise performance of the CTLE-based receiver lies between that of finite and infinite impulse response DFE-based receivers but achieves better gain than both architectures.

LDLA14: a 14 Gbps optical transceiver ASIC in 55 nm for NICA multi purpose detector project

This paper presents the design and test results of a 14 Gbps optical transceiver ASIC (LDLA14) fabricated in a 55 nm CMOS technology for NICA Multi Purpose Detector (MPD) project. The LDLA14 is a single-channel bidirectional (1Tx + 1Rx) optical transceiver ASIC, including a Laser Driver (LD) module and a Limiting Amplifier (LA) module. It would drive the Vertical Cavity Surface Emitting Laser (VCSEL) of Transmitter Optical Sub-Assembly (TOSA) and receive signals from Photo Diode (PD) of Receiver Optical Sub-Assembly (ROSA), respectively. In the LDLA14, a novel structure of capacitive coupling pre-emphasis is proposed in the output driver of LD to obtain peaking effect without sacrifice the modulation current swing. A shared inductor technology and a Continuous Time Linear Equalizer (CTLE) pre-emphasis structure are added in the output buffer of LA to improve the quality of the output eye diagram. The dimension of LDLA14 is 1.5 mm × 1.3 mm, and the power consumption is 178 mW. The Peak-to-Peak Jitter (PPJ) and Root-Mean-Square Jitter (RMSJ) of the 14 Gbps optical eye diagram of LD in the Tx direction are 22.5 ps and 3.5 ps, respectively. The PPJ and RMSJ of the 14 Gbps electrical eye diagram of LA in the Rx direction are 23.1 ps and 4.7 ps, respectively. The BER tests have been conducted in Tx, Rx directions and the Tx-Rx loop condition, and the BER less than 10−12 is achieved in all tests.

A 1.68–23.2-Gb/s Reference-Less Half-Rate Receiver With an ISI-Tolerant Unlimited Range Frequency Detector

This paper presents a reference-less half-rate receiver with an unlimited range frequency detector (URFD) for 13.8X continuous rate operation. To tolerate channel loss induced inter-symbol interference (ISI), the receiver is integrated with a continuous time linear equalizer (CTLE) and a 2-Tap decision feedback equalizer (DFE) on the same chip. Incorporating with the novel pulse width based URFD, the date rate of the receiver is limited by the frequency tuning range of the voltage-controlled oscillator (VCO). The energy efficiencies of the whole receiver and clock data recovery (CDR) are about 2.39 and 0.97 pJ/bit respectively. Implemented in a TSMC 28-nm CMOS process, the active area is 0.056 mm.

A SYSTEM FOR REGULATING THE LINEARITY EQUALIZER IN A RECEIVER

The improvement of linearity of the two-stage continuous time linear equalizer cir¬c¬u¬it located in the receiver of the high speed SER-DES data transmission system is presented. It allows to significantly increase the linearity of the system, which leads to an increase in the output working range of the circuit. A system controlled by a common mode of the input voltage has been introduced, which solves the problem of evenly changing currents in differential pairs. Simulation results show that in the worst case the proposed method incre¬a¬s¬es the linearity of the system by 35% due to the reduction of the amplification coefficient by 6%.

A 4 × 10 Gb/s Adaptive Optical Receiver Utilizing Current-Reuse and Crosstalk-Remove

This article presents a $4 \times 10$ Gb/s low-noise adaptive optical receiver, utilizing a current-reuse architecture and channel crosstalk-remove techniques in 65-nm CMOS process. The receiver integrates a transimpedance amplifier (TIA), a continuous-time linear equalizer (EQ), high-gain and high-bandwidth limiting amplifiers, and a 50- $\Omega $ output driver into a single die. The TIA employs a common-source-based pseudo-differential topology with input series inductive peaking and $g_{m}$ -enhancement to improve bandwidth and noise performance. An automatic-gain-control loop scheme is presented which solves the bandwidth variation issue caused by variation of the TIA input impedance, across a large dynamic range of a small input to a maximum overload current. Multiple crosstalk reduction techniques are adopted to improve the channel isolation performance. The 850-nm vertical cavity surface emitting laser (VCSEL)-based full-link measurement results show that the optical receiver achieves $20.4~\mu \text{A}_{\mathrm {pp}}$ sensitivity bit-error-rate (BER $ -12) with a 200-fF photodiode, competitive with other prior CMOS-based TIAs. The crosstalk over different channels is also measured, demonstrating only a sensitivity penalty of 1 dB.

A 10-Gb/s Driver/Receiver ASIC and Optical Modules for Particle Physics Experiments

We present the design and test results of a Drivers and Limiting AmplifierS ASIC operating at 10 Gb/s (DLAS10) and three miniature optical transmitter/ receiver/transceiver modules (MTx+, MRx+, and MTRx+) based on DLAS10. DLAS10 can drive two transmitter optical subassemblies (TOSAs) of vertical cavity surface emitting lasers (VCSELs), receive the signals from two receiver optical subassemblies (ROSAs) that have no embedded limiting amplifiers (LAs), or drive a VCSEL TOSA and receive the signal from a ROSA, respectively. Each channel of DLAS10 consists of an input continuous time linear equalizer (CTLE), a four-stage LA, and an output driver. The LA amplifies the signals of variable levels to a saturation amplitude of 800 mV (peak-peak). The output driver drives VCSELs or impedance-controlled traces. DLAS10 is fabricated in a 65-nm CMOS technology. The die is 1 mm ×1 mm. DLAS10 is packaged in a 4 mm ×4 mm 24-pin quad-flat no-leads (QFNs) package. DLAS10 has been tested in MTx+, MRx+, and MTRx+ modules. Both measured optical and electrical eye diagrams pass the 10-Gb/s eye mask test. The input electrical sensitivity is 40 mVp-p, while the input optical sensitivity is -12 dBm. The total jitter of MRx+ is 29 ps (P-P) with a random jitter of 1.6 ps (rms) and a deterministic jitter of 9.9 ps. Each MTx+/MRx+ module consumes 82.6 and 174.4 mW/ch, respectively.

A 28-nm CMOS 11.2-Gbps Receiver based on Adaptive CTLE and Adaptive 3-Tap DFE With Hysteresis Low-pass Filter

This paper proposes a receiver design incorporating both an adaptive continuous-time linear equalizer (CTLE) and an adaptive decision-feedback equalizer (DFE). The CTLE utilizes a merged rectifier and error amplifier, improving the DC gain and reducing the current consumption. Offset cancelation of the CTLE is performed by adaptively adjusting the load resistance of a CTLE cell. The DFE adopts the technique of using a slave latch behind a current summer for the relaxed timing constraint but excludes other auxiliary circuits that perform a master-latch function. The proposed low-pass filter with a hysteresis can suppress the oscillation of the DFE tap coefficients and the data level in the steady state. Fabricated in 28-nm CMOS process, the prototype receiver shows that the measured BER is less than 10<SUP>-14</SUP> at 10.4 Gb/s for an 18-inch FR4 trace and at 11.2 Gb/s for a 12-inch FR4 trace, respectively, with both the adaptive CTLE and the adaptive DFE activated. Operating at 11.2 Gb/s, the energy efficiency of the receiver is 5.36 pJ/bit.

A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS

This paper discusses a 56-Gb/s PAM4 receiver analog-front end (AFE) implemented in TSMC 40-nm CMOS process. The system consists of a differential 100- Ω termination, a two-stage continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA), and an output buffer. The source-degenerated transconductance stage and inverter-based transimpedance (TIA) with source follower structure are adopted for both CTLE and VGA. The utilization of source follower can solve the harsh DC operation problem in conventional inverter-based TIA and extend the bandwidth. By altering the source-degenerated resistors and capacitors in the two-stage CTLE, the proposed AFE can reach fixed peaking frequency with 9-dB compensation range at high frequency. Moreover, it can also achieve a fixed bandwidth at 14 GHz and 9.5-dB DC gain tuning range when altering the feedback resistors and negative capacitance compensation network (NCC) in VGA. Measurement results demonstrate that: it can compensate for 7.3-dB channel loss at 14-GHz Nyquist frequency and open the closed eye for 56-Gb/s PAM4 signal with BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> from 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> - 1 PRBS input. The core of the AFE occupies 0.32-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area and consumes 30-mW power from 1.1/1.2-V supply.

A 20-Gb/s charge-steering equalizer utilizing highly-efficient charge-steering linear equalizer

The need for high-speed low-power receivers has grown due to the large increase in data rates and Internet-of-Things (IoT) applications. Equalizer-based receivers contain mainly two types of equalizers; Continuous-Time-Linear-Equalizers (CTLE) and non-linear equalizers implemented as Decision-Feedback-Equalizers (DFE). Many solutions have been introduced in the literature to enhance the power consumption of DFEs by using time interleaving or charge-steering. Still, the CTLE power consumption remains considerable a big portion of the overall power of the equalizer-based receivers. The CTLE function cannot be neglected as it equalizes the pre-cursors. This paper presents a low-power charge-steering based receiver that consists of a 1/8-rate charge-steering DFE integrated with a newly proposed Charge-Steering-Linear-Equalizer (CSLE). The proposed CSLE is explained qualitatively and quantitatively. The entire receiver chain consumes 2.9-mW running from a 0.9-V supply and can compensate for 14-dB channel loss at Nyquist-rate when processing 20-Gb/s data.

Multi-Rate Programmable Equalizer for M-PHY Serial Interface

A programmable continuous-time linear equalizer (CTLE) for multi-rate high speed serial interfaces (HSSI) is proposed in this paper. Our solution is compliant with the multi-data rates of 1.45, 2.9, 5.8 and 11.6 Gbps specified by the M-PHY rev.4 HSSI standard for mobile applications. The specifications of the input short-term total jitter STTJ are analyzed demystifying the M-PHY standard. A STTJ generator which is implemented using the behavioral description language cadence verilog-A, is also proposed in order to optimize the CTLE operation and to improve the simulation time for jitter tolerance testing. The transfer function and the power consumption are programmable according to the data-rate and to the frequency band of the STDJ. The CTLE topology was designed and simulated in TSMC CMOS 65 nm process with 1.2 V supply voltage and dissipates 12.5 mA for 11.66 Gbps and the FoM is 0.12 pJ/bit/dB. The output deterministic jitter is around 2.5 ps for 11.66 Gbps.

A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects

This article presents a quarter-rate source-synchronous PAM-4 receiver for energy-efficient chip-to-module communication. A novel single-stage multiple peaking continuous-time linear equalizer (MP-CTLE) using feedback enabled multiple peaking scheme for both high-frequency equalization (HF-EQ) and low-frequency equalization (LF-EQ) is proposed to improve the BER performance and overall energy efficiency. The LF-EQ of the MP-CTLE eliminates the need for many DFE taps in SR/VSR applications to save power and area. A 1-tap feedforward equalizer (FFE) is used to further compensate for the high-frequency loss. We also use a ring oscillator based wide bandwidth phase-locked loop (WBW-PLL) as the multiphase clock generator (MPCG) in the clock and data recovery loop to save power with acceptable phase accuracy. Fabricated in 40-nm CMOS technology, the prototype receiver chip achieves error-free operation up to 52 Gb/s PAM-4 with superior bit efficiency of 0.126pJ/bit/s/dB while compensating 7.3-dB channel loss at 13GHz. With the proposed single-stage MP-CTLE, the receiver extends the error-free operation from PRBS-7 to PRBS-9. The BER bathtub curve at $10^{-6}$ is improved from 0.018 UI to around 0.1 UI.