Continuous-time Linear Equalizer Research Articles

A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS

A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver (TRx) designed in a 28-nm complementary metal-oxide-semiconductor (CMOS) process is presented in this article. A voltage-mode (VM) driver featuring a 4-tap reconfigurable feed-forward equalizer (FFE) is employed in the quarter-rate transmitter (TX). The half-rate receiver (RX) incorporates a continuous-time linear equalizer (CTLE), a 3-stage high-speed slicer with multi-clock-phase sampling, and a clock and data recovery (CDR). The experimental results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board (COB) assembly. The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV (upper-eye), 31 mV (mid-eye), and 28 mV (lower-eye) with an output amplitude of 353 mV single-ended. The recovered 14 GHz clock from the RX exhibits random jitter (RJ) of 469 fs and deterministic jitter (DJ) of 8.76 ps. The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ, at bit-error rate (BER) of 10−5 (0.53 UI). The power dissipation of TX and RX are 125 and 181.4 mW, respectively, from a 0.9-V supply.

A 16 Gb/s serial link transceiver with active inductor based CTLE and 3-tap DFE in 12-nm FinFET CMOS

This paper presents a 16 Gb/s serial link transceiver implemented in 12-nm FinFET CMOS technology. The equalization scheme incorporates a 3-tap feed-forward equalizer (FFE) in the transmitter, a 5-stage continuous time linear equalizer (CTLE), and a 3-tap decision-feedback equalizer (DFE) in the receiver. The proposed FFE structure offers small step size and flexible configuration. The CTLE's high-frequency boost is augmented by integrating an active inductor. A high-accuracy clock and data recovery (CDR) circuit, featuring a cascaded two-step analog phase interpolator (PI) structure, is developed for data retiming. Occupying a footprint of 0.26 mm × 0.63 mm per lane, the transceiver test chip is packaged in a flip chip ball grid array (FC-BGA) module. Measurement results demonstrate a horizontal eye opening of 38 % at a bit error rate (BER) of 10−12 over a channel with 28 dB loss at 8 GHz. Moreover, the power consumption is 68.85 mW per lane at 16 Gb/s.

A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology

A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology

A 12.5 Gb/s 1.38 mW all-inverter-based optical receiver with multi-stage feedback TIA and continuous-time linear equalizer

A 12.5 Gb/s 1.38 mW all-inverter-based optical receiver with multi-stage feedback TIA and continuous-time linear equalizer

Differential Evolution-Based Adaptation Algorithm for Multistage Continuous-Time Linear Equalizer

Differential Evolution-Based Adaptation Algorithm for Multistage Continuous-Time Linear Equalizer

A High Efficiency 14–28 Gb/s Tunable Receiver Analog Front-End in 65 nm CMOS Technology

This work presents a tunable receiver analog front-end (AFE) circuit, capable of achieving data rates between 14 Gb/s and 28 Gb/s. The circuit is implemented using the TSMC 65 nm CMOS technology. The circuit incorporates a continuous-time linear equalizer (CTLE), a transimpedance amplifier (TIA) and an output buffer. A [Formula: see text]-boosted technique is employed within the CTLE for bandwidth and gain enhancement, while the TIA leverages a super source follower (SSF) structure to combat parasitic output node issues. By adjusting the tunable structures in the circuit, the proposed AFE can achieve variable DC gain at 14 GHz. Simulation results reveal that the AFE can compensate for the channel loss at the 14 GHz Nyquist frequency, delivering eye diagram spreads of approximately 0.85 UI and 0.78 UI at 14 Gb/s and 28 Gb/s, respectively. The complete post-simulation layout area is only 0.0026[Formula: see text]mm2. Operating with a power consumption of 10.5[Formula: see text]mW, the AFE exhibits an exceptional FoM of 11.8 pJ/bit/dB.

A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement

A 10–26 Gb/s energy-efficient receiver incorporating a dual-feedback nested loop clock and data recovery circuit (DF-CDR) is proposed. Combining a direct modulation path on voltage-controlled oscillator (VCO) and phase interpolator (PI)-based phase rotator inside a phase locked loop (PLL), it improves high-frequency jitter tolerance by 0.15 UI. An edge-first equalization scheme is proposed to reduce power and hardware overhead of decision feedback equalizers. Meanwhile, it facilitates adaptive equalization of continuous time linear equalizer, and background offset calibration of the receiver frontend. A three-stage latch comparator is adopted to enable high-speed direct feedback equalizer. By applying PRBS-31 test pattern through a 32 dB loss channel, the receiver is error-free and features the best energy efficiency of 103 fJ/b/dB at 26 Gb/s.

A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology

With the rapid development of Ethernet, the research of new high-speed optical communication technology is getting more and more attention. The external modulation technique is unaffected by frequency chirp makes the fiber optic system more stable. Meanwhile, the small driving voltage and efficient area of the electro-absorption optical modulator make the electro-absorption modulator(EAM) driver more widely used. The signal emission by the optical module is critically dependent on the performance of the EAM driver. This article presents a 50 Gb/s four pulse amplitude modulation(PAM-4) EAM driver in 28-nm CMOS. The proposed EAM driver consists of a continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA), a preamp, and an output stage circuit. Linearity is enhanced by using inverter-based structures in the proposed CTLE, VGA, and preamp. The source-degenerated resistors are adopted by CTLE and VGA to provide equalization and improve linearity. Additionally, shunt peaking inductors are used to extend the bandwidth. To provide a large output swing, the output stage adopts the cascode structure. Measured results demonstrate that: the EAM driver has 23.12 GHz bandwidth and 2.14 V output voltage swing at 50-Gb/s. The EAM driver consumes 226 mW power while having an active area of 0.26 mm2.

A 0.90-Tb/s/in 1.29-pJ/b Wireline Transceiver With Single-Ended Crosstalk Cancellation Coding Scheme for High-Density Interconnects

This article presents a four-lane single-ended transceiver featuring a crosstalk-canceling coding scheme, Fibonacci coding (FC), which supports high-speed transmission over high-density parallel inter-chip channels. In-depth experiments and analyses are presented to evaluate FC’s performance, and the results suggest that the FC scheme can provide significant near-end and far-end crosstalk cancellation (XTC) while maintaining high channel density for high-speed multi-lane inter-chip links. By simulation, an effective data rate of 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 8.5 Gb/s is enhanced to 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 18 Gb/s by FC for a four-channel link. The transceiver, including an FC codec, a feed-forward equalizer (FFE), and a continuous-time linear equalizer (CTLE), is implemented in 28-nm CMOS. It achieves a data rate density of 0.90 Tb/s/in with an energy efficiency of 1.29 pJ/b and an area of 0.004 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> /lane. The performance of FC is measured on 3.8-mil-spaced four-lane coupled printed circuit board (PCB) microstrips. For the 2-in wires, the peak-to-peak jitter of the received eye is reduced by 45.0% at 10 Gb/s, and the horizontal aperture is broadened to 0.58 UI at a bit error rate (BER) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula> 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-12}$</tex-math> </inline-formula> by activating the FC scheme and equalizers. For the 5-in wires, the jitter is reduced by 43.9% and the eye is 0.47-UI-wide at 8.5 Gb/s. And for the 8-in wires, the jitter is reduced by 49.0% and the eye is 0.43-UI-wide at 6 Gb/s.

A 25-Gb/s dual-loop adaptive continuous-time linear equalizer based on power comparison for the optical transmitter

A new dual-loop adaptive continuous-time linear equalizer (CTLE) based on power comparison is proposed to realize a 25-Gb/s optical transmitter. The adaptive CTLE controls the high-frequency gain peaking of the loop regulation path to match the configuration of the boost factor for improved adaptive capacity and power comparison accuracy. A digital control method is used to operate two power comparison loops with different running cycles for increased power comparison accuracy and reduced power consumption of the adaptive control process. Measurements of an adaptive CTLE fabricated by the 0.18 μm SiGe BiCMOS process showed that it was able to compensate for the coaxial cables with an attenuation of at least −11.4 dB @12.5 GHz. The adaptive CTLE only consumed 22.8 mW from a 1.8-V power supply, resulting in energy efficiency at 0.91 pJ/b.

A 3–5 GHz, 108fs-RMS jitter, clock receiver circuit for time-interleaved ADCs with a sampling rate of 4 GS/s

This paper presents a high-speed, low-jitter, and high-precision clock receiver circuit (CLKRX) for time-interleaved ADCs with a sampling rate of 4 GS/s operating in the 3–5 GHz frequency range. The CLKRX circuit is composed of a continuous-time linear equalizer (CTLE) and a duty-cycle corrector (DCC). The CTLE featuring active feedback, negative Miller capacitance, and source-follower feedback is capable of enhancing the bandwidth, and improving the quality of the high-speed clock. Whereas the 3–5 GHz DCC module contains a common-mode voltage correction circuit and a wideband amplifier that corrects the input signal's duty cycle ranging from 20% to 80%. A second-order duty-cycle detection circuit is used in the feedback loop, which significantly improves the range and accuracy of duty-cycle correction and greatly reduces duty cycle jitter.The clock receiver circuit proposed in this paper was verified in a 28 nm CMOS process, and the test results show that the output duty cycle is corrected to 50 ± 0.1% within the input duty cycle range of 20–80% (3–5 GHz).

Asynchronous Sampling-Based Hybrid Equalizer

An equalizer architecture based on asynchronous sampling is described. The circuit implementation is a hybrid feed-forward equalizer (FFE) using three digital postcursor taps realized via level-crossing samplers (LCSs) and inverter-based delays. Utilizing a current mode logic (CML)-based summer stage, an analog main tap and digital postcursor taps are combined into an inductively tuned resistor load. With a 0.67-mV-rms simulated output-referred noise, the FFE has better noise performance than a conventional continuous-time linear equalizer (CTLE) and a slicer/latch-based decision feedback equalizer (DFE) circuit. Moreover, it exhibits very good linearity and group delay performance suitable for an equalizer. Using inverter-based delays enables area efficiency as well as the capability to tune the delay across process voltage and temperature (PVT) variations. Since the FFE is an event-driven combinational logic based on the incoming data, it does not require synchronous sampling coming from a high-speed clock and data recovery (CDR), and it is advantageous for high-speed and multirate operation as its power consumption scales with the data rate. Fabricated in 40-nm CMOS technology, the hybrid FFE achieves energy per bit of 2.7 pJ/bit with a 20-dB Nyquist insertion loss link at the 28.57-Gb/s nonreturn to zero (NRZ) data rate.

A PAM4 transceiver design scheme with threshold adaptive and tap adaptive

To meet the demand of low bit error rate and high bandwidth for high-speed links, a reliable 112 Gb/s four-level pulse amplitude modulation (PAM4) transceiver design scheme with adaptive threshold voltage and adaptive decision feedback equalizer is proposed in this paper. In this scheme, three continuous time linear equalizers (CTLEs) at the front end of receiver are used to compensate the high-frequency, mid-frequency and low-frequency signals, respectively, and the variable gain amplifier (VGA) and saturation amplifier (SatAmp) are used to scale the signal amplitude. In addition to the three data samplers, four auxiliary samplers are also used for threshold adaptation. The sign-sign least mean squares algorithm uses the offset between the data sampler and the auxiliary sampler at the receiver side to drive the auxiliary reference voltage to converge to the signal constellation level, thus ensuring that the eye diagram of the PAM4 received signal has equal spacing and a constant signal–noise ratio for the three eyes in the vertical direction. In addition, the adaptive DFE for PAM4 signaling allows the transceiver to better adapt to the channel and thus achieve better equalizer performance. The simulation results show that the PAM4 transceiver design can compensate up to 25 dB of channel loss with an average eye height of 59.6 mv and an average eye width of 0.27 UI at a bit error rate of 10−12 under the condition of 3-tap feedforward equalizer (FFE) transmitter.

A 14-Gb/s VCSEL Driver in 65-nm CMOS With a Power-Efficient Driving Structure for Particle Physics Experiments

This paper presents the design and test results of a 14-Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) driving ASIC based on a commercial 65 nm CMOS technology with a novel power efficient driving structure. This VCSEL driver consists of an input equalizer stage, a pre-driver stage, an output driver stage, and their bias circuits. The equalizer stage uses the continuous time linear equalizer (CTLE) structure to compensate for the high-frequency attenuation. The pre-driver stage is composed of two stage limiting amplifiers with a shared inductor structure. The proposed output driver stage adopts a novel complementary-modulated method to fully utilize the currents in both branches of the conventional differential structure. In addition, a self-adjusting CTLE pre-emphasis with edge peaking function is combined in the output stage to improve the bandwidth and boost the falling edge of the output current signal. This VCSEL driving ASIC has been fully tested with a real VCSEL load, and the wide-open optical eye diagrams have been captured at a 14-Gbps data rate with a power consumption of 44 mW. The peak-to-peak jitter of the 14-Gbps optical eye diagram is 15.8 ps with a random jitter of 3.02 ps.

A Continuous-Time Linear Equalizer With Ultrafine Gain Adjustment Achieving 0.3-dB DC-Gain Step and 0.9-dB Peaking-Gain Step

A four-stage continuous-time linear equalizer (CTLE) in a 28-nm CMOS process is presented. The proposed CTLE provides peaking gain at a Nyquist frequency of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula> 16 GHz, as well as mid-frequency boosting for low-frequency channel-loss compensation. An ultrafine gain-tuning scheme employing an extra positive-feedback path is proposed and analyzed, which enables both a large gain-tuning range and fine gain-tuning steps. The dc gain covers a wide range from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 3.81 to 11.29 dB with a step size of less than 0.3 dB, and the peaking gain at Nyquist frequency can be adjusted from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 3.52 to 13.48 dB with a step size of less than 0.9 dB, while providing a large boost range of 13 dB. The CTLE consumes 32-mW power from a 0.9-V supply.

An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS

A noise-immune spatial-delta coding (SDC) scheme is proposed for single-ended multi-lane links. The SDC technique allows differential sensing of single-ended PAM2 signals for high signal integrity while still achieving the same pin efficiency as the 8b9b data bus (DBI) scheme, providing high compatibility with conventional DDR interfaces. The SDC encoding/decoding functions are implemented with simple XOR gates to minimize power and latency overhead. Continuous-time linear equalizers in the receiver compensate for distortions in incoming pseudodifferential signals with high tolerance on dynamic common-mode switching associated with the SDC operation. An 8b9b SDC transceiver prototype array composed of nine data channels and a differential clock channel has been fabricated in 28-nm CMOS technology for demonstration. The transceiver array achieves a 77.44 Gb/s aggregate data rate with 9 wires at 9.68 Gbaud/s. The bit error rate is measured to be less than 1e-12 while consuming 4.9 pJ/b from a 1.25-V supply.

A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET

Demand for increased data rates in serial link transceivers calls for innovative architectures capable of overcoming impairments such as limited channel bandwidth (BW) and stringent jitter specifications. This article presents a receiver front-end (RXFE) architecture that supports multicarrier signaling to provide a ~3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> relaxation in clock jitter requirements. A total of 40 Gb/s data rate is supported by three 4-GS/s bands with baseband (BB) four-level pulse amplitude modulation (PAM4) and mid-band (MB) and high-band (HB) 16-state quadrature amplitude modulation (QAM16) on 4- and 8-GHz orthogonal carriers, respectively. The RXFE uses three per-band optimized continuous-time linear equalizers (CTLEs) to partially equalize the in-band channel loss and four-way time-interleaved 7-b pipelined-successive approximation register (SAR) analog-to-digital converters (ADCs). Tight band spacing is achieved with tolerable inter-channel interference (ICI) using resettable integrators in the receiver segments. Fabricated in a 22-nm fin field-effect transistor (FinFET), the proposed 40-Gb/s multicarrier RXFE can tolerate up to 1.6-psrms jitter and achieve a bit error rate (BER) < 10−5 operating over a channel with 20-dB loss at 10 GHz when combined with an off-chip one-tap digital ICI canceller. The ADC-based front-end achieves 3.05-pJ/bit power efficiency, including all the front-ends, ADC, and clocking power.

A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes

A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude modulation (4-PAM) with −8.2-dBm sensitivity is presented in support for optical receivers required in the next-generation intra-data center links. A proposed three-stage TIA is comprised of a shunt-feedback stage followed by digitally programmable continuous-time linear equalizers (CTLEs) and a variable gain amplifier (VGA). Broadband low-noise design is achieved by having the first stage with much lower bandwidth (BW) followed by the proposed BW recovering CTLEs. A low-power design is supported by the inverter-based single-ended architecture with a single-ended-to-pseudo-differential conversion in the last stage. TIA’s BW extension is further supported by optimizing the photodiode-to-receiver (PD-to-RX) interconnect and utilizing several inductive peaking techniques. It achieves 63-dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> gain, 32-GHz BW, and an average input-referred current noise density of 16.9 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sqrt {\text {Hz}}$ </tex-math></inline-formula> while operating at 0.9-V supply and consuming 47-mW power. Opto-electrical measurements are performed on a co-packaged prototype comprised of identical proposed TIAs in CMOS with combinations of various commercial PDs and PD-to-RX interconnect lengths confirming 112-Gb/s 4-PAM reception meeting pre-forward error correction (FEC) symbol error rate (SER) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.8 \times 10 ^{-4}$ </tex-math></inline-formula> without any post-equalization.

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

This work proposes a RX front-end structure, which is used for channel equalization of 25Gb/s high-speed links. This design includes two parts, linear equalizer and decision feedback equalizer. Linear equalizer consists of the variable gain amplifier, the continuous-time linear equalizer and the output buffer, which provide 19dB peaking gain around the Nyquist frequency. The half-rate decision feedback equalizer with one speculative tap is cascaded after the buffer to eliminate residual inter-symbol interference. The circuit layout occupies an area of 0.005mm2 designed in 65nm CMOS, the power consumption of which is 96mW under 1.2V power supply. The design is used to equalize the FR-4 backplane channel, of which the insertion loss reaches 35dB at 12.5GHz. The result shows that both the voltage margin and time margin of the receiver signal reach 171mV and 0.61UI at the BER of 10-12, respectively.

A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation

This brief presents an 8-to-16-Gb/s referenceless receiver with a stochastic continuous-time linear equalizer (CTLE) adaptation. The proposed stochastic CTLE gain selector (SCGS) achieves a maximum horizontal eye margin and avoids sub-optimal settling by utilizing sequential edge and data samples. The proposed SCGS detects the optimum CTLE coefficient with the weighted summation of the histograms obtained under various data patterns and channel conditions. The stochastic CTLE adaptation shares the deserialized edge and data samples used for the CDR. Therefore, it does not require additional hardware in the analog domain, achieving low power consumption. The golden weight of the SCGS is obtained through an epsilon-constraint weight searching algorithm. A prototype chip fabricated in 28-nm CMOS technology occupies an active area of 0.029 mm2. The measured CTLE adaptation behavior shows that the maximum eye width is achieved with the proposed SCGS. The prototype chip achieves BER over a channel with 14-dB loss at 8 GHz and consumes 17.7 mW at 16 Gb/s, exhibiting a power efficiency of 1.1 pJ/b.