Continuous-time Filter Research Articles

How to Avoid the Curse of Dimensionality: Scalability of Particle Filters with and without Importance Weights

Particle filters are a popular and flexible class of numerical algorithms to solve a large class of nonlinear filtering problems. However, standard particle filters with importance weights have been shown to require a sample size that increases exponentially with the dimension $D$ of the state space in order to achieve a certain performance, which precludes their use in very high-dimensional filtering problems. Here, we focus on the dynamic aspect of this “curse of dimensionality” (COD) in continuous-time filtering, which is caused by the degeneracy of importance weights over time. We show that the degeneracy occurs on a time scale that decreases with increasing $D$. In order to soften the effects of weight degeneracy, most particle filters use particle resampling and improved proposal functions for the particle motion. We explain why neither of the two can prevent the COD in general. In order to address this fundamental problem, we investigate an existing filtering algorithm based on optimal feedback control that sidesteps the use of importance weights. We use numerical experiments to show that this feedback particle filter (FPF) by [T. Yang, P. G. Mehta, and S. P. Meyn, IEEE Trans. Automat. Control, 58 (2013), pp. 2465--2480] does not exhibit a COD.

Parameter estimation for partially observed linear stochastic system

This paper is concerned with the problem of parameter estimation for a partially observed linear stochastic system. The state estimator is obtained by using the continuous-time Kalman linear filter...

Analog Statistical Design for Manufacturability Using Linear and Nonlinear Response

Manufacturing yield, overkill, and defect level can limit the feasibility of analog circuits in SoCs. The conventional method of handling process and environmental variation is to assign the design margin such that the design meets specifications at several processes and environmental corners. However, checking only a few extreme corners limits performance more than the more rigorous statistical approach of computing manufacturing and quality figure of merit. On the other hand, the statistical approach requires transistor level simulation of hundreds or thousands of samples, not just a few corners, and hence is very time-consuming. This paper gives a way to sidestep the problem by characterizing each of many samples of building blocks once at the transistor level. The building blocks are scalable so that statistics are preserved when a building block is adjusted to the requirement of a higher level design. Many design scenarios may be rapidly explored by assembling and scaling the building block samples without SPICE simulation. A continuous-time low-pass filter design example is used to extract the requirements of the building block approach. The requirements include a method to assemble building blocks (biquad element for the example) into a filter design while preserving the statistics that would have been extracted by simulation of the entire filter at the transistor level. The assembly method for both linear and nonlinear response is proposed.

Fully‐differential flipped‐source‐follower low‐pass analogue filter in CMOS 28 nm bulk

This study presents a novel low-pass continuous-time filter based on the voltage flipped-source-follower (SF). The filter efficiently operates in CMOS 28 nm and improves the SF filters state-of-the-art thanks to a dedicated circuit that operates in fully-differential fashion (instead of the pseudo-differential typically used in state-of-the-art SF filters) with a dedicated Common-Mode-Feedback circuit. Thus this work extends the application of the SF filtering stages to the nm-range technologies where threshold voltage (VTH) is only two times lower than the supply voltage (VDD) for what regards standard-process MOS transistors. In order to validate the design concept, the proposed filter has been designed in CMOS 28 nm technology. Extensive simulation results of a 131 MHz −3 dB frequency proof-of-concept second-order filter are proposed. The device consumes 510 µW power from a single 1 V supply-voltage. In-band integrated noise is 160 µVRMS and IIP3 is 19 dBm for 20 and 21 MHz input tones frequencies. Simulation results lead to 166 J−1 figure-of-merit, outperforming the analogue filter state-of-the-art.

Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters

This paper demonstrates a completely on-chip implementation of expansion and compression of continuous-time, wideband, analog pulses. The input pulse is fed to a continuous-time filter whose delay exceeds the pulse duration. Once the pulse is completely inside the filter, it is stored in the form of the filter’s state-variables, which can completely reconstruct the pulse. Instantaneously decreasing or increasing the filter’s bandwidth at this instant results in the output pulse being expanded or compressed, respectively, compared with when the bandwidth is unchanged. A 1.6 mm2, 370 mW, 0.13 $\mu \text{m}$ prototype has a delay filter whose bandwidth can be switched between 870 and 472 MHz. It achieves $1.8\times $ pulse expansion and $1.7\times $ pulse compression with an rms error which is 33 dB below the peak-peak pulse amplitude.

Nano-scale area-efficient Gm–C filters using MOS capacitors

ABSTRACTThe rapid growth of scaling and integration of nano-scale digital circuits is hardly tracked by the analog circuits which require additional passive components for fabrication. Mixed-signal Complementary Metal Oxide Semiconductor (CMOS) technologies are released with some delays after digital CMOS technologies, due to the issues related to integration of analog components. This urges the designers to consider using the same digital CMOS technology for integration of advanced analog circuits like continuous-time filters. As such, this article presents an area-efficient Gm–C filter made from MOS devices only. Instead of classical metal–insulator–metal capacitors, the proposed filter exploits the available compact-size MOS devices as capacitor. This modification makes the filter design compatible to any low-cost digital CMOS process. Besides, the 3-dB cut-off frequency of the filter can now be changed by varying the size of MOS capacitors. The effectiveness of the new design approach is validated through simulation of a fifth-order elliptic low-pass filter with a cut-off frequency of 1 MHz in 90-nm CMOS technology. The new filter dissipates around 115 µW from a 1.0 V power supply, and the sensitivity of its cut-off frequency is kept as low as 6% over various process and temperature corners.

CMOS analog filter design using the Proportional Source Transconductances Integrator

This work assesses the applicability of a compact CMOS current-mode companding integrator in the design of analog continuous-time filters with high linearity. The companding integrator is based on the proportionality between the source transconductances of the input and output MOS transistors and is independent of the inversion level of the devices. The circuit has been designed in CMOS 130 nm technology with approximately 90 μm2 total active area including biasing elements. According to simulation results the integrator performs a useful frequency bandwidth of up to 4 MHz and a third order intermodulation distortion smaller than −47 dB for input amplitudes ranging from 100 nA to 1 μA. The small and large signal responses and the third order intermodulation, among other features, have also been analyzed through simulation for a fourth order low-pass filter and a sixth order bandpass filter. Performance is compared with a CMOS log-domain integrator and filter.

Designing an Inverter-based Operational Transconductance Amplifier-capacitor Filter with Low Power Consumption for Biomedical Applications

The operational transconductance amplifier-capacitor (OTA-C) filter is one of the best structures for implementing continuous-time filters. It is particularly important to design a universal OTA-C filter capable of generating the desired filter response via a single structure, thus reducing the filter circuit power consumption as well as noise and the occupied space on the electronic chip. In this study, an inverter-based universal OTA-C filter with very low power consumption and acceptable noise was designed with applications in bioelectric and biomedical equipment for recording biomedical signals. The very low power consumption of the proposed filter was achieved through introducing bias in subthreshold MOSFET transistors. The proposed filter is also capable of simultaneously receiving favorable low-, band-, and high-pass filter responses. The performance of the proposed filter was simulated and analyzed via HSPICE software (level 49) and 180 nm complementary metal-oxide-semiconductor technology. The rate of power consumption and noise obtained from simulations are 7.1 nW and 10.18 nA, respectively, so this filter has reduced noise as well as power consumption. The proposed universal OTA-C filter was designed based on the minimum number of transconductance blocks and an inverter circuit by three transconductance blocks (OTA).

Networked continuous-time filtering for quadratically inner-bounded time-delay systems with multirate sampling

This paper addresses the networked H∞ filtering problem for time-delay systems with quadratically inner-bounded nonlinearities, where the different output sub-vectors of the systems are sampled respectively by sensor groups with different sampling periods (i.e., multirate sampling or MRS). The multirate sampled data are transmitted to a filter through multiple communication channels with network-induced packet dropouts and time-varying transmission delays. Considering MRS’s asynchronous behavior, we propose a matching mechanism to synchronize the successfully transmitted sampled data of the nonlinear system and the sampled data of a filter. Based on the matched sampled data, two types of new continuous-time filters are presented to estimate the objective signal of the nonlinear system. In view of the fact that the lifting technique may fail to model the nonlinear system, the resultant filtering error systems are modeled as continuous-time nonlinear systems with several sawtooth delays. By the Lyapunov-Krasovskii functional approach, some sufficient conditions are obtained to ensure that the filtering error systems are stable with a prescribed H∞ performance level, and the design methods of the two filters are given. Finally, a numerical example shows the effectiveness of our proposed methods.

Continuous-time analog filter with passband constant IIP3 based on common-gate amplifier

This paper presents an analog filter based on Rauch biquadratic cell. The filter exploits an improved analog stage that makes linearity performance uniform over the entire pass-band frequency region. All feedback analog filters suffer from poor linearity when the input tones frequency is in close proximity to the closed-loop poles frequency, where loop-gain reduces. This often forces an overdesign with higher current (higher power consumption) and/or higher overdrive voltages (lower dynamic range) in order to meet the linearity specifications over the whole filter pass-band region. The hereby proposed Rauch scheme resolves such a binding issue without power increasing and having the same IIP3 at low and at high frequency (up to the filter closed-loop poles frequency). Hence the linearity performance is in first approximation independent on the input tones bandwidth. In order to validate the hereby proposed idea a 4th-order 25 MHz −3 dB bandwidth pseudo-differential filter has been designed and simulated in CMOS 28 nm technology. The prototype consumes 820 µW from 1 V supply voltage and has 15 and 13 dBm IIP3 at 5 and 6 and 20 and 21 MHz input tones, respectively.

Nonlinear Sequence Transformation-Based Continuous-Time Wavelet Filter Approximation

Time-domain synthesis is used to design continuous-time filters when their time-domain response for a given excitation is known. A case in point is the design of a continuous-time wavelet filter which requires a chosen wavelet as the filter’s impulse response. A key step in the design of a continuous-time wavelet filter is the approximation of its transfer function to a proper rational function. This approximation problem is addressed using methods that can be broadly categorized as closed-form methods and numerical optimization methods. While optimization methods are very effective, closed-form solutions are attractive because they are easy to design. In this work, we propose variants of nonlinear sequence transformation (a closed-form method) that obtain proper rational approximations of wavelet functions which are stable and also perform better in terms of mean square error when compared to those obtained by other closed-form methods. It is shown that the model-order reduction of the proposed variants leads to either similar or better performance compared to \(L_2\) optimization method. These variants are also shown to act as good starting points for optimization methods that use local search routines.

Low-Power ${G}_{{m}}{-}C$ Filter Employing Current-Reuse Differential Difference Amplifiers

This paper deals with the design of low-power high-performance continuous-time filters. The proposed operational transconductance amplifier architecture employs current-reuse differential difference amplifiers in order to produce more power-efficient ${G}_{{m}}{-}{C}$ filter solutions. To demonstrate this, a sixth-order low-pass Butterworth filter was designed in a 0.18- $\mu\text{m}$ CMOS, achieving a 65-MHz −3-dB frequency, an in-band input-referred third-order intercept point of 12 dBm, and an input-referred noise density of 40 nV/Hz1/2, while only consuming 8.07 mW from a 1.8-V supply and occupying a total chip area of 0.21 mm2 with a power consumption of only 1.19 mW per pole.

Formula omitted] filtering for descriptor systems with strict LMI conditions

In this paper, the problem of H∞ filtering for descriptor systems with strict linear matrix inequalities (LMIs) is investigated. The necessary and sufficient conditions for the solvability and the expression of the solution are obtained for both continuous-time and discrete-time descriptor systems. The proposed continuous-time filters extend the results presented by Xu and Lam (2006) by removing semi definite conditions and introducing new formulation for the filter parameters which does not require determination of intermediate variables. For discrete-time descriptors, differing from existing methods that provide sufficient conditions only, two necessary and sufficient conditions are introduced. New proposed design methods propose less conservative results comparing with existing works. Two numerical examples are presented to demonstrate the applicability of the proposed methods.

Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA

An open-source simulator to design and implement circuits and systems, replicating the results from the Field Programmable Analog Array (FPAA) is presented here. The fundamental components like the transistors, amplifiers and floating gate devices have been modeled based on the EKV model with minimal parameters. Systems including continuous-time filters and the analog front-end of a speech processing system have been built from these basic components and the simulation results and the data from the FPAA are shown. The simulated results are in close agreement to the experimental measurements obtained from the same circuits compiled on the FPAA fabricated in a 350 nm process.

Discrete-Time Filter Synthesis using Product of Gegenbauer Polynomials

A new approximation for designing continuous- time and discrete-time low-pass filters, presented in this pa- per, based on the product of Gegenbauer polynomials, pro- vides the ability of more flexible adjustment of passband and stopband responses. The design is achieved taking into ac- count a prescribed specification, leading to a better trade-o amongthemagnitudeandgroupdelayresponses. Manywell- known continuous-time and discrete-time transitional filter based on the classical polynomial approximations (Cheby- shev, Legendre, Butterworth) are shown to be special cases of proposed approximation method.

21.5 dBm‐IIP3 22.5 MHz fourth‐order follow‐the‐leader‐feedback analogue filter

A 4th-order single-loop follow-the-leader-feedback (FLFB) low-pass continuous-time filter in CMOS 0.18 µm is hereby presented. The outstanding FLFB noise behaviour is exploited to allocate the power consumption to linearity performance. The low-pass filter prototype features 22.5 MHz−3 dB frequency, 21.5 dBm-IIP3 and 76 µVRMS input referred in-band integrated noise. The overall power consumption is 7 mA from a 1.8 V supply voltage. The signal-to-noise ratio for a −40 dB-total harmonic distortion is 69 dB.

A Functional Composition Approach to Filter Sharpening and Modular Filter Design

Designing and implementing systems as an interconnection of smaller subsystems is a common practice for modularity and standardization of components and design algorithms. Although not typically cast in this framework, many of these approaches can be viewed within the mathematical context of functional composition. This paper re-interprets and generalizes within the functional composition framework one such approach known as filter sharpening, i.e. interconnecting filter modules which have significant approximation error in order to obtain improved filter characteristics. More specifically, filter sharpening is approached by determining the composing polynomial to minimize the infinity-norm of the approximation error, utilizing the First Algorithm of Remez. This is applied both to sharpening for FIR, even-symmetric filters and for the more general case of subfilters that have complex-valued frequency responses including causal IIR filters and for continuous-time filters. Within the framework of functional composition, this paper also explores the use of functional decomposition to approximate a desired system as a composition of simpler functions based on a two-norm on the approximation error. Among the potential advantages of this decomposition is the ability for modular implementation in which the inner component of the functional decomposition represents the subfilters and the outer the interconnection.

10 Gb/s adaptive receive-side merged near-end and far-end crosstalk cancellation circuitry in 65 nm CMOS

Crosstalk between neighboring channels can have significant impact on system bit-error rate (BER) as serial I/O data rates scale above 10 Gb/s. This paper presents receive-side circuitry which merges the cancellation of both near-end and far-end crosstalk (NEXT/FEXT) and can automatically adapt to different channel environments and variations in process, voltage, and temperature. NEXT cancellation is realized with a novel 3-tap FIR filter which combines two traditional FIR filter taps and a continuous-time band-pass filter IIR tap for efficient crosstalk cancellation, with all filter tap coefficients automatically determined via an on-die sign---sign least-mean-square (SS-LMS) adaptation engine. FEXT cancellation is realized by coupling the aggressor signal through a differentiator circuit whose gain is automatically adjusted with a power-detection-based adaptation loop. A prototype fabricated in a general purpose 65-nm CMOS process includes the adaptive NEXT and FEXT circuitry, along with a continuous-time linear equalizer (CTLE) to compensate for frequency-dependent channel loss. Enabling the crosstalk cancellation circuitry while operating at 10 Gb/s over coupled 4-in FR4 transmission line channels with NEXT and FEXT aggressors opens a previously closed eye and allows for a 0.2 UI timing margin at a BER = 10ź9. Total power including the NEXT/FEXT crosstalk cancellation circuitry, CTLE, and high-speed output buffer is 34.6 mW, and the core circuit area occupies 0.3 mm2.

A novel Nth-order voltage-mode universal filter based on CMOS CFOA

With the development of integrated circuits, the fully integrated continuous time filter has been focused widely. A Nth-order universal filter based on Current Feedback Operational Amplifier (CFOA) is proposed. Compared with available circuits, the proposed circuit using less components (2n CFOAs, n capacitors, and 3n resistors) can realize the universal filter functions without changing circuit configuration, and the operating frequency of proposed filter circuit is at least 10MHz. All of capacitors in proposed circuit are grounded, this is another benefit from integration point of view. PSPICE simulations have been carried out using 0.18μm CMOS technology, and sensitivity analysis of proposed Nth-order low-pass filter circuit is completed.

Switched-Mode Operational Amplifiers and Their Application to Continuous-Time Filters in Nanoscale CMOS

We introduce a new class of feedback amplifiers, called switched-mode operational amplifiers (SMOAs) that address voltage-swing limitations of classical feedback amplifiers in scaled CMOS technologies. By exploiting the increased timing resolution available in scaled CMOS, SMOAs encode analog signal information in the time domain and provide near-rail-to-rail output-signal swing, high output-stage efficiency and better linearity. A 4th-order, 70 MHz continuous-time active-RC Butterworth filter is presented in 65 nm CMOS to demonstrate the advantages of SMOAs. The filter consumes 25.4 mW from a 0.6 V supply and achieves 55.8 dB peak SNDR while operating at a full-scale of 873 mV ppd. Thanks to SMOAs, the full-scale (73% of the 0.6 V supply voltage) and the bandwidth are respectively, a 2.5 × and 6.2 × improvement over other state-of-the-art low-voltage filters.