Continuous-time ΔΣ Modulator Research Articles

A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing

A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing

Hybrid integrators with predictive overload estimation for analog computers and continuous-time ΔΣ modulators

Abstract. Continuous-time integrators are a central component in ΔΣ modulators, in analog computers, and general analog signal processing. If several integrators are interconnected, scaling plays an important role: In analog computers, scaling is performed with respect to the machine unit (MU). In ΔΣ modulators, scaling is performed in such a way that at maximum input signal the allowable dynamic range of no integrator is exceeded. In both cases the scaling is a compromise limiting the dynamic range. For analog computers, it was proposed early on to extend the dynamic range by hybrid integrators. Here, an analog range overflow is processed digitally and the analog integrator is reduced to its permissible operating range within the machine unit interval. While in earlier proposals for hybrid integrators only the subsequent integrator stage processes the overflow and works with reduced analog values, our hybrid integrator can process the overflow directly, with the analog reset process being continuous-time. In the case of highly dynamical input signals and transients, analog overload handling is further improved by a prediction of the overload that includes the currently applied input signal in the calculation. For example, with continuous-time ΔΣ modulators, overload of the analog integrator can be reliably avoided.

A Capacitor-Reused 2b/Cycle Active-Passive Second-order Noise-Shaping SAR ADC

In this manuscript, a novel 2nd-order noise-shaping successive-approximation register (NS-SAR) analog-to-digital converter (ADC) is introduced for potential application in wideband continuous-time (CT) ΔΣ modulators. The proposed NS-SAR employs a special active-passive residue filter that reuses the capacitor of the reference digital-to-analogue converter (DAC) of the SAR. Compared to the conventional NS-SAR that uses an active residue filter, the proposed approach saves one power-hungry amplifier and four replica DACs. An asynchronous 2b/cycle conversion scheme is adopted for a reduced excessive loop delay (ELD) in the modulator. Transistor-level simulations in a 65nm CMOS process are presented to demonstrate the principle of the proposed NS-SAR.

A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/f noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> ) same as the sampling frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/ √{Hz} input-referred noise density, 1.9 μV offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> . With -110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique.

A Capacitance to Digital Converter Using Continuous Time ΔΣ Modulator for Microphone-Based Auscultation

This paper presents a novel Capacitance to Digital Converter (CDC) for ultra-low power microphone-based auscultation. The proposed CDC utilizes a continuous-time Capacitance to Voltage Converter (CVC) inside a delta-sigma (ΔΣ) modulator to perform the Delta operation. The multi-bit feedback in the embedded CVC with a capacitive DAC reduces the voltage swing at its output, which permits a larger capacitive signal gain and relaxes the noise requirements. The multi-bit feedback also allows a larger signal swing at the CVC output, and improves the dynamic range. The proposed CDC was fabricated in 0.18 μm CMOS technology and was measured with a commercial capacitive sensor. Measurement results demonstrate that the proposed CDC consumes only 6.3 nJ while achieving 13-bit resolution. This corresponds to a FoM of 0.84 pJ/conversion-step.

Improved Continuous-Time Delta-Sigma Modulators With Embedded Active Filtering

Continuous-time ΔΣ modulators used in wireless transceivers need to digitize small desired signals that are accompanied by large out-of-band interferers. In such applications, it is desirable that the CTΔΣM have a low-pass signal transfer function whose bandwidth can be specified. Many architectures present themselves as potential candidates to realize such filtering-CTΔΣMs. This work investigates these threads and concludes that a CTΔΣM with an embedded Rauch filter is a compelling design choice. The theory is supported by measurement results from a filtering-CTΔΣM test chip that achieves a peak SNDR of 76.7dB in a 1MHz signal bandwidth. Measurements demonstrate improved power efficiency and out-of-band linearity when compared to prior art.

A High Dynamic Range ΔΣ Modulator using Anti-Windup Compensated Integrators

This paper presents a continuous-time (CT) ΔΣ modulator employing an anti-windup (AW) feedback control technique to mitigate integrator overload and maintain an acceptable performance simultaneously. The proposed technique accommodates a large dynamic range and can be applied to multi-loop modulators. According to simulations, using AW augmentations, for a 50% higher dynamic range (DR), integrators do not overload and the signal-to-distortion-ratio (SNDR) drops less than 1dB from the maximum SNDR of the modulator.

A 15-μW 105-dB 1.8-Vpp Potentiostatic Delta-Sigma Modulator for Wearable Electrochemical Transducers in 65-nm CMOS Technology

Wearable electrochemical sensors represent a point of convergence between lab-on-a-chip technologies, advanced microelectronics and connected intelligence. These three pillars establish data flow from analytes present in body fluids, to the Cloud infrastructures towards next-generation personal healthcare and wellness. The design of electrode-embedded interfacing instrumentation in advanced CMOS technology nodes offer a number of challenges spanning from ultra-low power operation, small footprint, sufficient general purpose operability, and compatibility with advanced CMOS technology nodes. This paper presents a low-power frontend with extended amperometric dynamic range and wide potentiostatic range for electrochemical transducers with Delta-Sigma (ΔΣ) digital output. The second-order single-bit continuous-time ΔΣ modulator architecture reuses the electrochemical cell dynamic characteristics for quantization noise shaping, while the differential potentiostat enables 1.8 V pp of control range under single 1.2-V supply. The proposed frontend has been integrated in TSMC 65-nm CMOS technology occupying 0.07 mm 2 . From electrical and electrochemical tests, the micro potentiostat achieves a Signal-to-Distortion-and-Noise of 80 dB with 15-μW power consumption and a combined multi-scale dynamic range of 105 dB.

A CT ΔΣ modulator using 4-bit asynchronous SAR quantizer and MPDWA DEM

The current paper aims at presenting a low-power second-order input-feedforward continuous-time (CT) ΔΣ modulator for audio applications. It uses a 4-bit asynchronous successive approximation register (SAR) quantizer which is more power efficient than the usual flash converter. Furthermore, in order for the proposed modulator to reduce the noise stemming from the component mismatches of the feedback digital-to-analog converter (DAC), it applies a modified partitioned data weighted averaging (MPDWA) dynamic element matching (DEM) so as to solve the DWA DEM-in band-tone problem. Despite the implementation of MPDWA, no further delay caused in the ΔΣ feedback loop compared to the conventional DWA. The implementation of the above-mentioned DEM in the modulator and required reforms have led to a new design with better performance and favorable figure of merit (FOM) value. The designed modulator which is simulated using 0.18 µm CMOS technology, achieves 84.17 dB SNDR for 20 kHz signal bandwidth and dissipates 54 µW while its FOM is obtained about 143 fJ/conv.-step.

Design and simulation of a DAC-calibrated 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS

This paper presents transistor-level design of a continuous-time delta-sigma modulator with 150 MHz bandwidth in 28 nm CMOS process with 1.4/0.85 V supply. Architectural-level design tradeoff for t...

A Continuous-Time Delta-Sigma Modulator for Biomedical Ultrasound Beamformer Using Digital ELD Compensation and FIR Feedback

This paper presents the design of a continuous-time ΔΣ modulator (CTDSM) to be used in an ultrasound beamformer for biomedical imaging. To achieve better resolution, the prototype modulator operates at 1.2 GHz. It incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. A digitally controlled reference-switching matrix, combined with the data-weighted averaging (DWA) technique, results in a delay-free feedback path. A multi-bit FIR feedback DAC, along with its compensation path, is used to achieve lower clock jitter sensitivity and better loop filter linearity. The modulator achieves 79.4 dB dynamic range, 77.3 dB SNR, and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies an area of only 0.16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 6.96 mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.

A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS

This paper presents a continuous-time ΔΣ modulator targeted at optimizing power efficiency for input bandwidth exceeding 50 MHz. Delay in the feedback path is carefully minimized and traditional techniques for DAC mismatch correction and excess loop delay compensation are both replaced with digital schemes. Power is also minimized by relaxing loop filter BW requirements and using a power efficient opamp topology. The modulator achieves 73 dB dynamic range (DR) in 80 MHz BW while consuming 23 mW. The peak SNR is 70 dB and the peak SNDR is 67.5 dB, resulting in FOMs of 168 dB and 163 dB based on DR and SNDR, respectively.

A Programmable 0.7–2.7 GHz Direct $\Delta \Sigma$ Receiver in 40 nm CMOS

This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.

Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering

Continuous-time ΔΣ modulators (CTDSM) used in wireless systems need to process signals in the presence of interferers. Peaking in the Signal Transfer Function of a conventional design necessitates a higher in-band dynamic range to accommodate interferers. A filter up front solves this problem at the expense of increased power dissipation and degraded linearity of the signal chain. Embedding the filter in the modulator achieves the same objective in a power efficient manner, while improving out-of-band linearity and reducing active area. However, having the filter inside a ΔΣ loop can be problematic with respect to stability. We show that such a system can be stabilized in a robust manner without extra hardware. Measurements of a CTDSM (signal BW = 2 MHz), with a built-in VGA (0 to 18 dB) and a second order Butterworth filter (4 MHz cutoff), show that the in-band/out-of-band IIP 3 improves by about 3/10 dB when compared to the filter-CTDSM cascade, and achieves a similar dynamic range and consumes 25% lower power.

A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW

This paper presents a single loop, third order continuous time ΔΣ modulator with an internal 4 bit quantizer sampled at 500 MHz with only an oversampling ratio of 10. Since multi-bit operation commonly suffers from DAC non-linearities, and dynamic element matching is ineffective at low oversampling, an alternative auxiliary DAC linearization is proposed for ΔΣ modulators. The unit element mismatches are digitally estimated based on a cross correlation of a binary test signal with the modulator output and represent the measured DNL of DAC1. The corresponding INL is calculated and stored in an 15×8 lookup-table which is applied to the 8 bit auxiliary DAC to linearize DAC1. Moreover, a design centering approach for amplifier finite gain bandwidth compensation within the loop filter is presented which allows for large bandwidth mismatch with negligible effect on loop filter stability. This results in a robust architecture over temperature, supply, and excess loop delay variations. The presented ΔΣ modulator achieves an SNDR of 67.5 dB, DR of 72 dB, and SFDR of 79 dB over a 25 MHz bandwidth and is implemented in a 1.2 V, 90 nm CMOS process. The modulator occupies an active area of 0.19 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and has a power consumption of 8.5 mW. It achieves a figure of merit of 88 fJ/conv-step which is one of the best published for multi-bit ΔΣ modulators.

Efficient technique for excess loop delay compensation in continuous‐time ΔΣ modulators

A highly digital technique is proposed for excess loop delay (ELD) compensation in multi-bit continuous-time ΔΣ modulators. A digitally controlled reference switching matrix is used to replace the power-hungry signal adder and extra DAC driving the quantiser, which are commonly used in ELD compensation. With the proposed technique, the feedback DAC is embedded in the quantiser and implemented by a few switches. Thus, it allows low-voltage and low-power operation.

Continuous-Time &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\Delta \Sigma $&lt;/tex&gt;&lt;/formula&gt; Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC

Conventional continuous-time ΔΣ modulators that use non-return-to-zero (NRZ) feedback DACs suffer from distortion due to intersymbol interference (ISI) and are sensitive to clock jitter. Using a return-to-zero (RZ) DAC solves the problem of ISI, but exacerbates clock jitter sensitivity. The clock jitter sensitivity of an NRZ DAC can be reduced using a switched-capacitor (SC) DAC, but the large peak-to-average ratio of the DAC waveform degrades modulator linearity. In this work, we introduce the switched-capacitor return-to-zero (SCRZ) DAC, which combines the low clock jitter sensitivity of the SC DAC with the low distortion of an RZ DAC. The efficacy of the SCRZ principle is borne out by measurement results from a modulator that achieves a DR/SNR/SNDR of 87.1/84.5/82.3 dB in a 2 MHz bandwidth while dissipating 16.5 mW from a 1.8-V supply. The converter, designed in a 0.18- μm CMOS technology, reduces clock jitter sensitivity by 28 dB when compared with a traditional RZ DAC.

An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT $\Delta \Sigma$ Modulator Dissipating 13.7-mW

A novel low power compact loop filter using a single amplifier biquad (SAB) network is presented for continuous-time (CT) delta-sigma (ΔΣ) modulators. This new technique reduces power consumption and die area by minimizing the number of active elements and simplifying the modulator topology. The new SAB network has a transfer function (TF) zero, which implements a local feedforward (FF) path in system-level diagram. By having a local FF branch embedded in the SAB network, the FF branches to the summing block in the SAB based feedforward modulator topology is reduced to half the number of FF branches in the conventional topology. Consequently, the SAB based modulator utilizes a switch-capacitor (SC) adder replacing the commonly used CT adder and the sample & hold blocks in the conventional architecture. The SAB based loop filter with reduced FF branches simplifies the design and implementation of the high-order continuous-time ΔΣ modulator. The proposed loop filter is a general filter, which can be used for both high and low oversampling ratios (OSRs). A 4th-order low pass continuous-time ΔΣ modulator is designed and implemented in 130 nm process to confirm the effectiveness of the proposed techniques. Within a 7.2 MHz signal bandwidth, the measured dynamic range and SFDR of this prototype IC are 80 dB and 83.1 dB, respectively, and the total power consumption of 13.7 mW.

A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer

This paper presents a continuous-time (CT) <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\Delta \Sigma$</tex></formula> modulator using a VCO-based internal quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue canceling quantizer (RCQ) and mitigates the impact of its nonlinearity by spanning only a small region of the VCO's V-to-F nonlinear tuning curve. The order of noise shaping is increased by placing the RCQ in a continuous-time <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\Delta \Sigma$</tex></formula> loop. Using only a first order loop filter, the proposed <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\Delta\Sigma$</tex></formula> modulator achieves second order noise shaping. Fabricated in a 90-nm CMOS process, the prototype modulator occupies an active area of 0.36 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$^2$</tex></formula> and consumes 16 mW power. It achieves a peak SNDR of 78.3 dB in 10-MHz bandwidth and an SFDR of better than 85 dB when clocked at 600 MHz. The figure of merit of the modulator is 120 fJ/conv-step.

Sensitivity Analysis of Continuous-Time $\Delta \Sigma$ ADCs to Out-of-Band Blockers in Future SAW-Less Multi-Standard Wireless Receivers

The increasing demand for integrating multiple wireless services in one multi-standard handset, exemplified by the software-defined radio (SDR) model, calls for digitizing wireless receivers in a quest for flexibility. Radio-frequency (RF) front-end and analog baseband filters need to be exchanged for digital processing at the expense of a highly challenging analog-to-digital converter (ADC) specifications. In this paper, the sensitivities of continuous-time (CT) delta-sigma (ΔΣ) ADCs, which are candidate architectures for multi-standard receivers and SDRs, to out-of-band (OOB) blockers at the ADC input are investigated. This analysis addresses the problems and performance limitations that can result from large OOB blockers appearing at the input of CT ΔΣ modulators in a digitized multi-standard receiver. Analysis and discussions given in different sections of the paper are verified by CT system-level simulations.