Context Switching Research Articles

Interopérabilité avec Objective Caml

We present in this paper the evolution of the inter-operability needs of the functional languages, illustrated in Objective Caml by our tools and multi-languages applications. First of all we describe the inherent difficulties of the low-level interfaces of communication for memory management and context switching. Then we define a new code generator, called O'Jacare, designed to facilitate interoperation between Java and Objective Caml through their object models. O'Jacare defines a basic IDL (Interface Definition Language) for classes and interfaces description to communicate from Objective Caml to Java. The adaptation of O'Jacare to .NET, called O'Jacare.net, improves communication between Objective Caml and C# via this common runtime.

Supporting Demanding Hard-Real-Time Systems with STI

Software thread integration (STI) is a compilation technique which enables the efficient use of an application's fine-grain idle time on generic processors without special hardware support. With STI, a primary function is automatically interleaved with a secondary function to create a single implicitly multithreaded function which minimizes context switching and, hence, both improves performance and also offers very fine-grain concurrency. In this work, we extend STI techniques to address two challenges. First, we reduce response time for interrupts or other high-priority threads by introducing polling servers into integrated threads. Second, we enable integration with long host threads, expanding the domain of STI. We derive methods to evaluate the response time for threads in systems with and without these new integration methods. We demonstrate these concepts with the integration of various threads in a sample hard-real-time system on a highly-constrained microcontroller. We use an inexpensive 20 MHz AVR 8-bit microcontroller to generate monochrome NTSC video while servicing a high-speed (115,2 kbaud) serial communication link. We have built and tested this system, achieving graphics rendering speed-ups of 3.99/spl times/ to 13.5/spl times/.

Extinction in multiple contexts does not necessarily make extinction less vulnerable to relapse

Three fear-conditioning experiments with rat subjects examined the effects of extinction in multiple contexts on a final relapse (renewal) effect that occurred when the extinguished fear cue was tested in a new context (Experiments 1 and 3) or in the context in which fear conditioning had first occurred (Experiment 2). Rats that received extinction in three contexts demonstrated more fear during extinction than rats that received the same number and temporal distribution of extinction trials in one context; extinction was partially lost with each context switch. Although extinction in multiple contexts thus had an impact on extinction behavior, it did not reduce the size of the final renewal effect. Fear during extinction was occasionally positively correlated with fear during final testing, but the two were never negatively correlated. The results suggest that extinction in multiple contexts does not necessarily weaken fear renewal, and that extinction procedures that generate high levels of responding in extinction do not necessarily make extinction learning less context-specific.

View and Space Management on Large Displays

This article describes the canvas portal framework that facilitates the development of alternative view-based space-management techniques on large displays. Implementations of the framework provide layout management, context switching, and space creation. The canvas portals are alternative views of display canvas areas where interacting with the portal's interior is equivalent to interacting with the depicted display area. To illustrate the generality of the canvas portals concept, we've instantiated a representative sample of existing large-display interaction techniques within the canvas portal design space, and developed several interaction techniques that address some of the challenges in new ways.

Scalable precision cache analysis for preemptive scheduling

Accurate timing analysis is key to efficient embedded system synthesis and integration. Caches are needed to increase the processor performance but they are hard to use because of their complex behavior especially in preemptive scheduling. Current approaches use simplified assumptions or propose exponentially complex analysis algorithms to bound the cache related preemption delay at a context switch. Existing approaches consider only direct mapped caches or propose non conservative approximation for set associative caches.In this paper we propose a novel cache related preemption delay analysis for set-associative instruction caches where the designer can adjust the analysis precision by scaling the problem complexity. Furthermore, this precise preemption delay analysis is integrated into a scheduling analysis to determine the response time of tasks accurately. In experiments we evaluate this tradeoff between analysis precision and analysis time. The results show an improvement of 22%-71% in analysis precision of cache related preemption delay and 5%-21% in response time analysis compared to previous conservative approaches.

Weaves: A Framework for Reconfigurable Programming

This paper presents a language independent runtime framework--called Weaves--for object based composition of unmodified code modules that enables selective sharing of state between multiple control flows through a process. Furthermore, the framework allows dynamic instantiation of code modules and control flows through them. In effect, weaves create intra-process modules (similar to objects in OOP) from code written in any language. Applications can be built by instantiating Weaves to form Tapestries of dynamically interacting code. The framework enables objects to be arbitrarily shared--it is a true superset of both processes as well as threads, with code sharing and fast context switching time similar to threads. Weaves does not require any special support from either the language or application code--practically any code can be weaved. Weaves also include support run-time loading and linking of object modules enabling the next generation of highly dynamic applications. This paper presents the elements of the Weaves framework and its implementation on the Linux platform over source-code independent ELF object files. The current implementation has been validated over Sweep3D, a benchmark for 3D discrete ordinates neutron transport (Koch et al. Trans. Am. Nucl. Soc. 65 (198) [1992]), and a user-level port of the Linux 2.4 family kernel TCP/IP protocol stack.

Fully associative cache partitioning with don't care bits for real-time applications

The usage of cache memories in time-critical applications has been limited as caches introduce unpredictable execution behavior. Cache partitioning techniques have been developed to reduce the impact of unpredictability owing to context switch effects. However, partitioning reduces the cache size available for each task resulting in capacity related cache misses. This paper introduces a fully associative cache architecture for multi-tasking applications where effective partition sizes are increased by tag compression in the cache. The proposed scheme uses a few don't care cells in its least significant bits of the tag to aggregate multiple tag entries into a single entry. The experimental results indicate that the proposed scheme is context switch resilient when eight different real-time benchmarks use the cache concurrently. Further, this cache architecture requires less time and less energy to perform tag table search compared to contemporary fully associative caches of the same size.

Hardware/software co-design for virtual machines

Hardware/software co-design and (re)configurable computing with field programmable gate arrays (FPGAs) are used to create a highly efficient implementation of the Java virtual machine (JVM). Guidelines are provided for applying a general hardware/software co-design process to virtual machines, as are algorithms for context switching between the hardware and software partitions. The advantages of using co-design as an implementation approach for virtual machines are assessed using several benchmarks applied to the implemented co-design of the JVM. It is shown that significant performance improvements are achievable with appropriate architectural and co-design choices. The co-designed JVM could be a cost-effective solution for use in situations where the usual methods of virtual machine acceleration are inappropriate.

Utilization Bounds for EDF Scheduling on Real-Time Multiprocessor Systems

The utilization bound for earliest deadline first (EDF) scheduling is extended from uniprocessors to homogeneous multiprocessor systems with partitioning strategies. First results are provided for a basic task model, which includes periodic and independent tasks with deadlines equal to periods. Since the multiprocessor utilization bounds depend on the allocation algorithm, different allocation algorithms have been considered, ranging from simple heuristics to optimal allocation algorithms. As multiprocessor utilization bounds for EDF scheduling depend strongly on task sizes, all these bounds have been obtained as a function of a parameter which takes task sizes into account. Theoretically, the utilization bounds for multiprocessor EDF scheduling can be considered a partial solution to the bin-packing problem, which is known to be NP-complete. The basic task model is extended to include resource sharing, release jitter, deadlines less than periods, aperiodic tasks, non-preemptive sections, context switches, and mode changes.

Hardware–software co-simulation of bus-based reconfigurable systems

One of the most flexible and modular approaches to reconfigurable systems is a bus-based approach. In order to get realistic performance estimates of these systems, detailed modeling of the processor as well as the bus and memory hierarchy is required. In addition, when coupling one or more reconfigurable units with a superscalar, out-of-order issue, load/store RISC CPU using the on-chip system bus, there are issues relating to cache coherency that need to be addressed. We have developed a cycle accurate co-simulator that uses a ‘C’ model of the processor and HDL models of the bus and reconfigurable units. We have also made modifications to the CPU pipeline to allow for non-cacheable accesses to the reconfigurable unit. This is reported in the paper. We have used this simulator to look at (a) The speedup obtained for two examples, namely, matrix multiplication and Lempel–Ziv compression, (b) the speedup obtained when there is a context switch from one application to the other and full reconfiguration is employed and (c) speedup obtained with partial reconfiguration. These results are reported in the paper.

An adaptive cryptographic engine for internet protocol security architectures

Architectures that implement the Internet Protocol Security (IPSec) standard have to meet the enormous computing demands of cryptographic algorithms. In addition, IPSec architectures have to be flexible enough to adapt to diverse security parameters. This article proposes an FPGA-based Adaptive Cryptographic Engine (ACE) for IPSec architectures. By taking advantage of FPGA technology, ACE can adapt to diverse security parameters on the fly while providing superior performance compared with software-based solutions. In this paper, we focus on performance issues. A diverse set of private-key cryptographic algorithms is utilized to demonstrate the applicability of the proposed cryptographic engine. The time performance metrics are throughput and key-setup latency. The latency metric is the most important measure for IPSec where a small amount of data is processed per key and key context switching occurs repeatedly. We are not aware of any published results that include extensive key-setup latency results.

Asynchronous software thread integration for efficient software

The overhead of context-switching limits efficient scheduling of multiple concurrent threads on a uniprocessor when real-time requirements exist. Existing software thread integration (STI) methods reduce context switches, but only provide synchronous thread progress within integrated functions. For the remaining, non-integrated portions of the secondary threads to run and avoid starvation, the primary thread must have adequate amounts of coarse-grain idle time (longer than two context-switches). We have developed asynchronous software thread integration (ASTI) methods which address starvation through the efficient use of coroutine calls and integration. ASTI allows threads to make independent progress efficiently and reduces the number of context switches needed through integration.Software-implemented protocol controllers are crippled by this problem; the primary thread "bit-bangs" each bit of a message onto or off of the bus, leaving only fragments of idle time shorter than a bit time. This fragmented time may be too short to recover through context switching, so only the primary thread can execute during message transmission or reception, slowing the secondary threads and potentially making them miss their deadlines. ASTI simplifies the implementation of embedded communication protocols on low-cost, moderate speed (1 - 100 MHz, 8- and 16-bit) microcontrollers. We demonstrate ASTI by replacing a standard automotive communication protocol controller (J1850) with software and generic hardware. Secondary thread performance improves significantly when compared with a traditional interrupt-based software approach.

Balancing register allocation across threads for a multithreaded network processor

Modern network processors employ multi-threading to allow concurrency amongst multiple packet processing tasks. We studied the properties of applications running on the network processors and observed that their imbalanced register requirements across different threads at different program points could lead to poor performance. Many times application needs demand some threads to be more performance critical than others and thus by controlling the register allocation across threads one could impact the performance of the threads and get the desired performance properties for concurrent threads. This prompts our work.Our register allocator aims to distribute available registers to different threads according to their needs. The compiler analyzes the register needs of each thread both at the point of a context switch as well as internally. Compiler then designates some registers as shared and some as private to each thread. Shared registers are allocated across all threads explicitly by the compiler. Values that are live across a context switch can not be kept in shared registers due to safety reasons; thus, only those live ranges that are internal to the context switch can be safely allocated to shared registers. Spill can cause a context switch. and thus, the problems of context switch and allocation are closely coupled and we propose a solution to this problem. The proposed interference graphs (GIG,BIG,IIG) distinguish variables that must use a thread's private registers from those that can use shared registers. We first estimate the register requirement bounds, then reduce from the upper bound gradually to achieve a good register balance among threads. To reduce the register needs, move insertions are inserted at program points that split the live ranges or the nodes on the interference graph. We show that the lower bound is reachable via live range splitting and is adequate for our benchmark programs for simultaneously assigning them on different threads. As our objective, the number of move instructions is minimized.Empirical results show that the compiler is able to effectively control the register allocation across threads by maximizing the number of shared registers. Speed-up for performance critical threads ranges from 18 to 24% whereas degradation for performance of non-critical threads ranges only from 1 to 4%.

An optimal algorithm for minimizing run-time reconfiguration delay

Reconfiguration delay is one of the major barriers in the way of dynamically adapting a system to its application requirements. The run-time reconfiguration delay is quite comparable to the application latency for many classes of applications and might even dominate the application run-time. In this paper, we present an efficient optimal algorithm for minimizing the run-time reconfiguration (context switching) delay of executing an application on a dynamically adaptable system. The system is composed of a number of cameras with embedded reconfigurable resources collaborating in order to track an object. The operations required to execute in order to track the object are revealed to the system at run-time and can change according to a number of parameters, such as the target shape and proximity. Similarly, we can assume that the applications comprising tasks are already scheduled and each of them has to be realized on the reconfigurable fabric in order to be executed.The modeling and the algorithm are both applicable to partially reconfigurable platforms as well as multi-FPGA systems. The algorithm can be directly applied to minimize the application run-time for the typical classes of applications, where the actual execution delay of the basic operations is negligible compared to the reconfiguration delay. We prove the optimality and the efficiency of our algorithm. We report the experimental results, which demonstrate a 2.5--40% improvement on the total run-time reconfiguration delay as compared to other heuristics.

ECEM: an event correlation based event manager for an I/O-intensive application

In Internet servers that run on general purpose operating systems, network subsystems and disk subsystems cooperate with each other for user requests. Many studies have focused on optimizing the data movement across the subsystems to reduce data copying overhead among kernel buffers, a network send buffer and a disk buffer. When data are moved across the subsystems, events such as read requests and write requests for data movement are also delivered across the subsystems by the servers and the operating system. However, there have been fewer studies on the optimization of event delivery across the subsystems. In conventional operating systems, an event from a disk subsystem is delivered to a network subsystem regardless of the status of the network subsystem. If the network subsystem is not ready for data sending, the execution of the server will be blocked, which causes scheduling and context switching overheads. This non-contiguous execution will incur deficiencies such as avoidable process blocking, context switching, cache pollution and long response time. To alleviate the deficiencies, we have developed inter-subsystem event delivery mechanisms that define event dependencies among the subsystems involved. We define an event correlation based on the happened-before relation. We propose deferred event delivery (DED) and disk-to-network splicing (DNS) to suppress scheduling and context switching during I/O request processing. We performed experiments on Linux 2.4 and the experimental results show that the number of context switching is reduced by up to 20% and server data transmit rate is improved by 4.0–8.1%.

Real-Time Garbage Collection for a Multithreaded Java Microcontroller

We envision the upcoming of microcontrollers and systems-on-chip that are based on multithreaded processor kernels due to the fast context switching ability of hardware multithreading. Moreover we envision an extensive market for Java-based applications in embedded real-time systems. This paper introduces two new garbage collection algorithms that are dedicated to real-time garbage collection on a multithreaded Java microcontroller. Our garbage collector runs in a thread slot in parallel to real-time applications. We show that our algorithms require only about 5–10% of the processor time for an effective garbage collection concerning our real-time benchmarks.

A model for computerized procedures based on flowcharts and success logic trees

A model for plant operating procedure based on flowchart and success logic tree has been developed. The tasks in procedures are classified into orthogonal actions and checks, which play the role of building units of the flowchart as well as an execution unit of procedures. Arrows relate actions and checks to indicate proper workflow. An action or a check is further decomposed into basic instructions considering function allocation between man and computer, characteristics of tasks, etc. N-out-of-M operator combines the instructions within a success logic tree. The flowchart and the tree are comprehensible, transparent, and dynamic. Computers support operators to execute the instructions. The effort to make the tree in allowable states is the driving force for an action or check to be executed successfully. This model improves understandings of procedures, minimizes context switching, and maximizes the usage of computers. Finally a computer based procedure complying with the model was implemented and evaluated with procedures after reactor trip.

Exploring Cognitive Strategies for Integrating Multiple-View Visualizations

Visualizing information is useful for finding patterns in complex data sets, but little research has been done on how people understand multiple-view visualizations (multiple visualizations presented simultaneously). A controlled experiment was performed using different combinations of visualizations and different task types as independent variables, and qualitative and quantitative data were collected. To collect the data psychological tests, logs of the participants' interaction, eye-tracking equipment, and video recordings were used. This paper reports a portion of the results from this experiment. Main findings include that, contrary to what was suggested in previous literature, the time cost for switching between different types of visualizations (context switching) may not be significant, and that displaying the data using the same type of visualization may cause interference. Orthogonal combinations appear to aid users in finding and recognizing patterns, and focusing attention and analogical reasoning on spatial relationships may be important cognitive abilities for the given tasks.

Fast and Time-Accurate Cosimulation with OS Scheduler Modeling

Hardware/Software cosimulation is the key process to shorten the design turn around time. We have proposed a novel technique, called virtual synchronization, for fast and time accurate cosimulation that involves component simulators running concurrently and interacting with each other. In this paper, we further extend the virtual synchronization technique with OS modeling for the case where multiple software tasks are executed under the supervision of a real-time operating system. The OS modeler models the RTOS overheads of context switching and tick interrupt handling as well as preemption behavior. While maintaining the timing accuracy to an acceptable level below a few percents, we could reduce the simulation time drastically compared with existent conservative approaches by removing the need of time synchronization between simulators. It is confirmed with a preliminary experiment on a multimedia example that consists of four real-life tasks.

Context Switching in a Run-Time Reconfigurable System

A distinguishing feature of reconfigurable computing over rapid prototyping is its ability to configure the computational fabric on-line while an application is running. Conventional reconfigurable computing platforms utilize commodity FPGAs, which typically have relatively long configuration times. Shrinking the configuration time down to the nanosecond region opens possibilities for rapid context switching and virtualizing the computational resources. An experimental context-switching FPGA, called the CSRC, has been created by BAE Systems, and gives researchers the opportunity to explore context-switching applications. This paper presents results obtained from constructing both control-driven and data-driven context switching applications on the CSRC device, along with unique properties of the run-time and compile-time environment.