Contention Management Research Articles

Graph Representation Learning for Contention and Interference Management in Wireless Networks

Graph Representation Learning for Contention and Interference Management in Wireless Networks

Handling hierarchy in cloud data centers: A Hyper-Heuristic approach for resource contention and energy-aware Virtual Machine management

For cloud data centers, a performant yet energy-efficient operation is critical for service quality and experience. The growing demand for cloud-based services has led to the development of large-scale hierarchical data center structures, characterized by horizontal expansion and vertical hierarchy, leading to challenges in managing Virtual Machines (VM) at a granular level. The hierarchical arrangement can increase the risk of deployment failures, often stemming from inadequate computational resources on physical hosts, even when the cluster-level resources seem sufficient. While substantial work has gone into managing VMs at the physical host level, there remains a dearth of research under hierarchical data center configurations. To fill the research gap, we address the hierarchy in cloud data centers with a novel two-stage approach named VMM-HHGT, aiming at suppressing VM deployment failures, while balancing the energy consumption and computation resource contention. VMM-HHGT comprises a Hyper-Heuristic-assisted broker (VMM-HH), which can learn the workload patterns and hardware configurations to generate cluster-selection heuristics. An offline training process is incorporated for continuous heuristic evolution with zero overhead on decision-making. Besides, a Game-Theory-assisted hypervisor (GT) is designed for inter-host live VM migration for fine-grained balancing of energy consumption and resource contention. Extensive experiments with traces from real-world VMware data centers show that VMM-HHGT achieves a higher deployment success rate compared to the state-of-the-art approaches, with a well-situated performance in energy consumption and resource contention.

On Flow Control and Optimized Back-Off in Non-Saturated CSMA

Medium Access Control (MAC) main functions encompass contention for channel access, packet scheduling, error control, and data integrity. Channel contention is a collective function involving all stations in the network, while data integrity pertains to data flows of each individual station. We propose a design where contention related functions are separated from other data management functions. The hinge connecting contention and other data management functions is a flow control algorithm, aiming at guaranteeing stability of contention queues and load on the MAC channel. With reference to Carrier-Sense Multiple Access (CSMA), we define an analytical model of contention queues under non saturated traffic. An asymptotic analysis of the model for large number of stations yields a closed form of the optimal flow control rate. The insight gained from the model is used to design an adaptive flow control algorithm that guarantees throughput optimality for all values of the number of stations.

The origin of LYONs: A case study in financial innovation

The origin of LYONs: A case study in financial innovation

Popular Contention and Progressive Legal Repression in China

AbstractHow do state authorities cope with popular contention under authoritarian legality? Based on ethnographic fieldwork and legal repression cases in China, this article highlights that conflicting rules and signals regarding contention management can impose considerable pressure on governments and motivate them to respond cautiously, even though the prevailing rhetoric of law-based governance provides a convenient basis on which authorities can legitimize their coercive actions. This study further theorizes a discreet pattern of government reaction under authoritarian legality – progressive legal repression – that rests on bureaucratic processing to overcome political uncertainty and lower potential risks before formally employing criminal sanctions to achieve domination. Instead of directly using criminal penalties to deter unruly protesters and potential dissenters, the preferred state action is to induce them to engage in available legal-bureaucratic procedures. By reconceptualizing protesters’ claims and behaviour as unreasonable and signalling fulfilment of responsibilities, bureaucratic practices help officials to reduce the risks of damaging their political image and receiving disciplinary action, encouraging them to deploy legal repression. This study reveals more complicated dynamics of state repression under authoritarian legality and emphasizes the important effects of procedural practices on governmental responses and the regime's stability.

Adaptive Contention Management for Fine-Grained Synchronization on Commodity GPUs

As more emerging applications are moving to GPUs, fine-grained synchronization has become imperative. However, their performance can be severely impaired in case of frequent synchronization failures caused by high data contention. Differently from CPUs, GPUs own thousands of hardware threads and adopt single instruction multiple threads paradigm, making it impractical to deploy the CPU contention management mechanisms directly on GPUs. In this article, we design a Software Warp Controlling Framework (SWCF), which employs producer-consumer execution model and leverages GPU hardware barriers to dynamically control the execution of warps at runtime. On the basis of SWCF, we propose a contention management strategy to decrease frequent synchronization failures while avoiding the over-reducing of parallelism. We evaluate SWCF and the proposed strategy on commodity GPUs using a set of applications with fine-grained synchronization. The results show that on V100 GPU our contention management achieves a 4.7X speedup and outperforms the conventional GPU software backoff solution by 42% on average.

Implementation of abstract MAC layer under jamming

In the past decades, with the widespread implementation of wireless networks, such as the Internet of Things, an enormous demand for designing relative algorithms for various realistic scenarios has arisen. However, with the widening of scales and deepening of network layers, it has become increasingly challenging to design such algorithms when the issues of message dissemination at high levels and the contention management at the physical layer are considered. Accordingly, the abstract medium access control (absMAC) layer, which was proposed in 2009, is designed to solve this problem. Specifically, the absMAC layer consists of two basic operations for network agents: the acknowledgement operation to broadcast messages to all neighbors and the progress operation to receive messages from neighbors. The absMAC layer divides the wireless algorithm design into two independent and manageable components, i.e., to implement the absMAC layer over a physical network and to solve higher-level problems based on the acknowledgement and progress operations provided by the absMAC layer, which makes the algorithm design easier and simpler. In this study, we consider the implementation of the absMAC layer under jamming. An efficient algorithm is proposed to implement the absMAC layer, attached with rigorous theoretical analyses and extensive simulation results. Based on the implemented absMAC layer, many high-level algorithms in non-jamming cases can be executed in a jamming network.

Model-based reinforcement learning for router port queue configurations

Fifth-generation (5G) systems have brought about new challenges toward ensuring Quality of Service (QoS) in differentiated services. This includes low latency applications, scalable machine-to-machine communication, and enhanced mobile broadband connectivity. In order to satisfy these requirements, the concept of network slicing has been introduced to generate slices of the network with specific characteristics. In order to meet the requirements of network slices, routers and switches must be effectively configured to provide priority queue provisioning, resource contention management and adaptation. Configuring routers from vendors, such as Ericsson, Cisco, and Juniper, have traditionally been an expert-driven process with static rules for individual flows, which are prone to sub optimal configurations with varying traffic conditions. In this paper, we model the internal ingress and egress queues within routers via a queuing model. The effects of changing queue configuration with respect to priority, weights, flow limits, and packet drops are studied in detail. This is used to train a model-based Reinforcement Learning (RL) algorithm to generate optimal policies for flow prioritization, fairness, and congestion control. The efficacy of the RL policy output is demonstrated over scenarios involving ingress queue traffic policing, egress queue traffic shaping, and one-hop router coordinated traffic conditioning. This is evaluated over a real application use case, wherein a statically configured router proved sub optimal toward desired QoS requirements. Such automated configuration of routers and switches will be critical for multiple 5G deployments with varying flow requirements and traffic patterns.

A general purpose contention manager for software transactions on the GPU

The Graphics Processing Unit (GPU) is now used extensively for general purpose GPU programming (GPGPU), allowing for greater exploitation of the multi-core model across many application domains. This is particularly true in cloud/edge/fog computing, where multiple GPU enabled servers support many different end user services. This move away from the naturally parallel domain of graphics can incur significant performance issues. Unlike the CPU, code that is hindered from execution due to blocking/waiting on the GPU can affect thousands of threads, rendering the advantages of a GPU irrelevant and reducing a highly parallel environment down to a serial one in the worst case. In this paper we present a solution that minimises blocking/waiting in GPGPU computing using a contention manager that offsets memory conflicts across threads through thread re-ordering. We consider conflicts of memory not only to avoid corruption (standard for transactional memory) but also in the semantic layer of application logic (e.g., enforcing ordering to ensure money drawn from bank account occurs after all deposits). We demonstrate how our approach is successful across a number of industry benchmarks and compare our approach to the only other related solution. We also demonstrate that our approach is scalable in terms of thread numbers (a key requirement on the GPU). We believe this is the first work of its kind demonstrating a generalised conflict and semantic contention manager suitable for the scale of parallel execution found on a GPU.

Adaptive Hybrid Synchronization Primitives: A Reinforcement Learning Approach

The choice of synchronization primitive used to protect shared resources is a critical aspect of application performance and scalability, which has become extremely unpredictable with the rise of multicore machines. Neither of the most commonly used contention management strategies works well for all cases: spinning provides quick lock handoff and is attractive in an undersubscribed situation but wastes processor cycles in oversubscribed scenarios, whereas blocking saves processor resources and is preferred in oversubscribed cases but adds up to the critical path by lengthening the lock handoff phase. Hybrids, such as spin-then-block and spin-then-park, tackle this problem by switching between spinning and blocking depending on the contention level on the lock or the system load. Consequently, threads follow a fixed strategy and cannot learn and adapt to changes in system behavior. To this end, it is proposed to use principles of machine learning to formulate hybrid methods as a reinforcement learning problem that will overcome these limitations. In this way, threads can intelligently learn when they should spin or sleep. The challenges of the suggested technique and future work is also briefly discussed.

A large-scale nesting ring multi-chip architecture for manycore processor systems

The optical network on chip (ONoC) paradigm has emerged as a promising solution to multi-core/many-core processor systems for offering enormous bandwidth and low power consumption. As chip multiprocessors (CMPs) scale to unprecedented numbers of cores, the performance of next-generation CMPs will be bounded by the process yield and power density of single chip. In earlier work we proposed a multi-chip ONoC architecture that scales to large numbers of CMPs and delivers high performance in terms of delay and throughout. Building on that work, in this paper we propose an optimized architecture for integrating a large number of cores into chips with a novel control strategy, including a contention resolution scheme and a resource reservation scheme. The proposed control strategy is crucial to large scale ONoCs, because the resource reservation scheme ensures efficient wavelength allocation for the traffic while the contention management scheme is effective in reducing the impact of contentions. To sustain good performance and energy efficiency of large-scale ONoC, the topology is optimized to reduce the average transmission distance with minimum increase of power consumption. We evaluate the proposed architecture within a 1000-core processor system and compare it with CMesh and several previously proposed topologies with different control strategies. The simulation results show that, our new large-scale architecture can achieve better performance on throughput and delay.

Lock Contention Management in Multithreaded MPI

In this article, we investigate contention management in lock-based thread-safe MPI libraries. Specifically, we make two assumptions: (1) locks are the only form of synchronization when protecting communication paths; and (2) contention occurs, and thus serialization is unavoidable. Our work distinguishes between lock acquisitions with respect to work being performed inside a critical section; productive vs. unproductive . Waiting for message reception without doing anything else inside a critical section is an example of unproductive lock acquisition. We show that the high-throughput nature of modern scalable locking protocols translates into better communication progress for throughput-intensive MPI communication but negatively impacts latency-sensitive communication because of overzealous unproductive lock acquisition. To reduce unproductive lock acquisitions, we devised a method that promotes threads with productive work using a generic two-level priority locking protocol. Our results show that using a high-throughput protocol for productive work and a fair protocol for less productive code paths ensures the best tradeoff for fine-grained communication, whereas a fair protocol is sufficient for more coarse-grained communication. Although these efforts have been rewarding, scalability degradation remains significant. We discuss techniques that diverge from the pure locking model and offer the potential to further improve scalability.

Receiver based contention management: A cross layer approach to enhance performance of wireless networks

IEEE 802.11 standards adopted Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) to witness improvements in performance. Supporting, CSMA/CA is found to enhance performance when the transmitters are located within the neighborhood of one another. But, in the presence of multiple flows, the channel state creates an asymmetric distribution of throughput for different flows. Some flows experience high throughput while others suffer with insufficient bandwidth. To address this problem, Receiver Based Contention Management Scheme (RBCMS) approach is proposed based on collisions sensed by the receiver. RBCMS makes use of RRTS (Request for RTS) packets and also ensures that only the required number of RRTS packets are used to minimize the control overhead. In RBCMS, the current channel status is estimated by Success Ratio (SR) parameter by which contention and congestion are effectively controlled. The potential receiver sends SR value via packets and that is utilized by the sender to estimate network condition in and around the receiver.Accordingly, Contention Window (CW) size in MAC layer and the procedures of congestion avoidance and slow start in transport layer are intensified. The NS3 simulation results obtained in terms of fairness, throughput, delay etc. reveal the performance enhancements of RBCMS over Advanced Backoff Algorithm (ABA) and BEB.

$$\hbox {TM}^{2}$$ TM 2 C: a software transactional memory for many-cores

Transactional memory is an appealing paradigm for concurrent systems. Many software implementations of the paradigm were proposed in the past two decades for both shared memory multi-core systems and clusters of distributed machines. Chip manufacturers have however started producing many-core architectures, with low network-on-chip communication latencies and limited support for cache coherence, rendering existing transactional-memory implementations inapplicable. This paper presents $$\hbox {TM}^{2}\hbox {C}$$ , the first software transactional memory protocol for many-core systems, hence featuring transactions that are both distributed and leverage shared memory. $$\hbox {TM}^{2}\hbox {C}$$ exploits fast messages over network-on-chip to make accesses to shared data coherent. In particular, it allows visible read accesses to detect conflicts eagerly and incorporates the first distributed contention manager that guarantees the commit of all transactions. We evaluate $$\hbox {TM}^{2}\hbox {C}$$ on Intel, AMD and Tilera architectures, ranging from common multi-cores to experimental many-cores. We build upon new message-passing protocols, based on both software and hardware, which are interesting in their own right. Our results on various benchmarks, including realistic banking and MapReduce applications, show that $$\hbox {TM}^{2}\hbox {C}$$ scales well regardless of the underlying platform.

Contention-conscious, locality-preserving locks

Over the last decade, the growing use of cache-coherent NUMA architectures has spurred the development of numerous locality-preserving mutual exclusion algorithms. NUMA-aware locks such as HCLH, HMCS, and cohort locks exploit locality of reference among nearby threads to deliver high lock throughput under high contention. However, the hierarchical nature of these locality-aware locks increases latency, which reduces the throughput of uncontended or lightly-contended critical sections. To date, no lock design for NUMA systems has delivered both low latency under low contention and high throughput under high contention. In this paper, we describe the design and evaluation of an adaptive mutual exclusion scheme (AHMCS lock), which employs several orthogonal strategies---a hierarchical MCS (HMCS) lock for high throughput under high contention, Lamport's fast path approach for low latency under low contention, an adaptation mechanism that employs hysteresis to balance latency and throughput under moderate contention, and hardware transactional memory for lowest latency in the absence of contention. The result is a top performing lock that has most properties of an ideal mutual exclusion algorithm. AHMCS exploits the strengths of multiple contention management techniques to deliver high performance over a broad range of contention levels. Our empirical evaluations demonstrate the effectiveness of AHMCS over prior art.

A virtualization approach to develop middleware for ubiquitous high performance computing

In ubiquitous high-performance computing (UHPC), performing concurrent services is an important task of middleware. Because a major development effort is not easily achieved, isolating a virtual machine (VM) may be a helpful solution but will likely suffer from additional overhead costs. This challenge can also be resolved by reusing the device driver. However, these solutions are difficult to implement without the VM technique. In this study, we present an alternative approach to minimizing overhead and develop a middleware called userspace virtualized middleware (Uware). Instead of bypassing the VM, the proposed approach depends on userspace transparency and contention management to shift the VM concept into middleware. We introduce two strategies to enhance the system adaptively: comprehensive restructuring by simplifying the VM memory mechanism and implementing zero-copy buffers to reuse devices. The result demonstrates that Uware is feasible and could be applied in a broad variety of UHPC.

Supporting Time-Based QoS Requirements in Software Transactional Memory

Software transactional memory (STM) is an optimistic concurrency control mechanism that simplifies parallel programming. However, there has been little interest in its applicability to reactive applications in which there is a required response time for certain operations. We propose supporting such applications by allowing programmers to associate time with atomic blocks in the form of deadlines and quality-of-service (QoS) requirements. Based on statistics of past executions, we adjust the execution mode of transactions by decreasing the level of optimism as the deadline approaches. In the presence of concurrent deadlines, we propose different conflict resolution policies. Execution mode switching mechanisms allow the meeting of multiple deadlines in a consistent manner, with potential QoS degradations being split fairly among several threads as contention increases, and avoiding starvation. Our implementation consists of extensions to an STM runtime that allow gathering statistics and switching execution modes. We also propose novel contention managers adapted to transactional workloads subject to deadlines. The experimental evaluation shows that our approaches significantly improve the likelihood of a transaction meeting its deadline and QoS requirement, even in cases where progress is hampered by conflicts and other concurrent transactions with deadlines.

Toward Consistency of State in MMOGs Through Semantically Aware Contention Management

This paper presents a protocol which utilizes semantically aware, transaction-based contention management to reduce rollback and improve consistency in massively multiuser systems. Of particular relevance to massively multiplayer online games (MMOGs), the proposed system is adaptive and scales with respect to connection latency. This paper presents some background to the area of state management and consistency in MMOGs, and their impact on user quality of service. Our solution is then outlined in significant detail, with particular attention paid to the manner in which it maps to the structure of MMOGs. A simulation is demonstrated and its behaviors discussed in-depth in order to support arguments regarding the suitability of the protocol.

Modification of Cache Inclusion Property for Multicore Systems

The cache coherency protocol guarantees the validity of the cache block by keeping it with the latest updated contents. In multi-level cache memory hierarchy, the inclusion property enforces the lower layer cache to maintain the superset of its higher layer cache contents. The inclusion property has its benefits for cache coherence, but it may waste valuable cache blocks and bandwidth by invalidating the duplicated contents in the higher level cache. In this paper, a new cache contention management scheme is presented with modified inclusion property to avoid unnecessary cache block invalidation.

Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems

Embedded systems are becoming increasingly common in everyday life and like their general-purpose counterparts, they have shifted towards shared memory multicore architectures. However, they are much more resource constrained, and as they often run on batteries, energy efficiency becomes critically important. In such systems, achieving high concurrency is a key demand for delivering satisfactory performance at low energy cost. In order to achieve this high concurrency, consistency across the shared memory hierarchy must be accomplished in a cost-effective manner in terms of performance, energy, and implementation complexity. In this article, we propose Embedded-Spec, a hardware solution for supporting transparent lock speculation, without the requirement for special supporting instructions. Using this approach, we evaluate the energy consumption and performance of a suite of benchmarks, exploring a range of contention management and retry policies. We conclude that for resource-constrained platforms, lock speculation can provide real benefits in terms of improved concurrency and energy efficiency, as long as the underlying hardware support is carefully configured.