Content Addressable Memory Research Articles

In‐Memory Search for Highly Efficient Image Retrieval

Finding similar images in real time plays a key role in information retrieval and serves as an indispensable function of the search engine. However, image retrieval involves massive distance computation. With the increase in image data volume and dimension, distance computation is suffering from huge power consumption and high computational complexity. Despite the remarkable advantages in energy efficiency shown by nonvolatile content addressable memory (nvCAM)‐based in‐memory search, achieving software‐comparable search accuracy remains a critical challenge under the impact of device variations and other nonideal factors. Here, a heterogeneous image retrieval system combining highly parallel in‐memory search with a high‐precision digital system is reported. Hamming distance (HD) can be calculated in situ with a few memory read operations on the memristor‐based CAM, and several similar images are fetched for further high‐precision rerank in the digital system. This heterogeneous computing system shows high energy efficiency (50×) compared to the CPU and higher search accuracy than the fully in‐memory computing method, thus alleviating the efficiency bottleneck of CPU‐based image retrieval.

Ferroelectric Content-Addressable Memory Cells with IGZO Channel: Impact of Retention Degradation on the Multibit Operation.

Indium gallium zinc oxide (IGZO)-based ferroelectric thin-film transistors (FeTFTs) are being vigorously investigated for being deployed in computing-in-memory (CIM) applications. Content-addressable memories (CAMs) are the quintessential example of CIM, which conduct a parallel search over a queue or stack to obtain the matched entries for a given input data. CAM cells offer the ability for massively parallel searches in a single clock cycle throughout an entire CAM array for the input query, thereby enabling pattern matching and searching functionality. Therefore, CAM cells are used extensively for pattern matching or search operations in data-centric computing. This paper investigates the impact of retention degradation on IGZO-based FeTFT on the multibit operation in content CAM cell applications. We propose a scalable multibit 1FeTFT-1T-based CAM cell composed of only one FeTFT and one transistor, thus significantly improving the density and energy efficiency compared with conventional complementary metal-oxide-semiconductor (CMOS)-based CAM. We successfully demonstrate the operations of our proposed CAM with storage and search by exploiting the multilevel states of the experimentally calibrated IGZO-based FeTFT devices. We also investigate the impact of retention degradation on the search operation. Our proposed IGZO-based 3-bit and 2-bit CAM cell shows 104 s and 106 s retention, respectively. The single-bit CAM cell shows lifelong (10 years) retention.

Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture

Modern shared-memory multi-core processors typically have shared Level 2 (L2) or Level 3 (L3) caches. Cache bottlenecks and replacement strategies are the main problems of such architectures, where multiple cores try to access the shared cache simultaneously. The main problem in improving memory performance is the shared cache architecture and cache replacement. This paper documents the implementation of a Dual-Port Content Addressable Memory (DPCAM) and a modified Near-Far Access Replacement Algorithm (NFRA), which was previously proposed as a shared L2 cache layer in a multi-core processor. Standard Performance Evaluation Corporation (SPEC) Central Processing Unit (CPU) 2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer. Results show improved performance of the multicore processor’s DPCAM and NFRA algorithms, corresponding to a higher number of concurrent accesses to shared memory. The new architecture significantly increases system throughput and records performance improvements of up to 8.7% on various types of SPEC 2006 benchmarks. The miss rate is also improved by about 13%, with some exceptions in the sphinx3 and bzip2 benchmarks. These results could open a new window for solving the long-standing problems with shared cache in multi-core processors.

Perfect Hash-Based Routing Lookup for LEO Constellation Backbone Network

The performance of packet forwarding mainly relies on the routing lookup (RL) in high-speed routers and switches. Due to the network topology change and the limited resource on aerospace devices, the RL strategy for LEO constellation backbone networks should be specifically designed. Targeting lower resource consumption, we first propose the perfect hash-based RL, including a Perfect Hash Function (PHF) for metarule space compression plus random access for the output interface. A Satellite Perfect Hash Function (SPHF) algorithm is proposed to generate efficient hash functions with limited storage. For 10000 randomized keys, the SPHF algorithm constructs 50-Kb PHFs in 3.05 milliseconds with 538 Kb storage. Then we design the Routing-oriented Hash Function (RHF) algorithm by fusing the perfect hash and RL, and optimize RHF towards the hardware implementation. The RHF algorithm is robust to different RL scenarios. In the FPGA (xc7k70t-fbv900-1) experiment with 10000 32-bit metarules and 4 output interfaces, a typical RHF algorithm (RHF1) costs only 13.2 ns and 1429 equivalent LUTs to lookup each packet under 312.5 MHz clock frequency. Compared with most advanced Ternary Content Addressable Memory (TCAM) based implementations, RHF1 reduces the storage and logic resources by at least an order of magnitude while keeping comparable lookup latency in the same FPGA Chip. This paper provides a design mentality for the RL of LEO constellation backbone networks.

LtRFT: Mitigate the Low-Rate Data Plane DDoS Attack With Learning-To-Rank Enabled Flow Tables

Software-Defined Networking (SDN) switches typically have limited ternary content addressable memory (TCAM) that caches the flow entries on the data plane. The scarcity and strong resource competitiveness of TCAM space put the flow tables at the risk of malicious Distributed Denial-of-Service (DDoS) attacks. In this paper, we propose LtRFT, a Learning-To-Rank (LtR) based scheme for mitigating the low-rate DDoS attacks targeted at flow tables. LtRFT consists of three modules: <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">monitor</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ranker</i> , and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mitigator</i> . <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Monitor</i> manages the flow table status and sends alerts to other modules after detecting attacks. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ranker</i> models the attack mitigation problem as a flow entry ranking task, and ranks malicious flows with a high eviction priority using a pairwise-based LtR algorithm. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mitigator</i> frees up the flow table space by deleting malicious flow entries according to the flow entry ranking sequence generated by <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ranker</i> . We introduce LtR to network attack detection innovatively and use both classification and information retrieval metrics to describe and evaluate LtRFT. Extensive experiments were conducted to validate the effectiveness and robustness of LtRFT in detecting and mitigating the low-rate data plane DDoS attacks. LtRFT can detect malicious attack flows with an accuracy of over 96%, and can reduce the attack flow duration by 97.7% with an average extra latency of 0.5 seconds, which proves that LtRFT is practicable in SDN deployments.

Major 3 Satisfiability logic in Discrete Hopfield Neural Network integrated with multi-objective Election Algorithm

&lt;abstract&gt; &lt;p&gt;Discrete Hopfield Neural Network is widely used in solving various optimization problems and logic mining. Boolean algebras are used to govern the Discrete Hopfield Neural Network to produce final neuron states that possess a global minimum energy solution. Non-systematic satisfiability logic is popular due to the flexibility that it provides to the logical structure compared to systematic satisfiability. Hence, this study proposed a non-systematic majority logic named Major 3 Satisfiability logic that will be embedded in the Discrete Hopfield Neural Network. The model will be integrated with an evolutionary algorithm which is the multi-objective Election Algorithm in the training phase to increase the optimality of the learning process of the model. Higher content addressable memory is proposed rather than one to extend the measure of this work capability. The model will be compared with different order logical combinations $ k = \mathrm{3, 2} $, $ k = \mathrm{3, 2}, 1 $ and $ k = \mathrm{3, 1} $. The performance of those logical combinations will be measured by Mean Absolute Error, Global Minimum Energy, Total Neuron Variation, Jaccard Similarity Index and Gower and Legendre Similarity Index. The results show that $ k = \mathrm{3, 2} $ has the best overall performance due to its advantage of having the highest chances for the clauses to be satisfied and the absence of the first-order logic. Since it is also a non-systematic logical structure, it gains the highest diversity value during the learning phase.&lt;/p&gt; &lt;/abstract&gt;

A Digital Processing in Memory Architecture Using TCAM for Rapid Learning and Inference Based on a Spike Location Dependent Plasticity

In this paper, we present a digital processing in memory (DPIM) configured as a stride edge-detection search frequency neural network (SE-SFNN) which is trained through spike location dependent plasticity (SLDP), a learning mechanism reminiscent of spike timing dependent plasticity (STDP). This mechanism allows for rapid online learning as well as a simple memory-based implementation. In particular, we employ a ternary data scheme to take advantage of ternary content addressable memory (TCAM). The scheme utilizes a ternary representation of the image pixels, and the TCAMs are used in a two-layer format to significantly reduce the computation time. The first layer applies several filtering kernels, followed by the second layer, which reorders the pattern dictionaries of TCAMs to place the most frequent patterns at the top of each supervised TCAM dictionary. Numerous TCAM blocks in both layers operate in a massively parallel fashion using digital ternary values. There are no complicated multiply operations performed, and learning is performed in a feedforward scheme. This allows rapid and robust learning as a trade-off with the parallel memory block size. Furthermore, we propose a method to reduce the TCAM memory size using a two-tiered minor to major promotion (M2MP) of frequently occurring patterns. This reduction scheme is performed concurrently during the learning operation without incurring a preconditioning overhead. We show that with minimal circuit overhead, the required memory size is reduced by 84.4%, and the total clock cycles required for learning also decrease by 97.31 % while the accuracy decreases only by 1.12%. We classified images with 94.58% accuracy on the MNIST dataset. Using a 100 MHz clock, our simulation results show that the MNIST training takes about 6.3 ms dissipating less than 4 mW of average power. In terms of inference speed, the trained hardware is capable of processing 5,882,352 images per second.

A Novel Cascadable TCAM Using RRAM and Current Race Scheme for High-Speed Energy-Efficient Applications

In this work, a novel ternary content addressable memory (TCAM) design is proposed using resistive random-access memory (RRAM) array in 2T2R configuration. The suggested memory array adopts the current-race (CR) sensing mechanism incorporated with a match-line (ML) booster in the sensing amplifier (SA) to improve energy efficiency, search speed and tolerance to RRAM switching variation. Several innovations are implemented to enhance the design further. For large TCAM arrays, match-line sensing amplifier (MLSA) direct cascading (DC) and an SR-latch cascading (SRC) schemes are proposed and compared in search speed, energy efficiency and MLSA noise margin. A same clock phase cascading (SCPC) scheme is also introduced to reduce latency in cascading structure by placing evaluation phase of all stages in the same clock phase. Furthermore, an RRAM-based tunable delay element (RRAM-TDE) is used in the TCAM design to provide flexibility and robustness against RRAM switching variation. The resulting system demonstrates excellent speed, energy and area efficiency against other TCAM designs using CMOS and emerging non-volatile memory (eNVM). To the best of our knowledge, the proposed 64-bit 1-stage TCAM system's speed and energy consumption match the best performance reported by other eNVM-based TCAM designs. The proposed design on a 128-bit 2-stage system also has speed and energy consumption comparable to SRAM-based TCAMs with the extra advantages of (a) compact size (90% reduction) and (b) non-volatility.

A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation

In this paper, we propose an energy-efficient, reliable, hybrid, 10-transistor/2-Double-Barrier-Magnetic-Tunnel-Junction (10T2DMTJ) non-volatile (NV) ternary content-addressable memory (TCAM) with sub-nanosecond search operation. Our cell design relies on low-energy-demanding MTJs organized in a low-complexity voltage-divider-based circuit along with a simple dynamic logic CMOS matching network, which improves the search reliability. The proposed NV-TCAM was designed in 28nm FDSOI process and evaluated under exhaustive Monte Carlo simulations. When compared to the best previous proposed NV-TCAMs, our solution achieves lower search error rate (3.8×) and lower write and search energy (–73% and –79%, respectively), while also exhibiting smaller area footprint (–74%). Such benefits are achieved at the expense of reduced search speed.

BiCAM-based automated scoring system for digital logic circuit diagrams

Abstract In online education, it is critical for the quality of education to evaluate and grade the assignments or examinations that students upload to the system. However, it is time-consuming to determine how well the circuit drawings prepared for the digital logic course, which is a fundamental course in computer engineering and similar disciplines, are not only correct but also compatible with the truth table. Content-addressable memory (CAM), also known as associative memory, is a data storage and retrieval unit. Typically, it is used instead of the conventional memories in fast-paced and time-sensitive applications such as address lookup in Internet routers, databases, and pattern recognition. CAMs implement the search process by comparing the content itself with a key instead of finding the address like the conventional memories. To see the effect of using binary content-addressable memory-based memory on the time spent scoring hand or digital-drawn logic circuits, it is compared with various data structures commonly used in logic simulation programs. I found a significant relationship (O(1)), indicating that the proposed architecture reduces the time complexity in the search process. This expression is the same as time complexity in hash tables.

Metode Bidirectional Associative Memory (BAM) Kontinu Pengenalan Pola Karakter Untuk Keamanan Data

Artificial Neural Networks have a paradigm for processing information with the concept of working using biology in processing information similar to how the human brain works. Artificial neural networks solve many problems using the concept of uncertainty such as the discussion in the material, namely the introduction of Continuous BAM Character Patterns. The problem in this research is the lack of data security in maintaining information so that a lot of data can be accessed by people who do not have authority. The main objective of this research is to maintain data security using the Continuous BAM concept. The BAM Kontine method is a method that has the ability to have associative memory or content addressable memory that can be called by using the part stored in the memory itself. The Continuous BAM method will change input to output more smoothly with values that lie in the range [0,1]. The activation function used is the sigmoid function. The results obtained from x1 = [7,-11], x2= [7,13] and x3=[-1,9], All Signs can be recognized by the Continuous BAM algorithm. All Sign Patterns have the same target but have different values.

Novel circuit design for content-addressable memory in QCA technology

Novel circuit design for content-addressable memory in QCA technology

Large Scale LEO Satellite Networks for the Future Internet: Challenges and Solutions to Addressing and Routing

This document analyses the problems and challenges of addressing and routing to Low Earth Orbit (LEO) satellites used for the future Internet. It focuses on the scenario where Inter-Satellite-Links (ISL) are used for massive LEO satellite constellation. Such LEO satellite network is the key to the Non-terrestrial Network (NTN) integration with 5G and beyond. The paper describes two categories of solutions. One is based on IPv6 and another is based on a new protocol, New IP. The two categories of solutions are a) using new types of addresses for LEO satellites and b) new concepts for routing with these addresses. The semantic addressing scheme leverages the characteristics of satellites with known orbit elements; and simplifies the satellite identification by using limited indexes. The routing method combines semantic addressing with source routing and generates a new semantic routing scheme. Compared with traditional methods, the new proposals dramatically reduce the workload in satellite, such as table size, Ternary Content-addressable memory (TCAM) lookups, and packet header size. Thus it is more suitable to networks in space where the harsh environment limits the hardware performance, power consumption, link bandwidth and system complexity.

Data and Computation Reuse in CNNs Using Memristor TCAMs

Exploiting computational and data reuse in CNNs is crucial for the successful design of resource-constrained platforms. In image recognition applications, high levels of input locality and redundancy present in CNNs have become the golden goose for skipping costly arithmetic operations. One promising technique for this consists in storing function responses of some input patterns into offline lookup tables and replacing online computation with search operations, which are highly efficient when implemented by emerging non-volatile memory technologies. In this work, we rethink both algorithm and architecture for exploiting locality and reuse opportunities by replacing entire convolutions with searches on Content-addressable Memories. By previously calculating convolution results and building compact lookup tables with our novel clustering algorithm, one can evaluate activations at constant time complexity, also requiring a single read operation of the current input tensor. Then, we devise a reconfigurable array of processing elements based on memristive Ternary Content-addressable Memories to efficiently implement the algorithmic solution and meet the flexibility requirements of several CNN architectures. Results show that our design reduces the number of multiplications and memory accesses proportionally to the number of convolutional layer channels. The average performance is 1,172 and 82 FPS for AlexNet and VGG-16 models, thus outperforming state-of-the-art works by 13×.

Multi-Layered QCA Content-Addressable Memory Cell Using Low-Power Electronic Interaction for AI-Based Data Learning and Retrieval in Quantum Computing Environment.

In this study, we propose a quantum structure of an associative memory cell for effective data learning based on artificial intelligence. For effective learning of related data, content-based retrieval and storage rather than memory address is essential. A content-addressable memory (CAM), which is an efficient memory cell structure for this purpose, in a quantum computing environment, is designed based on quantum-dot cellular automata (QCA). A CAM cell is composed of a memory unit that stores information, a match unit that performs a search, and a structure, using an XOR gate or an XNOR gate in the match unit, that shows good performance. In this study, we designed an XNOR gate with a multilayer structure based on electron interactions and proposed a QCA-based CAM cell using it. The area and time efficiency are verified through a simulation using QCADesigner, and the quantum cost of the proposed XOR gate and CAM cell were reduced by at least 70% and 15%, respectively, when compared to the latest research. In addition, we physically proved the potential energy owing to the interaction between the electrons inside the QCA cell. We also proposed an additional CAM circuit targeting the reduction in energy dissipation that overcomes the best available designs. The simulation and calculation of power dissipation are performed by QCADesigner-E and it is confirmed that more than 27% is reduced.

Ferroelectric Devices for Content-Addressable Memory.

In-memory computing is an attractive solution for reducing power consumption and memory access latency cost by performing certain computations directly in memory without reading operands and sending them to arithmetic logic units. Content-addressable memory (CAM) is an ideal way to smooth out the distinction between storage and processing, since each memory cell is a processing unit. CAM compares the search input with a table of stored data and returns the matched data address. The issues of constructing binary and ternary content-addressable memory (CAM and TCAM) based on ferroelectric devices are considered. A review of ferroelectric materials and devices is carried out, including on ferroelectric transistors (FeFET), ferroelectric tunnel diodes (FTJ), and ferroelectric memristors.

An All-Optical Address Look-Up Table Using Optical CAM and Optical RAM Banks

We report for the first time, to the best of our knowledge, the experimental demonstration of a complete all-optical 2-bit Address Look-Up (AL) table that performs address matching and forwarding and operates at 10Gb/s. The circuit incorporates an optical Content Addressable Memory (CAM) and an optical Random Access Memory (RAM) table that are interconnected via an optical Encoding/Decoding circuit. The AL table has been experimentally validated for different sets of CAM and RAM word contents as well as for different CAM and RAM row interconnect settings at 10Gb/s, revealing a power penalty of around 9 dB at a bit-error-rate (BER) of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> . Furthermore, we demonstrate experimental results of a fully integrated InP-based optical CAM cell, which includes an integrated XGM Flip-Flop (FF) memory cell and a Mach-Zehnder Interferometer (MZI) XNOR Access Gate (AG) and supports content addressing operation at 5 Gb/s. This fully-integrated optical CAM cell indicates a possible integration roadmap for the AL constituent building blocks towards the deployment of integrated optical ALs that can be utilized in optical routing or, more general, in optical content matching and forwarding operations.

Computational Associative Memory with Amorphous Metal‐Oxide Channel 3D NAND‐Compatible Floating‐Gate Transistors (Adv. Electron. Mater. 12/2022)

Massively Scalable Ternary Content-Addressable Memories In article number 2200643, Xunzhao Yin, Xiao Gong, and co-workers present high-performance floating-gate transistors with an amorphous-InGaZnO channel and the application in ternary content addressable memories (TCAMs). The two-transistor configuration and the extremely low OFF current of the TCAM cell significantly improve the scalability of the TCAM array.

Segmented Match-Line and Charge-Sharing Based Low-Cost TCAM

This brief presents a segmented match-line (ML) and charge-sharing based search scheme for low-cost ternary contents addressable memory (TCAM). In the proposed TCAM, a first-round search operation is performed on half cells located in even columns. During the first-round search, most of the mismatch cases are filtered out while remaining few mismatched cases that is misrecognized as the matched case. To complete the search operation in a low-power manner, a charge-sharing between the segmented MLs is used for the second-round search operation. The proposed 16KB 16T-NOR TCAM macro has been implemented using a 28nm CMOS technology. Numerical results show that the proposed TCAM improves sensing delay up to 5.6x faster and saves search energy-delay-product by 83% compared to the conventional approaches.

Memtransistor-Based Ternary Content-Addressable Memories: Design and Evaluation

The memtransistor (MT) based on 2-D materials is considered a promising candidate to extend Moore’s law, thanks to its scalability. As a hybrid integration of a memristor and a transistor, MT combines the electrical properties of memristor-based one-transistor one-resistor (1T-1R) structures (i.e., nonvolatile resistive switching and gate selection) into a single compact device. In this work, we evaluate MT technology from an application perspective and explore its use in ternary content-addressable memory (TCAM) systems. Based on characterization data from a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${10} \times {10}$ </tex-math></inline-formula> MoS2-based MT crossbar array, we propose two designs of MT-based TCAM (i.e., bitcells and TCAM array implementations and layouts). We also explore the design space of TCAM parameters and compare the performance and reliability of the proposed TCAM designs. In particular, we demonstrate that the use of MT technology facilitates the implementation of long TCAM words (>2 kbits) at low MT resistance ratios and search voltages, which is desirable for long TCAM endurance.