Contacted Gate Pitch Research Articles

Foundry Integration of Carbon Nanotube FETs With 320 nm Contacted Gate Pitch Using New Lift-Off-Free Process

While advances with silicon-based technologies continue to be made, alternative technologies to supplement Silicon are currently being explored. Carbon nanotube (CNT) field-effect transistors (CNFETs) are a leading proposed candidate for back-end-of-line (BEOL) heterogenous integration with silicon. However, a challenge facing the scalability and performance of heterogeneously integrated CNTs and other nanomaterials is the current use of non-standard metal evaporation and lift-off for contact metallization. We experimentally demonstrate a new VLSI-compatible, lift-off-free CNFET process that uses conventional sputtered liner and tungsten metal fill/damascene for contact formation. This process is implemented in a commercial silicon CMOS foundry and demonstrates improved scalability and performance (~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> higher on-current and ~40% lower subthreshold swing) compared to lift-off processing. All processing is low-temperature (≤415°C) and thus still (BEOL) compatible.

Opportunities in Device Scaling for 3-nm Node and Beyond: FinFET Versus GAA-FET Versus UFET

The performances of FinFET, gate-all-around (GAA) nanowire/nanosheet,and U-shaped FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To accommodate a contacted gate pitch (CGP) of 32 nm and below, the gate length is scaled down to 14 nm and beyond. While going from 5-nm node (N5) to 3-nm node (N3) dimensions, the GAA-lateral nanosheet (LNS) shows 8% reduction in the effective drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) due to an enormous rise in short channel effects, such as subthreshold slope (SS) and drain-induced barrier lowering (DIBL). On the other hand, 5-nm diameter-based lateral nanowire shows an 80% rise in total current driving capability (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ). Therefore, to enable future devices, we explored electrostatics and effective drive current (Ieff) in FinFET, GAA-FET, and UFET architectures at a scaled dimension. The performances of both Siand SiGe-based transistors are compared using an advanced device simulator, TCAD Sentaurus.

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm2 is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm2 array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall Vmin of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.

Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures

Scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL), and Middle-of-Line (MOL) device parameters, is systematically investigated. It is concluded that the combined requirements of device electrostatics together with the demands on contact resistance, presents a Contacted-Gate-Pitch (CGP) scaling limit for horizontal-transport FETs. FET drive is expected to significantly degrade below this CGP ~ 40 nm as a result. Good agreement between hardware data and TCAD simulations is achieved and employed to estimate the contact resistance values for aggressively scaled FinFETs. These observations show that FinFETs scaled below CGP of 40 nm will require the contact resistivity (ρ C ) of ~8 × 10 -10 Ω-cm 2 , while fully ohmic contacts i.e., ρ C of ~1 × 10 -10 Ω-cm 2 will be required if FinFETs are to extend performance below CGP of 30 nm. Ultimately, transition to new device architectures in which contact area is independent of CGP and/or Fin-Pitch will be necessary.

30-nm Contacted Gate Pitch Back-Gate Carbon Nanotube FETs for Sub-3-nm Nodes

Carbon nanotube FETs (CNFETs) promise significant energy efficiency benefits versus silicon for digital systems. While these projected benefits are for CNFETs with similar geometries as silicon FETs (e.g., top-gate FETs, with the FET gate on top of the channel), the majority of the demonstrated CNFETs leverage back-gate geometries due to ease of fabrication (i.e., the gate is fabricated before and underneath the FET channel). Although back-gate CNFETs have already been experimentally demonstrated, importantly, there lacks any rigorous analysis of their benefits for digital very-large-scale integrated (VLSI) circuits. Here, we rigorously quantify, for the first time, the benefits of back-gate geometries: both for enabling aggressive device scaling as well as VLSI circuit energy-delay product (EDP) benefits. The key contributions of this paper are: 1) first analysis of back-gate FET geometries for digital VLSI circuits, showing they enable >1.6× additional EDP benefit for CNFETs due to reduced parasitic capacitances (versus top-gate CNFETs), 2) our analysis shows that leveraging back-gate FETs enables aggressive FET scaling to sub-3-nm technology nodes, and 3) as a feasibility case study, we experimentally realize digital logic circuits that fit within the world's smallest contacted gate pitch to date (CGP, a key metric defining the area of an FET and consequently the technology node) of 30 nm.

Chip Power Scaling in Recent CMOS Technology Nodes

This paper tracks the scaling of total chip power at constant frequency (i.e., energy-per-operation) through the last few CMOS nodes. The focus is on high-performance microprocessors. To evaluate the progression of chip power, Intel’s Core-i7 (Intel’s highest performance consumer microprocessor manufactured in the highest performance CMOS technology node) was used as the benchmark. Core-i7 has been manufactured for eight generations starting in the 45-nm node and continuing through the 14++ node. This paper argues that in the more recent nodes, the total chip power at constant frequency (energy-per-operation) has scaled much less than that of the earlier CMOS nodes. The early 14-nm technology exhibited particularly poor power scaling, and in fact, the technology was improved by increasing the device current and relaxation of the contacted gate pitch in 14++. Early product data in 10 nm points to issue in dropping the chip power (at constant frequency) relative to the previous node (14++), which may challenge the power-performance justification for scaling to the 10 nm node and beyond. Improving chip power scaling (energy-per-operation) in upcoming nodes is critical as a key part of the value proposition for continued CMOS scaling, especially as applied to high-performance microprocessors.

(Invited) Advanced Replacement High-K/Metal Gate Stack Engineering for High-Performance Strained Silicon-Germanium Finfets with High Ge Content

Strain engineering for pFETs has been conventionally enabled utilizing embedded SiGe in the source/drain regions to continuously boost the transistor current drive and transconductance [1]. Historically, for planar technologies, transconductance was monotonically improved by advancing the technology generations. However, this trend for transconductance, when properly normalized to the effective device width (fin perimeter) is no longer observed when FinFETs were introduced to the mainstream CMOS to improve the short channel effects for sub 30nm gate lengths [2]. The FinFET transconductance saturation or drop be attributed to ineffectiveness of the embedded SiGe stressors (in spite of higher mobility near-(110) surfaces) and/or increased contribution of the S/D resistance as the contacted gate pitch size aggressively scales down. Unless there is a strong and reliable method to externally apply gigantic strain to the Si fin channel, using strained SiGe (s-SiGe) channel, with built-in uniaxial compression, is a strong option to overcome this issue. In fact, SiGe has been utilized in CMOS industry as a knob to control the threshold voltage (Vth) and in part to boost the pFET reliability and transport [3]. Moreover, introduction of SiGe channel for planar pFET has improved reliability, resulting in further Capacitance-Equivalent-oxide-Thickness (CET) scaling over Si. For s-Si1-xGex FinFETs, choice of Ge content (x) is not trivial. Adding more Ge can ideally build in more channel stress resulting increased hole mobility and current drive. However, epitaxial-defect-driven fin height control due to the critical thickness constraints, process thermal budget, bandgap reduction and gate-induced drain leakage (GIDL) control remain challenging. In particular, High-Ge-Content (HGC) s-SiGe FinFETs are of great interest for two reasons, from the transport point of view: First, very high level of strain (close to 3GPa) can be achieved when lattice matched to Si [4]. Second, if strain-relaxed buffer (SRB) SiGe with moderate Ge % is used to tensily strain Si nFET, higher Ge is required to compressively strain the pFET [5]. The GIDL issue can be mitigated by operating the high-performance (HP) device at a lower VDD, i.e. below 0.6V, in line with logic roadmap [4]. Controlling the HFIN, to be competitive with the state-of-the-art Si FinFETs, remains challenging. Above all, a major challenge is associated with the gate stack and interface trap control which is more pronounced in HGC SiGe than Si and pure Ge. In this talk, key process details to enable relatively tall fins and optimized replacement high-k metal gate (RMG) stacks in high-Ge-content SiGe will be discussed and their impact on key device characteristics will be presented. In particular, we review our recent advancement to achieve optimized RMG IL and passivation [6], high hole mobility and record performing short channel pMOS FinFETs. In additions, a metal gate work-function tuning solution will be presented utilizing an ultra-thin replacement metal-gate scheme to achieve target high-performance off current down to 15nm gate lengths.

Consideration of UFET Architecture for the 5 nm Node and Beyond Logic Transistor

In this paper, we propose a trench MOS architecture for the upcoming 5 nm node and beyond logic transistor. The intended device has a gate formed vertically downward, with added spacers along the gate to S/D sidewall. In doing so, the recessed device having longer channel length (than the defined gate footprint) would be a constructive approach to limit the short channel effects (SCE). The novel transistor has the potential to enable the scaling of gate length (footprint) less than 10 nm and contacted gate pitch below 32 nm, resulting in the smallest active area (on-wafer footprint) for a single device. Novel process steps are simulated depicting easier fabrication while the electrical analysis shows a better electrostatic control over any unwanted leakage flows. Along with the area scaling and SCE control, the planar upper surface allows a vertical integration. Growing another flipped device on top surface permits the designer to implement a logic circuit on a footprint of a single device, achieving ~50% area gain further. TCAD based simulations were performed to design and characterize the performances of an individual device and the vertical inverter.

(Invited) Gate-All-Around Transistors Based on Vertically Stacked Si Nanowires

Gate-all-around (GAA) transistors based on vertically stacked horizontal nanowires are promising candidates to replace FinFETs in future CMOS technology nodes. First of all, GAA devices provide optimal electrostatic control over semiconducting nanowire channels, which enables downscaling of the gate length to below the FinFET limit, while maintaining low off-state leakage [1]. Besides, horizontally oriented nanowires are an evolutionary extension of FinFETs, as opposed to vertical nanowires which require more disruptive technology and design changes [2]. Finally, stacking of nanowires is relevant for enhancing the drive current per footprint. Based on these considerations, GAA transistors made of vertically stacked horizontal nanowires have been included in the ITRS roadmap to reduce the contacted gate pitch, which is a key figure of merit for CMOS device density, to below ~40 nm in 2019-2021 [3]. In the context of the industrial relevance described above, we present the fabrication of Si GAA devices on bulk Si substrates. Multiple processing aspects that are relevant for bulk CMOS technology definition are addressed, including stacking of 8-nm-diameter Si wires at 45-nm lateral pitch and 20-nm vertical pitch [4], and nanowire-compatible replacement metal gate processing in combination with threshold voltage tuning by dual work function metal integration [5]. Temperature restrictions for the formation of shallow trench isolation, and the interaction between N- and P-type junction formation on one hand and nanowire release processes on the other hand are discussed as well. [1] K. J. Kuhn, IEEE Trans. Electron Devices, vol. 59 (7), p.1813, (2012). [2] L. Liebmann et al., VLSI Tech. Dig., p.112 (2016). [3] The International Roadmap for Semiconductors (ITRS) 2.0, http://www.itrs2.net/ (2015). [4] H. Mertens et al., VLSI Tech. Dig., p.158 (2016). [5] H. Mertens et al., IEDM Tech. Dig., p.524 (2016). Figure 1

Titanium Silicide/Titanium Nitride Full Metal Gates for Dual-Channel Gate-First CMOS

We demonstrate a thermally stable titanium silicide/titanium nitride (TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> /TiN) full metal gate (FMG) for dual-channel gate-first high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> /metal gate complementary metal–oxide–semiconductor technology. Unlike prior tungsten-based FMG, the simple TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> /TiN gate electrode does not require any additional barrier layer preventing oxygen down-diffusion during high-temperature processing, as the TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> itself blocks oxygen. With HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based gate dielectrics and without any oxygen scavenging scheme, we thus demonstrate a capacitance-equivalent thickness in inversion ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\mathrm {inv}})$ </tex-math></inline-formula> of 1.11 nm, corresponding to an equivalent oxide thickness of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 0.7$ </tex-math></inline-formula> nm. Silicon channel nFET and silicon germanium channel pFET parametrics are similar to those of control devices utilizing a conventional a-Si/TiN metal-inserted poly-Si stack (MIPS) gate, while providing superior gate sheet resistance. By supplanting MIPS with such an FMG, we anticipate that contacted gate pitch can be scaled aggressively via reduced gate height and borderless source/drain contacts.

A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology

This paper reviews the different stressor techniques used in microelectronics, in the scope of the Ultra-Thin Body & Buried Oxide Fully-Depleted Silicon On Insulator technology (UTBB FD-SOI). We compare the mechanical efficiency of the various stressors and present the impact of device dimensions (active area, gate length and pitch) on their efficiency. Our study emphasizes the high efficiency, for the FD-SOI technology, of the intrinsically strained channels, compared to the traditional embedded raised source/drain and contact-etch stop liner. With these techniques FD-SOI technology has already demonstrated channel stress higher than 1.5GPa for n type transistor and −2.3GPa for the p type devices and we envision channel stress values up to ±3GPa for n and p transistor channel, respectively. This performance is partly due to the mechanical configuration of intrinsically strained channels, in parallel mode rather than in serial mode as for the previous generation of stressors, which makes them less sensitive to the scaling of the contacted gate pitch. We also highlight another key element the high mechanical stability of the UTBB technology, related to the limited channel thickness (around 6nm) which enables achieving highly stressed channel without substantial adaptation of the integration flows.

A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part II: Extrinsic Elements, Performance Assessment, and Design Optimization

We present a data-calibrated compact model of carbon nanotube (CNT) field-effect transistors (CNFETs) including contact resistance, direct source-to-drain and band-to-band tunneling currents. The model captures the effects of dimensional scaling and performance degradations due to parasitic effects and is used to study the trade-offs between the drive current and leakage current of CNFETs according to the selection of CNT diameter, CNT density, contact length, and gate length for a target contacted gate pitch. We describe a co-optimization study of CNFET device parameters near the limits of scaling with physical insight, and project the CNFET performance at the 5-nm technology node with an estimated contacted gate pitch of 31 nm. Based on the analysis including parasitic resistance, capacitance, and tunneling leakage current, a CNT density of 180 CNTs/{\mu}m will enable CNFET technology to meet the ITRS target of drive current (1.33 mA/{\mu}m), which is within reach of modern experimental capabilities

(Invited) Challenges in Contact Technologies for Planar/Non-Planar Si Technologies

This article explores challenges to fabricating contacts to CMOS devices as the industry transitions from planar to non-planar device geometries. Traditional challenges such as contacted gate pitch scaling, parasitic capacitance & resistance as well as newer challenges due to an increase in process & integration complexity are reviewed and highlighted.

Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length

We report high-performance extremely thin SOI MOSFETs fabricated with a channel thickness down to 3.5 nm, sub-20-nm gate length, and contacted gate pitch of 100 nm. At an effective channel length of 18 nm, a drain-induced barrier lowering of 100 mV is achieved by either thinning the channel to 3.5 nm or by applying a reverse back-gate bias to 6-nm channel MOSFETs. Moreover, minimal increase in series resistance is seen when the channel is scaled to 3.5 nm, resulting in no performance degradation with SOI thickness scaling.

Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High- $\kappa$/Metal-Gate nFinFETs for High-Performance Logic Applications

Strained-silicon-on-insulator (SSOI) undoped-body high-κ /metal-gate n-channel fin-shaped field-effect transistors (nFinFETs) at scaled gate lengths and pitches (i.e., <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GATE</sub> ~ 25 nm and a contacted gate pitch of 130 nm) were fabricated using a gate-first flow. A “long and narrow” fin layout (i.e., fin length ~ 1 μm) was leveraged to preserve uniaxial tensile strain in the transistors. These devices exhibit drive currents suitable for high-performance logic technology. The change in the slope of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GATE</sub> (dR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /dL <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GATE</sub> ), transconductance <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MSAT</sub> , and injection velocity ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inj</sub> ) measurements indicate a ~ 15% mobility-induced <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> enhancement with SSOI relative to SOI nFinFETs at ultrashort gate lengths. Raman measurements conducted on SSOI substrates after fin formation demonstrate the preservation of ~ 1.3-GPa uniaxial tensile strain even after 1100°C annealing.

High-Performance Partially Depleted SOI PFETs With In Situ Doped SiGe Raised Source/Drain and Implant-Free Extension

We report partially depleted silicon-on-insulator p-channel field-effect transistors fabricated with a 32-nm technology ground rule and featuring SiGe raised source/drain, SiGe channel, and implant-free extension formation process. A respectable drive current of 950 μA/μm is obtained at an OFF current of 100 nA/μm, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1V, and a contacted gate pitch of 130 nm. Furthermore, when the transistor width is scaled down to 100 nm, the saturation transconductance increases by about 15%, leading to a drive current of 1100 μA/μm.

Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap

We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-kappa/metal gate) reach their limits and physical gate length can no longer be effectively scaled down. By judiciously engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of selective device structure scaling that will enable technology scaling and contacted gate pitch scaling for several generations beyond the currently perceived limits.