High-Performance Partially Depleted SOI PFETs With In Situ Doped SiGe Raised Source/Drain and Implant-Free Extension

Abstract

We report partially depleted silicon-on-insulator p-channel field-effect transistors fabricated with a 32-nm technology ground rule and featuring SiGe raised source/drain, SiGe channel, and implant-free extension formation process. A respectable drive current of 950 μA/μm is obtained at an OFF current of 100 nA/μm, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1V, and a contacted gate pitch of 130 nm. Furthermore, when the transistor width is scaled down to 100 nm, the saturation transconductance increases by about 15%, leading to a drive current of 1100 μA/μm.