Contact Windows Research Articles

Robust parameter design for integrated circuit fabrication procedure with respect to categorical characteristic

We consider a robust parameter design of the process for forming contact windows in complementary metal-oxide semiconductor circuits. Robust design is often used to find the optimal levels of process conditions which would provide the output of consistent quality as close to a target value. In this paper, we analyze the results of the fractional factorial design of nine factors: mask dimension, viscosity, bake temperature, spin speed, bake time, aperture, exposure time, developing time, etch time, where the outcome of the experiment is measured in terms of a categorized window size with five categories. Random effect analysis is employed to model both the mean and variance of categorized window size as functions of some controllable factors as well as random errors. Empirical Bayes’ procedures are then utilized to fit both the models, and to eventually find the robust design of CMOS circuit process by means of a Bootstrap resampling approach.

Observation of current polarity effect in stressing as-formed sub-micron Al–Si–Cu/TiW/TiSi 2 contacts

Formation of good silicide contacts becomes more important but difficult as the contact size continues shrinking toward the deep sub-micron regime. At the same time, higher current density, which may easily appear in small regions, could pose strong impact to the long-term reliability of sub-micron contacts. In this work, high current density stress experiments were conducted on the Al–Si–Cu/TiW/TiSi 2 contacts with the size ranging from 0.5×0.5 μm 2 down to 0.25×0.25 μm 2. The self-aligned silicide contacts were formed by using collimated sputtering, E-beam lithography, RTA, and RIE techniques. The silicide contacts were sintered at 400°C for 30 min. Cross-bridge Kelvin resistor structures were formed for electrical stressing and contact resistance measurement. One-way and two-way stressings were performed at high current density (∼10 7 A/cm 2) and the contact resistance was measured periodically at low current density during the stressing to monitor the evolution. It was found that the initial resistance of as-formed contacts was higher than expected. This is probably due to the difficulty of forming good interfaces in the small contact region by sputtering and that the sintering temperature may not be high enough to smear out the imperfection. The stressing was found to anneal the contacts. With electrons flowing from metal layer into the contact window, the contact resistance was reduced more efficiently than with reverse current of the same density. Stressed first by reverse current then by normal current, the resistance showed a two-step reduction with a significant transition at the switch of current polarity. For prolonged stressing, the contacts were gradually degraded and the reverse current induced more severe damage. These observations indicate strong electromigration effect at the small contacts.

A three-terminal N-channel InGaAsP–InP-based double heterostructure optoelectronic switch (DOES)

In this work, we give the first report on the physical and functional characteristics of a three-terminal InGaAsP–InP-based double heterostructure optoelectronic switch (DOES) device. In this device, electrical contact is made to the emitter, collector, and active layers while optical input is made via a window in the emitter contact. The DC current–voltage characteristic of a 100 μm × 80 μm device exhibits a switching voltage of 6.6 V with an OFF-state resistance of 200 kΩ and an ON-state resistance of <50 Ω. In conjunction with the electrical outputs, optical emission is generated with a ratio of >10 in the light emission between the ON (2 mA) and OFF states. We show that injection of current and (or) injection of light into the active region reduces the switching voltage. This is used to switch the device from the OFF state to the ON state without having to alter the output circuit bias (emitter–collector bias). The ability to switch the three-terminal InGaAsP–InP DOES with both electrical and optical inputs demonstrate its functionality, flexibility, and suitability for use in optoelectronic switching applications and for InP-based optoelectronic integrated circuits.

Laser diodes in piezoelectric quantum-well structures

We have determined the carrier density and internal electric field as a function of drive current in InGaAs quantum-well laser structures grown on GaAs (111)B substrates by fitting the spontaneous emission spectra observed through a top contact window using a self-consistent solution of Poisson’s and Schrödinger’s equations. At room temperature at threshold the internal field is still 50% of its initial value and as a result the quasi-Fermi levels are closer to the band edges of the well than in a square well, causing significant carrier loss through the barrier/waveguide material. We determine the loss by this route to be twice that for a similar device if the internal field was completely screened.

Electrical characterization of SrBi2Ta2O9 thin films for ferroelectric non-volatile memory applications

Abstract Ferroelectric SiBi2Ta2O9 capacitors with Pt electrodes were measured to have a non-volatile polarization of 6.6 μC/cm2 using 3 V pulse polarization measurements, a leakage current of less than 3×10−9 A/cm2 at 3 V, and a breakdown of voltage greater than 20 V. The temperature dependence of hysteresis loops were measured to 200 °C and both the non-volatile polarization and coercive field were observed to decrease with temperature. Process damage caused by CVD of overlying dielectrics and contact window plasma etching was reversed by oxygen annealing. Good resistance against both fatigue and imprint were observed.

Optimization of fully-implanted NPNs for high-frequency operation

With a very straightforward (low-cost) process flow as basis, fully-implanted washed-emitter-base (WEB) NPNs have been optimized for operation in the 10-30 GHz range. Above 20 GHz the best overall performance is achieved by heavy doping of the epi. A low-stress silicon rich nitride layer is proven effective as surface isolation before contact window dip-etch.

Bipolar integrated Kelvin test structure for contact resistance measurement of self-aligned implantations

A Kelvin contact resistance test structure has been developed for accurate measurement of highly-doped, shallow n/sup +/ and p/sup +/ implantations, which are self-aligned to the contact window. Here the structure has been integrated, without additional processing, in a 30 GHz washed-emitter-base n-p-n bipolar process, for the purpose of monitoring the emitter contact resistance. Diffusion taps to the emitter have been made with the phosphorus collector-plug implantation. Phosphorus evaporation from the contact window during the anneal step and the low sheet resistance of the collector-plug implantation, together with the overall design of the test structure, assure a very accurate determination of the emitter contact resistance even in situations where complete junction isolation of the diffusion taps is not directly possible. Results are presented for the optimization of the emitter anneal cycle with respect to the emitter contact resistance.

Integrity of shallow junction CMOS structures with Ti/TiN/AlSiCu and Ti/TiN/AlCu contact metallization

Shallow junction complementary metal oxide semiconductor (CMOS) structures (0.25 and 0.35 μm depth) were studied using sputter deposited Ti/TiN/AlSiCu and Ti/TiN/AlCu films for contact metallization. Single contact Van de Pauw patterns (to measure the breakdown voltage) as well as large junction area structures with multiple contact windows were used for electrical measurements. An increase in the RTA temperature used to silicide the contacts increased the Si consumption in the junctions and resulted in degradation of junctions yields. The thickness of the Ti layer had a larger influence on the stability of the junction than the thickness of the TiN layer (in the range of thicknesses studied). AlSi(0.75 wt%)Cu(0.5 wt%) films are more stable than AlCu(0.5 wt%) films for junction spiking. The AlCu films are more reactive, and the interdiffusion of Ti into the AlCu films makes the junctions less stable. The annealing temperature and post wafer fabrication is critical in maintaining stability of junctions. The junction depths, and dopants (BF 2- p- and As n-implanted) used in forming the junctions affect the breakdown voltages and junction yields. The BF 2 implanted junctions are more stable than arsenic implanted junctions.

The multianalytic approach; or yes, you can get there from here! Problem solving in semiconductor manufacturing

Manufacturing, development and failure mode analysis problems, in the semiconductor industry, present unique challenges and opportunities, not only to utilize several analytical techniques, but to process and deprocess samples into an appropriate format for analysis. In today' s' cleanrooms a great deal of development is integrated into the manufacturing line. This, combined with the ever decreasing size and increasing density of components on a single integrated circuit, creates the need for accurate as well as precise measurements. The method of measure must be appropriate to the task, compatible with the manufacturing environment, and useful in a process control system.Current complimentary bipolar technologies, utilizing shallow junction implants, require additional as well as less robust processing in order to maintain the depth and latitude of the junction. Additional processing includes the formation of a contact window spacer. The spacer is formed, following implant and thermal anneal, by growing and subsequently removing a thermal oxide layer. In the manufacturing process, oxide removal is verified by optical measure using visible light.

Development of single‐layer positive resist process for electron beam direct writing technology

AbstractA single‐layer resist process using a high resistivity positive resist by solubility reversal (PSR) for electron beam direct writing is described. Conventional PSR designed for mask creation is found to have inhomogeneous dissolution characteristics due to a side effect during the stage of deprotection reaction. To overcome this problem, the efficiency of dissolution inhibition is improved by controlling the composition of base resin materials. Using an optimized base resin structure, 0.4‐μm contact window patterns were successfully delineated in a 1.6‐μm thick single‐layer with a sensitivity of 3.5 μC/cm2. The dry etching durability of a single‐layer PSR was also examined and a high level of dry etching durability for SiO2 etching was observed.

Grain Boundary Grooving as the Mechanism of the Blech Electromigration in Interconnects

AbstractWe present a new approach to understand the mechanism of "homogeneous", or Blech electromigration (EM). This phenomenon describes macroscopically homogeneous displacement of the up-wind edge of thin film lines in microelectronic devices and is responsible for openings at contact windows, "vias" and other sites of perfect diffusion flux divergence.Our SEM, EPMA and EM drift velocity experiments have revealed the gradual transition from the microscopically homogeneous EM displacement to the highly nonhomogeneous mode wherein copious islands of residual material remain behind the drifting cathode edge of aluminum stripes. The transition is shown to occur due to an increase in either the current density, j, or in the stripe length, 1. The latter case suggests, that the transition results from the growth of the net grain boundary (GB) diffusion flux, I=le-Ib ,where Ie∝j and 1b∝1/1 are the EM flux and stress-gradient-driven back flux, respectively.Based upon recent progress in the theory of GB grooving under "external" GB fluxes, with surface diffusion acting as the healing mechanism, grooves' propagation along the line and their merging is considered to be the micromechanism of the "homogeneous" EM. In terms of the simple model described, the transition from the slow receding of the cathode butt edge slightly wrinkled by shallow grooves (A-regime of EM) to the fast extension and merging of slot -like grooves (B-regime) accounts for the transition observed in EM mode, while in both regimes the EM displacement velocity, V, is presumed to represent the groove propagation rate.The theory developed reduces to Blech formulae for V for the truly homogeneous A-regime and predicts quite different EM kinetics for the B-regime of microscopically nonhomogeneous EM. The latter is expected to dominate for films loaded by high current density with large grains and low surface diffusion.The dependence obtained for the residual mass left behind the drifted edge vs the displacement velocity, V, for unpassivated aluminum stripes of various lengths, loaded by j=2-106 A/cm2 at 548K provides a good evidence in support of a new approach.

Yield loss mechanisms in MOS-gated power devices

Defects which cause yield loss in MOS-gated power devices are discussed. Design and fabrication of a test element group for analysis of gate to source shorts in MOS-gated power devices are described. Experimental results obtained from these test elements are presented, based upon which it is demonstrated that gate to source shorts in power MOS-gated devices occur mainly along the edge of the polysilicon gate. The contact window opening step has been found to have a strong influence on the density of gate to source shorts. >

An Absorbing Layer Approach to Reducing Reflections in Multilayer Metal Lithographic Processes

We demonstrate that the use of an absorbing layer on top of an interlevel oxide can be used in lieu of the normal antireflective layer approaches to isolate the lithography of a via or contact window level from the reflections of an underlying metal layer. Specifically, we show the use of a sputtered amorphous silicon layer of 500 Å thickness in a double level metal process using g‐line lithography.

A simple, approximate representation of the electrical behaviour of metal-silicon contacts

Normally a metal-semiconductor contact is viewed as consisting of three distinct materials [1]: metal, a "native oxide" layer which is, in fact, of unknown composition, and semiconductor. The contact is held to be electrically characterized by its contact resistivity or specific contact resistance, which is the resistance per unit area (actually the resistance x area product). The contact interface is regarded then as a two-dimensional network of infinitesimal resistances connecting the metal to the bulk, which is itself a three-dimensional network of infinitesimal resistances. In previous work on electrical contacts to semiconductors, much effort has been expended on developing suitable test structures for measuring contact resistivity [1-4], and in refining the analysis of existing test structures [5, 6]. However, little attention has been paid to the fact that there does not appear to be a homogeneous interface layer. The evidence for this is the rather large scatter in measured resistances usually obtained in experiments [4, 7-10]. In an earlier paper [10] we showed that the source of the scatter in resistance was more likely to be variation in the contact resistivity than fluctuation in the contact window dimensions [4, 7]. Upon further reflection and examination of our experimental results, we find that the concept of contact resistivity, itself, requires modification. This, at least, appears to be the case for aluminium contacts to p-type silicon, but judging from the scatter in resistance observed for other metals and materials [9], may be true generally. The fall in contact resistance observed during the initial stage of annealing [8] gives evidence for penetration of an impurity film or native oxide layer. It is also known that aluminium dissolves silicon at the elevated temperature of annealing. The aluminium-doped silicon later deposits on the substrate during cooling, as may be inferred from the work of Naguib and Hobbs [8]. It is suggested here that the deposit occurs in patches in the contact window. Evidence for this has appeared in quite another context in the work of Black [11]. To model the electrical behaviour of the contact corresponding to this metallurgical condition, we must consider the equivalent electrical circuits that arise. We consider first the case of lightly doped p-type silicon. Away from precipitates there must exist a Schottky barrier as well as a bulk resistance, whereas in the vicinity of precipitates the conduction is essentially that occurring in the pure bulk material. For heavily doped silicon and for regions free of

Lateral Diffusion of Sodium from Peripheral Sources in Metal Oxide Semiconductor Transistors

In some metal oxide semiconductor (MOS) processes, sodium contamination may occur during the formation of source/drain contact windows or during subsequent metallization. Once introduced, the sodium diffuses laterally at different rates along several paths, with the potential for ultimate metal oxide semiconductor field effect transistor (MOSFET) threshold voltage instability. For this study, sodium was ion implanted within the source/drain region of a MOSFET near the end of its fabrication sequence, and various temperature and bias/temperature stresses were applied to induce sodium diffusion. The sodium appears to be prevented from reaching the MOS gate by a barrier, which can only be surmounted by the application of a gate bias voltage. The sodium diffusion coefficient for reaching this barrier is about at 400°C.

Loading Effects on Kinetical and Electrical Aspects of Silane‐Reduced Low‐Pressure Chemical Vapor Deposited Selective Tungsten

The growth rate of selective tungsten using tungsten hexafluoride and silane was measured in situ by measuring the time‐reflectance curve during selective deposition on a grating or contact window pattern etched in oxide on a silicon substrate. Ex situ measurements were performed by step‐height and weight‐increase measurement. The growth rate and electrical resistivity depend on the loading, i.e., the density of the growing area in a selective deposition. The difference in growth rate between extreme cases, i.e., 100% vs. 0.04% growing surface of a 3‐inch wafer for identical flow and pressure conditions can be as high as a factor of 20. The true surface kinetics were independent of the loading and can be determined quantitatively by calculating the surface partial pressures using a mathematical model. At low growing surface densities, the partial pressures at the wafer surface were approximately equal to the input partial pressures. At large loading, significant differences were calculated between surface and input conditions. The apparent order of growth rate in was 1 at low ratios and increased at a critical ratio. The order of growth rate in was −0.2 (±0.05) at ratios below 0.5 and became approximately −0.7 at higher ratios. The temperature dependence of the growth rate was small. The growth rate had a maximum at 300°C.

Adhesion and leakage current characteristics of selective CVD tungsten films on the silicon substrate

In this study we investigated the effects of SF 6 and CF 4 plasma pretreatments on the adhesion and junction leakage characteristics of the selective CVD W films by SiH 4 reduction of WF 6 on the Si substrate. The SF 6 plasma pretreatment performed in situ prior to W deposition to remove the polymer films in contact holes results in enhacement of the adhesion of W films to the Si substrate but degradation of junction leakages due to vertical and lateral Si consumptions. The CF 4 plasma pretreatment performed as the last step of the reactive ion etching for contact window opening produced the W/Si contacts of good adhesion, low contact resistances and low junction leakages for thin W films, while it produced the W/Si contacts of poor adhesion and high contact resistances fir thick W films. The selective CVD W films deposited by the three step process of SiH 4 reduction/in situ annealing/SiH 4 reduction was found to have both good adhesion and low junction leakage characteristics

On the source of scatter in contact resistance data

Previous treatments have assumed that small fluctuations in contact window dimensions between devices are chiefly responsible for the scatter in contact resistance data. Although this is plausible, it is shown in this paper that the source of this scatter is variation in contact resistivity, ρc, from resistor to resistor. It is further suggested that ρc is Cauchy distributed. Since standard deviation is in theory infinite for a Cauchy distribution, very high values of resistance at a contact window would occur with much greater frequency than common sense might suggest.

A Stacked Capacitor Cell with a Fully Self‐Aligned Contact Process for High‐Density Dynamic Random Access Memories

A new, self‐aligned contact process has been developed for a stacked capacitor dynamic random access memories (DRAM) cell. The bit line contact is three‐fold, self‐aligned with respect to the transistor gate, the field oxide, and the upper cell plate of the stacked capacitor. An oxide spacer technique is used to encapsulate the transistor gate. Etching of the overlapping bit line contact is self‐aligned by a proper choice of deposited materials and etch selectivities and does not affect the oxide isolation of the transistor gate and the field oxide. In addition, the stacked capacitor cell plate is self‐aligned and isolated from the bit line by a selective oxidation process. Using this technique, optimal contact window shaping and improved planarization of the interconnect dielectric isolation is simultaneously achieved. This fully self‐aligned contact process allows an increase in cell capacitance by a factor of about 1.4. No electrical degradation compared to a conventional contact process has been observed. For reduction of contact resistance, a process based on Si+‐ion implantation with subsequent annealing has been developed.

An O(n log m) algorithm for VLSI design rule checking

The authors describe a new variant of the segment tree approach for VLSI design rule checking. The best known algorithms to date for flat VLSI design rule checking require O(n log n) expected time and O( square root n) space, where n is the total number of edges on a mask layer of the chip. The expectation is with respect to a uniform distribution of edges over the chip area. The authors present a new algorithm of O(n log m) expected time complexity, where m is the maximum feature size for a given mask layer. Since m is bounded by the height of a chip, i.e. m=O( square root n), the new algorithm is adaptively more efficient than O(n log n). For layers such as diffusion or contact windows where m is independent of the chip size, i.e. m=O(1), the new algorithm runs in O(n) expected time, a definite improvement. The improved time efficiency is achieved without sacrificing O( square root n) space complexity.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>