Contact Resistance In Devices Research Articles

Dopant Diffusion Inhibition in Organic Field-Effect Transistors Using Organic Semiconductor/High-Molecular-Weight Polymer Blends

Molecular contact doping in organic field-effect transistors (OFETs) has been proved to be a very efficient strategy to reduce the device contact resistance. It consists of inserting a dopant layer between the organic semiconductor (OSC) and the top gold contacts to reduce the energy barrier required to inject/release charges. However, a main bottle-neck for its implementation is that the dopant diffuses toward the OFET channel with time, doping the OSC, and hampering the on/off switching device capability. In this work, we fabricated OFETs based on the benchmark OSC 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT-C8) by a solution shearing technique. First, we show that the OFET performance of these devices is significantly improved when a layer of the p-dopant 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ) is inserted before the evaporation of the gold source/drain contacts. Remarkably, we demonstrate that the dopant diffusion can be controlled by blending the OSC with polystyrene (PS) of different molecular weights. In-depth electrical characterization combined with studies of surface and in-depth distribution of the dopant by time-of-flight secondary ion mass spectrometry (ToF-SIMS) unambiguously show that in thin films of OSC blends with high-molecular-weight PS, the dopant remained drastically confined into the contact areas, which was reflected by an enhanced long-term device stability.

(Digital Presentation) Effect of Active Layer Thickness on Organic Thin-Film Transistors

ABSTRACT: Thin-Film Transistors (TFTs) are a substantial technological advancement in recent decades for various applications. The source/drain electrode layer and organic active layer thicknesses of Organic Thin-Film Transistors (OTFTs) should be optimized for better device performance. Organic electronics have been used for a wide range of applications, including flexible screens, smart digital devices, and photovoltaic cells, because of their flexibility and environmental sensitivity. The OTFT has the capability to match the efficiency of thin-film amorphous Silicon transistors, while also being companionable with low-temperature solution/printing-processed fabrication on flexible coupling substrates. The OTFTs are a valuable tool for determining unipolar carrier transport parameters in various situations.In this present research work, authors have utilized the concept of OTFTs in the assessment of bipolar transport properties in active layer blends. It offers a strategy to improve the precision of the assessment. Thereafter, in this this research work, impacts of active layer thickness on physical parameters of OTFT device performance have been realized. The 2D numerical device simulators have been used to examine the proposed OTFT structures. The discussion focuses on the various characteristics and parameters of OTFTs. The OTFTs are transistors that manage electric current flow using organic semiconductors as an active layer. The output and transfer characteristics of various OTFT structures have been used to calculate the performance characteristics of OTFTs. Optimizing the OTFT's organic active layer thickness is critical for high device performance. Both photo-current and photo-responsivity exhibit the same variation trend with increasing organic active layer thicknesses, increasing rapidly for a while and then tending to saturate at high values. The research findings demonstrate the impact of these parameters on device performance and temperature and the need to optimize these variables in the device. The carrier mobility of the high-performance P3HT: PCBM-based OTFT structure was approximately 10 cm2/Vs, and an ON/OFF current ratio of ~103. These results are compatible with those OTFTs fabricated previously. Research Methodology, Results, and Discussions A schematic structure is shown in Figure 1(a) proposed structure top view, and 1(b) a side view of the proposed structure used for simulation. Top-gate OTFT and bottom-gate OTFT geometrical structures have been used in this OTFT. The device's contact resistance, field mobility, and threshold voltage degrade subjected to bias stress. Since top-gate OTFT has a higher device degradation, the authors used bottom-gate OTFT. Due to the distinct properties here in this work the authors utilized conventional materials such as a blend of poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl C61-butyric acid methyl ester (PCBM) as the active layer. A P3HT: PCBM mix is simulated with an electronic device simulator and analyses the variation in active layer thickness that affects the device's performance and the factors that influence the performance of the device in this research work. The output and transfer characteristics of OTFTs have been realized using proper boundary conditions and OTFT physics. The proposed OTFT structures' output and transfer characteristics have been evaluated, and the simulated results show that the optimized structure's drain current (Id, max) is ~2.85 μA. The obtained results show that the device has good transfer and output characteristics at lower gate voltages. With increasing organic active layer thicknesses, both photo-current and photo-responsivity exhibit the same variation trend of increasing sharply at first and then tending to saturate at high values. Conclusion The simulation results examined the performance of devices built with bottom-gate OTFTs. A detailed analysis of the influence of active layer thickness on the OTFT configuration was realized. The device has the advantage of operating at a lower gate voltage, transforming it into a gate efficient control device. The operation at a lower voltage improves electrical stability. The electric field of the OTFT is 1.4x106 V/cm is obtained. The ON/OFF current ratio is higher. The outcomes of this analysis have been optimized and extracted after being tested in various contexts. The findings demonstrated that the suggested concept might be used to make rollable active-matrix displays, nonvolatile memory, sensors, and printed electronic devices. This work also reduces the SCEs and shows more efficient performance than traditional MOSFETs. Together with all application areas, the most important research area has been argued to be the simple manufacturing technique of OTFT with low production cost and non-breakable impacts that can be bent and folded. This device will be optimized with fabrication using these materials in the future, and thereafter, its characteristic will be verified with the simulated results. Figure 1

Contact property depending on radiation intensity between the perovskite semiconductor layer and electrode film

Hybrid organic–inorganic perovskites have been widely studied in high-performance optoelectronic devices. Long-term stability is a key limitation to date in restricting their further development and commercial application. In general, interface properties between a semiconductor and an electrode highly affect device performance and stability. Herein, contact characteristics between the perovskite and electrode varying with illumination status have been first investigated. The results suggest that device's contact resistance (RC), obtained from a transfer length method, decreases as the incident light intensity increases. The RC under a higher irradiation intensity (1.26 mW/cm2) is about one-tenth of that at a lower density (0.08 mW/cm2). Simulation has been performed and shows a similar trend with experimental results. The interface physical model has been discussed based on an energy band theory. The band bending and barrier modulation at the interface under light illumination are originated from the surface states and the localized charges. This work explains the interface in determining device's fundamental properties, including stability, RC variation, and charge carrier transport process. It is significant in understanding the device working mechanism and providing a potential way for perovskite optoelectronic devices with enhanced stability and performance.

Lower Limits of Contact Resistance in Phosphorene Nanodevices with Edge Contacts.

Edge contacts are promising for improving carrier injection and contact resistance in devices based on two-dimensional (2D) materials, among which monolayer black phosphorus (BP), or phosphorene, is especially attractive for device applications. Cutting BP into phosphorene nanoribbons (PNRs) widens the design space for BP devices and enables high-density device integration. However, little is known about contact resistance (RC) in PNRs with edge contacts, although RC is the main performance limiter for 2D material devices. Atomistic quantum transport simulations are employed to explore the impact of attaching metal edge contacts (MECs) on the electronic and transport properties and contact resistance of PNRs. We demonstrate that PNR length downscaling increases RC to 192 Ω µm in 5.2 nm-long PNRs due to strong metallization effects, while width downscaling decreases the RC to 19 Ω µm in 0.5 nm-wide PNRs. These findings illustrate the limitations on PNR downscaling and reveal opportunities in the minimization of RC by device sizing. Moreover, we prove the existence of optimum metals for edge contacts in terms of minimum metallization effects that further decrease RC by ~30%, resulting in lower intrinsic quantum limits to RC of ~90 Ω µm in phosphorene and ~14 Ω µm in ultra-narrow PNRs.

Effect of dielectric surface passivation on organic field-effect transistors: spectral analysis of the density of trap-states

The semiconductor/dielectric interface is arguably the most important region in field-effect transistors. This article investigates the performance-enhancing effects of passivation of the dielectric surface by a self-assembled layer (SAM) of silanes on organic field-effect transistors. Apart from conventional figures of merit for the devices, the energetic distribution of the density of the in-gap trap-states (trap-DOS) and the contact resistance are evaluated using numerical methods. The investigation reveals that the surface passivation of the dielectric SiO2 has a dual effect on device operation. Firstly, it establishes quantitatively that the surface passivation leads to a significant reduction in the density of both shallow and deep traps in the organic semiconductor PBTTT-C14. This effect outweighs the impact of the SAM dipoles on the device turn-on. Secondly, the contact resistance gets lowered by a factor of more than 10 due to the improved top-surface morphology of the PBTTT-C14 thin film. The lower contact resistance in devices is corroborated by lower contact potential difference between PBTTT-C14 and gold, measured using scanning kelvin probe microscopy.

(Invited) Cutting-Edge Epitaxial Processes for Sub 3 Nm Technology Nodes: Application to Nanosheet Stacks and Epitaxial Wrap-Around Contacts

The epitaxial growth of group IV semiconductor materials is one of the backbones of modern IC production flows. At present nodes it is used for the Source/Drain (S/D) engineering of both p- and n-MOS high performance transistors, allowing the deposition of SiGe:B and Si:P layers with active carrier concentrations ~ 1x1021 cm-3, ensuring low contact resistivities [1]. However, with reducing device dimensions, the growing importance of contact resistance in devices remains a major concern. A significantly lower parasitic S/D resistance could also be obtained thanks to the use of epitaxial and metal wrapped-around contacts (WAC) [2]. In addition, alternatives to Si channel materials (SiGe or Ge) and new device concepts such as 3D transistor stacking, complementary FET (CFET) and gate-all-around (GAA) nanosheet devices, all considered for the upcoming technological nodes of 3 nm and below [3], require process temperatures < 500ºC.To meet these temperature requirements, epitaxial processes based on the combination of high order Si and Ge precursors are explored together with low temperature Cl2 etching. The strength of this approach has already been demonstrated by the successful implementation of Ge/SiGe stacks and Ge S/D deposited at low temperature for the production of pMOS Ge GAA devices exhibiting excellent electrostatic control at sub-30 nm gate lengths [3].In this contribution, we use advanced low temperature epitaxial processes to enable cutting-edge applications. Complex and highly strained multi stacks are pseudomorphically grown with a limited thermal budget. The compositional contrast between the different parts of the stack, combined with very sharp interfaces, allows for the selective removal of sacrificial layers and the formation of active channels being totally isolated from parasitic channels in the substrate (Fig. 1(a)). In addition, highly B (Fig. 1 (b)) or B+Ga co-doped SiGe layers are grown at temperatures down to 400ºC with an active doping concentration exceeding 1x1021 cm-3. Epitaxial WAC structures are finally demonstrated Fig. 1 (c).[1] H. Wu et al., IEDM, 819 (2018)[2] S. Chew et al., 2017 IEEE Int. Interconnect Techn. Conf. (IITC), 1 (2017)[3] E. Capogreco, et al., Symposium on VLSI Technology , T94 (2019) Fig. 1. Example applications for advanced low temperature epitaxial growth processes. (a) HAADF-STEM cross-section image of a SiGe/Si multi stack used for the fabrication of nanosheet device with integrated bottom SiN/SiCO isolation; (b) B concentration profile measured by SIMS on a SiGe:B layer grown at low temperature, resulting in a carrier concentration above ~1x1021 cm-3. (c) Low temperature SiGe:B grown on Si fins demonstrating epitaxial WAC. Figure 1

Significant improvement of 2,9-DPh-DNTT organic thin-film transistors based on organic heterojunction buffer layer

High-mobility thin film transistors of para-sexiphenyl (p-6P)/2,9-diphenyl-dinaphtho[2,3-b:2′,3′-f]-thieno[3,2-b] thiophene (2,9-DPh-DNTT) are demonstrated by employing copper hexadecafluorophthalocyanine (F16CuPc), cobalt (II) hexadecafluoro-phthalocyanine (F16CoPc) and molybdenum oxide (MoO3) as buffer layers. The highest field-effect mobility of 9.3 cm2/Vs is achieved by using the F16CoPc buffer layer, which is the highest reported mobility for polycrystalline 2,9-DPh-DNTT thin film transistors. The improvement of the device performance is due to reducing device contact resistance between metal electrodes and the organic semiconductor and improving the carrier injection. Based on the optimized results, we fabricated an OTFT array consisting of p-6P/2,9-DPh-DNTT OTFTs with F16CoPc as the buffer layer by photolithography. A high mobility of 2.7 cm2/Vs and a low VT of −2.3 V are achieved which proved that 2,9-DPh-DNTT is an excellent organic semiconductor in the field such as a large-area display and sensor matrix, etc.

(Invited) Highly Doped Si1-XGex Epitaxy in View of S/D Applications

Modern CMOS devices are a fertile ground for innovation, as scaling and conceptual evolutions drive regular updates in process and material specifications. Requirements are usually set by device modelling, which defines the performance objectives for a new technology. Simulations recently carried out assuming fin [1] and nanosheet [2] field effect transistor geometries have for instance highlighted limitations due to the growing importance of contact resistance in devices with reduced dimensions. To meet the objectives, source/drain (S/D) contact regions receive a specific attention and aggressive targets are set to enable higher-performing generations of devices. Within this framework, contact resistivities (rc) lower than 1E-9 W.cm2 are specified for sub 5 nm technology nodes. Reaching this objective for n and p-type S/D is a challenging task, both from the perspectives of obtaining the right materials and of reliably measuring low rc values [3]. Several material parameters are known to affect the final contact resistivity. Novel epitaxial growth schemes are considered to maximize the active doping concentration to narrow the Schottky barrier at the metal - S/D interface. Additionally, the composition of and strain relaxation in the S/D layer affect band alignment and must be considered.This contribution focuses on S/D epitaxial layers grown and in-situ doped by chemical vapor deposition, and on the properties of fabricated Ti / p-Si1-xGex contacts. For a given Ge concentration, the Ti / Si1-xGex:B contact resistivity is minimized for an optimized range of Si1-xGe1-x:B layer thickness, and increases as the layer relaxes [4]. With increasing Ge content, the rise in contact resistivity begins for lower thicknesses. Observed trends are nevertheless similar (Fig. 1). Please note that the targeted boron concentration is constant within each series of samples but differs for different Ge concentrations. The variations in resistivity and contact resistivity as seen for different series are assigned to the different boron concentrations rather than the variation in Ge concentration. Indeed, lower resistivities and contact resistivities are measured for higher active boron concentrations.The correlation between the electrical properties and layer thickness reported in figure 1 confirms that preserving strain in the Si1-xGex:B S/D material is important. However, the increase in S/D layer and contact resistivities with increasing layer thickness is not caused by the (small) increase in electrical band gap. Instead, B incorporation during epitaxial growth is affected by the initiation of layer relaxation and decreases as the material relaxes (R) as can be concluded from Fig. 2. This figure shows the boron concentration as function of depth for two partially relaxed Si1-xGex with 25% and 65% Ge, respectively. A reduction in B incorporation when the S/D material thickness exceeds the critical thickness for strain relaxation (tc) is observed for the whole range of Ge concentrations. This phenomenon is supported by density functional theory results which indicate a reduced propensity of boron to occupy substitutional lattice sites in relaxed Si1-xGex.

Graphene based Van der Waals contacts on MoS2 field effect transistors

Device performance of two dimensional (2D) material based field effect transistors is severely limited by the relatively high contact resistance encountered at the contact-channel interface. Metal-graphene hybrid contacts have been previously used to improve the contact resistance of devices based on thick exfoliated materials. Here we report a novel 2D FET fabrication process entailing the transfer of metal-graphene hybrid contacts on top of 3 monolayer-thick chemical vapor deposition (CVD) MoS2, enabling a lithography free contacting strategy, with respect to MoS2. Three different metal-graphene stacks consisting of Ni, Pd and Ru, have been fabricated, transferred onto MoS2 and characterized extensively using electrical and physical characterization techniques. We find strong correlation between the measured electrical characteristics and physical characterization of the contact interface. From Raman spectra measurement, maximum charge transfer of 1.7 × 1013 cm−2 is observed between graphene and Ru, leading to an improved contact resistance for MoS2 devices with Ru-Gr contacts. Ru-Gr contact shows the lowest contact resistance of 9.34 kΩ · µm among the three metal-graphene contact stacks reported in this article. This contact resistance is also the best among reported CVD grown graphene contacted MoS2 devices. Using more than 400 devices, we study the impact of the different metal-graphene contacts on other electrical parameters such as hysteresis, sub-threshold swing and threshold voltage. The metal-graphene contact stack transfer technique represents a technologically relevant contacting approach which can be further up-scaled to larger wafer areas.

Extending the metal-induced gap state model of Schottky barriers

Fermi level pinning at Schottky barriers strongly limits the minimization of contact resistances in devices and thereby limits the scaling of modern Si electronic devices, so it is useful to understand the full range of behaviors of Schottky barriers. The authors find that some semiconductor interfaces with compound metals like silicides have apparently weaker Fermi level pinning. This occurs as these metals have an underlying covalent skeleton, whose interfaces with semiconductors lead to miscoordinated defect sites that create additional localized interface states that go beyond the standard metal-induced gap states (MIGSs) model of Schottky barriers. This causes a stronger dependence of Schottky barrier height on the metal and on interface orientation. These states are argued to be an additional component needed to extend the MIGS model.

Electron Charge Transport in Non-Peripherally Substituted Copper Phthalocyanine

Bottom-gate, bottom-contact organic thin film transistors (OTFTs) were fabricated using solvent soluble copper-1,4,8,11,15,18,22,25-octakis(hexyl)phthalocyanine as the active semiconductor layer. The compound was deposited as 70 nm thick spin-coated films onto gold source-drain electrodes supported on octadecyltrichlorosilane treated 250 nm thick SiO2 gate insulator. The analysis of experimental results showed the n-type field effect behaviour. Devices annealed at 100 oC under vacuum were found to exhibit the field-effect mobility of 0.0989 cm2 V−1 s−1, with an on/off current modulation ratio of ∼106, a reduced threshold voltage of 0.7 V and a sub-threshold swing of 2.12 V decade−1. The variations in surface morphology of the devices are found reflected considerably in the electrical measurements. The device contact resistance was found to be decreased as the gate bias increased and also with the annealing.

The role of SnO2 high resistivity transparent layer deposited onto commercial conducting glass as front contact in superstrate configuration thin films solar cells technology: influence of the deposition technique

The deposition of a high resistivity transparent (HRT) oxide between a transparent conductive oxide (TCO) and the window CdS has demonstrated the improvement of performance of CdS/CdTe solar cells, fabricated in the superstrate-configuration. In this work the influence of the pneumatic spray pyrolysis (PSP) and magnetron sputtering techniques on the properties TCO/SnO2/CdS structure through the deposition of the intermediate SnO2 between the commercial conducting glass and CdS window is presented by means of X-ray photoelectron spectroscopy (XPS), secondary ion mass spectroscopy (SIMS), and contact resistance, calculated using transmission line method (TLM), in order to reduce the front contact resistance in devices with superstrate-configuration. The results of this work are applicable to other solar cells in the same configuration as the recent solar cells based on the compound Sb2Se3, where the use of this type of HRT has not been studied.

The role of contact resistance in GeTe and Ge2Sb2Te5 nanowire phase change memory reset switching current

Nanowire (NW) structures offer a model system for investigating material and scaling properties of phase change random access memory (PCRAM) at the nanometer scale. Here, we investigate the relationship between nanowire device contact resistance and reset current (Ireset) for varying diameters of NWs. Because the reset switching current directly affects possible device density of PCRAM NWs, it is considered one of the most important parameters for PCRAM. We found that the reset switching current, Ireset, was inversely proportional to the contact resistance of PCRAM NW devices decreasing as NW diameter was reduced from 250 nm to 20 nm. Our observations suggest that the reduction of power consumption of PCRAM in the sub-lithographic regime can be achieved by lowering the contact resistance.

Ion Implantation Applications for Advanced Device Scaling

In the past decade, the surge of mobile devices has been tremendous. These novel mobile devices have all functionalities to communicate as well as gaming, computing capabilities etc. Obviously with such enabling features, mobile devices are a very significant part of the semiconductor market. To address the stringent requirements in terms of battery lifetime, device speed and scaling, the mobile devices processing needed innovations. To achieve these, novel processing techniques in the front end of line (e.g., strained silicon channel, High-K Metal Gate) and novel contact materials for back end of line have been implemented. In addition, the process margin is becoming a key factor as the cost and complexity of making devices is increasing. One dramatic change to address device scalability is the moved to Multigate architecture such as the FinFET (Field Effect Transistor) or GAA (Gate All around Transistors). In fact, the FinFET architecture enables to virtually increase the gate length of the device leading to better electrostatic performance. For FinFET device, due to its three dimension architecture, the junction formation has some unique process requirements. Unlike planar devices, FinFET device requires side wall doping as well as excellent control of junction planarity. In addition, due to the small volume involved with narrow Fin, controlling the Fin damage is becoming a key challenge. To address these, damage engineering for tilted beamline implantation as well as plasma doping approaches have generated great interest. The paper demonstrates the benefits of these novel implantation concepts using different metrologies and device structures. We discuss that these novel implant techniques can also be applied to other applications to further improve FinFET device performances. In order to achieve the multi-threshold voltage (Vth) needed for SoC applications, the work function tuning by implantation is of great interest. Several ideas have been discussed in literature for channel and/or metal gate Vth tuning and are reviewed in this paper. Another key area of interest is the reduction of the device contact resistance. From an implant perspective, several approaches have been reported such as pre-silicide pre-amorphization technique, Schottky Barrier Height (SBH) reduction, or Dopant Segregation Schottky (DSS). We demonstrate that a combination of these contact implant techniques along with advanced annealing provide ways to meet the contact resistance and uniformity need. To further increase channel mobility, new channel materials are being considered to further boost device performance. For PMOS, the move to SiGe or Ge channels is very attractive, however formation of such Fin channels is a challenge. From a diffusion perspective, the main p-type dopant (Boron) has a lower diffusivity as Germanium concentration increases, which may benefit Short Channel Control. However, for NMOS devices, n-type dopants (Arsenic and Phosphorus) diffuse faster than in silicon as well as have lower solubilities. This results in a strong challenge in forming a highly active as well as defect-free junction. We will demonstrate that damage engineering via a combination of novel implant and anneal technologies for junction, damage, and strain will become even more critical for these novel channel materials. Finally we will review the change of architecture to Gate All Around and briefly discuss the multiple implant applications for those new devices.

High Quality Silicon Cap Layer for 28nm and Beyond PMOS Processes

High quality embedded SiGe film with [Ge] concentration > 35% with Epitaxial grown Silicon (Si) cap layer has been demonstrated on a state-of-the-art 28nm logic flow. Si cap layer is a significant benefit to SiGe device for p-MOSFET contact resistance improvement but adversely affects the SiGe film strain relaxation especially for the high concentration [Ge] (> 35%). High quality, relaxation free SiGe film, with surface roughness improved from 4.21 to 0.65nm and 30% device contact resistance reduction are characterized in this work.

Effect of compression on PFSA-ionomer morphology and predicted conductivity changes

Ion-conductive membranes used in energy devices are always under compression to minimize a device's contact resistance. In this paper, the conductivity and nanostructure of Nafion membrane, a commonly used ionomer in many electrochemical energy applications, are investigated under compression. Hydrophilic-domain spacing as a function pressure is determined both in the plane (face-on imaging) and thickness (edge-on imaging) directions using small-angle X-ray scattering (SAXS). SAXS results suggest a similar nanostructure in all directions indicating lack of a strong anisotropy when not under compression. However, compressing the membrane induces structural anisotropy where domain spacing gets smaller in the compression (thickness) direction while it elongates in the plane of the membrane. From the domain spacing and water content under compression, the change in conductivity is calculated as a function of pressure and compared with measured data. The findings of this work provide insight into the effect of compression on the three-dimensional morphology of a PFSA membrane and its conductivity, issues that have not been previously explored and are critical to the understanding of ion-conductive membranes.

Estimation of Fermi Level Changes Caused by Changes in Ambient Conditions around Organic Semiconductors by Seebeck Effect Measurement

By using the Seebeck effect measurement, we investigated changes in the Fermi level of pentacene caused by changes in ambient conditions. Since, measurement of Seebeck voltage is not accompanied with current flow, this measurement is not affected by contact resistance of devices. Thus, we can measure Fermi level change caused by ambient change without influence of contact resistance.

Estimation of Fermi Level Changes Caused by Changes in Ambient Conditions around Organic Semiconductors by Seebeck Effect Measurement

By using the Seebeck effect measurement, we investigated changes in the Fermi level of pentacene caused by changes in ambient conditions. Since, measurement of Seebeck voltage is not accompanied with current flow, this measurement is not affected by contact resistance of devices. Thus, we can measure Fermi level change caused by ambient change without influence of contact resistance.

The electrical property of plasma-treated Ta/TaN x diffusion barrier

In copper damascene processes, a barrier film is necessary to prevent copper diffusion into a dielectric layer as well as to improve the adhesion between the copper and dielectric layers. The tantalum/tantalum nitride (Ta/TaN x ) composite film deposited by ionized metal plasma is widely used as the copper diffusion barrier layer due to its effective barrier property and chemical inertness. To reduce the contact resistance of devices, re-sputtering technology using biased Ar plasma was applied to remove the barrier layer from bottoms in advanced metallization processes. This study found that the film resistivity of Ta films depended on the re-sputtering amount of under TaN x films. As the re-sputtering amount of under TaN x films increased, the resistivity of the Ta/TaN x bi-layer decreased and saturated to a limited value. The behavior resulted from the phase transformation of Ta films on different TaN x substrates.

High‐Resolution Characterization of Pentacene/Polyaniline Interfaces in Thin‐Film Transistors

AbstractWe present the first detailed report that directly correlates the reduced contact resistance in organic thin‐film transistors (TFTs) with fundamental structural and morphological characterization at the organic semiconductor/conducting polymer interface. Specifically, the pentacene grains are similar in size and continuous across the channel/electrode interface in bottom‐contact TFTs with polyaniline (PANI) electrodes. On a molecular level, the fused rings of pentacene are oriented perpendicular to the surface both in the channel and on PANI. Accordingly, the contact resistance is small in such devices. In TFTs with gold electrodes, however, the pentacene grains are different in size and are discontinuous across the channel/electrode interface. Further, the fused rings of pentacene are oriented perpendicular to the channel surface and parallel to the gold surface. Such differences across the channel/electrode interface lead to structural and electronic disorder, which manifests itself as a significantly larger contact resistance in devices with gold electrodes.