Contact Plug Research Articles

A novel nanoprobing analysis flow by using multi-probe configuration to localize silicide defect in MOSFET

It is demonstrated that nanoprobing technique is superior in localizing silicide defect rapidly in metal-oxide-semiconductor field-effect transistor (MOSFET). Cobalt silicide (CoSi2) as an interfacial material below tungsten contact plug, various types of defects about CoSi2 often cause leakage current in MOSFET, so close studies of problematic silicide is significant regarding MOSFET reliability enhancement. When one MOSFET in a combinational logic circuit is suspected of anomaly, because this kind of circuit is composed of several devices which are sometimes arranged in an active area (AA) of unique geometric shape, it is impossible to collect MOSFET characteristic correctly based on regular nanoprobing flow since conventional method hits limit for combined circuits measurement. Such circumstance almost impedes failure analysis (FA) in device level. Nevertheless, relying on our alternative strategy of multi-probe configuration, a novel nanoprobing analysis flow is adopted for device examination. It is shown that exact I-V characteristic of failed device can be captured by proposed workflow. Following I-V curve analysis further reveals an evident electrical signature of abnormal abrupt junction. It corresponds to an active area shorting with its surrounding nwell region. In addition, sophisticated leakage current behaviors are exhaustively interpreted by simplified models. Eventually, we confirmed CoSi2 encroachment from the active area into nwell by the means of transmission electron microscopy (TEM) analysis. This paper presents an effective analysis to identify leaky junction of MOSFET in logic circuit that is rarely reported before. Furthermore, our exploration exhibits impressive flexibility of nanoprobing analysis in terms of localizing unusual silicide defect, so nanoprobe analysis is clearly an attractive option to optimize MOSFET manufacturing.

Direct-write formation of integrated bottom contacts to laser-induced graphene-like carbon

We report a simple, scalable two-step method for direct-write laser fabrication of 3D, porous graphene-like carbon electrodes from polyimide films with integrated contact plugs to underlying metal layers (Au or Ni). Irradiation at high average CO2 laser power (30 W) and low scan speed (∼18 mm s)−1 leads to formation of ‘keyhole’ contact plugs through local ablation of polyimide (initial thickness 17 μm) and graphitization of the plug perimeter wall. Top-surface laser-induced graphene (LIG) electrodes are then formed and connected to the plug by raster patterning at lower laser power (3.7 W) and higher scan speed (200 mm s)−1. Sheet resistance data (71 ± 15 Ω sq.)−1 indicates formation of high-quality surface LIG, consistent with Raman data which yield sharp first- and second-order peaks. We have also demonstrated that high-quality LIG requires a minimum initial polyimide thickness. Capacitance data measured between surface LIG electrodes and the buried metal film indicate a polyimide layer of thickness ∼7 μm remaining following laser processing. By contrast, laser graphitization of polyimide of initial thickness ∼8 μm yielded devices with large sheet resistance (>1 kΩ sq.)−1. Raman data also indicated significant disorder. Plug contact resistance values were calculated from analysis of transfer line measurement data for single- and multi-plug test structures. Contacts to buried nickel layers yielded lower plug resistances (1-plug: 158 ± 7 Ω , 4-plug: 31 ± 14 Ω) compared to contacts to buried gold (1-plug: 346 ± 37 Ω , 4-plug: 52 ± 3 Ω). Further reductions are expected for multi-plug structures with increased areal density. Proof-of-concept mm-scale LIG electrochemical devices with local contact plugs yielded rapid electron transfer kinetics (rate constant k 0 ∼ 0.017 cm s−1), comparable to values measured for exposed Au films (k 0 ∼0.023 cm s)−1. Our results highlight the potential for integration of LIG-based sensor electrodes with semiconductor or roll-to-roll manufacturing.

Origins of wear-induced tungsten corrosion defects in semiconductor manufacturing during tungsten chemical mechanical polishing

During chemical mechanical polishing (CMP) process optimization, a unique corrosion defect was identified in the tungsten (W) contact plugs, which were investigated to develop practical solutions to improve CMP mass productivity. The corrosion defect occurred in the absence of external incident energy and was observed to occur only at the W plugs connected to the P+/n-well close to the wafer edge. To examine the root cause of the corrosion, a series of experiments was carried out at each W CMP step, using in-line defect inspection. Additional experiments were conducted using on-line inductively coupled plasma mass spectrometry (ICP-MS) to understand pH- and potential-dependent electrochemical dissolution behaviors of W. Experimentally, W corrosion was confirmed to be exacerbated if the surface oxide of the W plugs is removed by the deionized water (DIW) rinsing step under wafer pressurization, then exposed to DIW and alkaline cleaning solution. Although the DIW rinsing step is commonly performed to clean polishing pads right after the main polishing, a small amount of applied pressure (0.5 psi) without slurry supply can lead to corrosion defects. This wear-induced corrosion of the W plugs can be prevented by removing the applied pressure during the post DIW rinsing step of W CMP.

Study on Abnormally Accelerated Oxidation of Tungsten Plugs during Tungsten Chemical Mechanical Polishing in Semiconductor Manufacturing

The root cause of the abnormally accelerated oxidation behavior occurring in tungsten (W) chemical mechanical polishing (CMP) has been performed to provide guidance to those developing practical solutions. Abnormal oxidation behavior refers to the case where the surrounding W contact plugs are normal, but oxidation occurs rapidly and abruptly only at a specific contact, causing device failure. For this study, the failure location was determined through a wafer-level probe test of fully processed DRAM device wafers. With this specific location information, a top-down view inspection was performed on the location immediately after CMP to assess the characteristics, and then a wafer-level probe test was conducted to confirm the failure. In this way, the top-down view plug images immediately after CMP and their potential failure were classified. Based on these results, the CMP process step involving abnormal oxidation was determined, as were the conditions needed to cause abnormal oxidation. Potential solutions to abnormal oxidation are presented based on our results.

Synthesis of Dilute Phosphorous-Embedded Co Alloy Films on a NiSi Substrate with a Superior Gap-Filling Capability for Nanoscale Interconnects

Nanoscale cobalt interconnection wire has a lower mean free path of electrons to reduce the electrical resistivity, therefore it has been increasingly studied as a promising interconnect material to replace the conventionally used copper in state-of-the-art nanoscale devices. This process further limits the space for barrier/seed layer deposition to conformally fill the narrow trenches/contact holes in nanoscale devices. Thus, an electrochemical approach not involving a conventional high-resistivity barrier is presented to study the gap-filling capability and properties of Co(P) films with a controlled composition on a NiSi substrate. Examining electrodeposited Co(P) films reveals that the composition is determined mainly by the deposition potential instead of the amount of NaH2PO2 in the electrolytes, yielding a film with a phosphorous concentration lower than 2.62 at.%. The lightly doped Co(P) film has an hexagonal close-packed Co structure with phosphorous atoms at the interstitial lattice site. A chronoamperometry study on the current transient during the electrochemical deposition indicates that NaH2PO2 addition can enhance the deposition of the Co(P) films. Hence, the Co(P) film developed here is capable of gap filling nanoscale trenches up to an aspect ratio of 5 and is practical as a contact plug material for NiSi in nanoscale devices.

Effect of Contact Plug Deposition Conditions on Junction Leakage and Contact Resistance in Multilevel CMOS Logic Interconnection Device.

Here, we developed the optimal conditions in terms of physical and electrical characteristics of the barrier and tungsten (W) deposition process of a contact module, which is the segment connecting the device and the multi-layer metallization (MLM) metal line in the development of 100 nm-class logic devices. To confirm its applicability to the logic contact of barrier and W films, a contact hole was formed, first to check the bottom coverage and the filling status of each film, then to check the electrical resistance and leakage characteristics to analyze the optimal conditions. At an aspect ratio of 3.89:1, ionized metal plasma (IMP) Ti had a bottom coverage of 40.9% and chemical vapor deposition (CVD) titanium nitride (TiN) of 76.2%, confirming that it was possible to apply the process to 100 nm logic contacts. W filling was confirmed, and a salicide etching rate (using Radio Frequency (RF) etch) of 13–18 Å/s at a 3.53:1 aspect ratio was applied. The etching rate on the thermal oxide plate was 9 Å/s. As the RF etch amount increased from 50–100 Å, the P active resistance increased by 0.5–1 Ω. The resistance also increased as the amount of IMP Ti deposition increased to 300 Å. A measurement of the borderless contact junction leakage current indicated that the current in the P + N well increased by more than an order of magnitude when IMP Ti 250 Å or more was deposited. The contact resistance value was 0.5 Ω. An AC bias improved the IMP Ti deposition rate by 10% in bottom coverage, but there was no significant difference in contact resistance. In the case of applying IMP TiN, the overall contact resistance decreased to 2 Ω compared to CVD TiN, but the distribution characteristics were poor. The best results were obtained under the conditions of RF etch 50 Å, IMP Ti 200 Å, and CVD TiN 2 × 50 Å.

Table-Top Evaluation Approach to Design Post-CMP Clean Chemicals

In todays advanced integration technology, there have been tough requirements for CMP process, particularly for post CMP clean because even minute defects heavily impact on device yield. CMP slurries have small abrasive particles and many additives, which remain on post CMP wafer and cause various types of defect. However, strong bulk chemical cleaners can easily damage a polished surface of wafer. Thus how to strike right balance between high cleanability and low erodibility is major challenge for post CMP clean chemical development. Another large difficulty to develop pCMP clean chemicals is that using full wafer-scale CMP and defect inspection tools takes too much time and cost. As a pCMP clean chemicals manufacturer, we have been trying to introduce a small coupon-scale evaluation metrology so that we can conduct screening tests for many candidate chemicals and their combinations in a quick and least cost manner. This metrology includes electrochemical analysis, surface analysis and also benchmarking test using a table-top polisher and a lab-size cleaning unit. In this paper, we will report how we can apply this coupon-scale evaluation metrology to post CMP clean evaluation for contact plugs. In CMP process involving contact plugs between transistor and M1, great care is necessary because the finest patterns are formed in this region. Typically, tungsten (W) is employed for plug metal and acidic chemicals have been used for post CMP clean because of its strong removability of iron (Fe) that is contained in slurries as a catalyst for W film oxidation. However acidic chemicals often do not have adequate particle removability. Therefore it is one of the top issues to make Fe removability and particle removability compatible. And also it is desirable that we can rapidly evaluate Fe and particle removability in small lab-scale. One of approach we would like to present is evaluation approach to Fe removability. Fe can be quantified by TXRF or VPD-ICP-MS after wafer polish and clean with CMP tools. But it is not practical to use every time these methods in initial screening stage due to their cost. For this purpose, we have applied electrochemical measurement approaches such as Tafel-plot and OCP (Open Circuit Potential) to estimate Fe removability for various chemicals. Tafel plot measurement provides corrosion current (Ecorr). A cleaner that has higher Fe removability shows higher corrosion current because the cleaner solution dissolves passivation film like a Fe2O3. So this method can compare Fe removal efficiency between cleaners. Open Circuit Potential (OCP) reflects surface passivation film condition. When passivation film is formed on surface, OCP rises because oxidation current becomes small. In contrast, when passivation film is removed, OCP drops. Therefore Fe removal speed can be compared by measuring time-dependent OCP for iron electrode with passivation layer in cleaner solution. In this presentation we will review details of metrology and also comparison of results between coupon-size, lab-level screenings and wafer size tests. Figure 1

Co and CoTix for contact plug and barrier layer in integrated circuits

Continuous transistor scaling in integrated circuits brings about a significant increase of electrical resistance in the source/drain area. To alleviate the problem, this paper proposes Co/CoTix to replace conventional contact plug/barrier materials of W/TiN/Ti. Co and CoTix amorphous alloy layers were deposited on SiO2/p-Si. The 3nm-thick amorphous CoTix layer promoted adhesion between Co and SiO2. The resistivity of the 150nm-thick Co film on CoTix showed low film resistivity close to bulk Co value both in as-deposited and annealed conditions. The amorphous structure of the CoTix layer was maintained throughout annealing up to 500°C. Capacitance-voltage measurement of Co/CoTix/SiO2/p-Si samples showed a good diffusion barrier property of the CoTix layer between Co and SiO2 after thermal stress as well as bias thermal stress. The obtained results indicated that Co/CoTix can be good candidate materials for contact plug and diffusion barrier in advanced integrated circuits.

Advanced characterizations of fluorine-free tungsten film and its application as low resistance liner for PCRAM

Using a metal-organic tungsten based precursor, a fluorine-free tungsten thin film has been obtained. The process deposition recipe includes a plasma-enhanced CVD (PECVD) step and atomic layer deposition (ALD) cycles. A set of physicochemical characterizations including X-ray reflectivity (XRR), in-plane X-ray diffraction (XRD), wavelength dispersive X-ray fluorescence (WDXRF), plasma profiling time of flight mass spectrometry (PPTOFMS) and microscope observations has been realized in order to study the W thin film structure and properties. The film is perfectly conformal whatever the structure size investigated (from tens of nanometers to micrometers wide). It was also highlighted that the F-free W film exhibits the lowest electrical resistivity phase (α-W) but is not pure. Indeed, in addition to a top surface oxidation, a layer located at the W film / substrate interface is present. This interface layer (IL) contains impurities, including carbon and oxygen, due to ligand decomposition. This IL might be deposited during the soak step or during the PECVD step.The W liner with thicknesses ranging from 3 to 4nm has been implemented on PCRAM structures in order to evaluate its impact on contact plug resistivity. First electrical results are promising and demonstrate the interest of using a F-free low resistance W liner. At the aspect ratio studied, the gain in terms of contact plug resistivity is about 20% compared to the process of reference using a TiN liner. Modeling shows that this benefit is mainly due to the reduction of interface resistances.

Low Power Phase Change Memory With Vertical Carbon Nanotube Electrode

Phase change memory (PCM) formed by Ge2Sb2Te5 (GST) on vertical carbon nanotube (CNT) filled contact plug is demonstrated in this paper. In order to achieve compatibility with the underlying process, the CNTs are synthesized using nickel catalyst at a low temperature. Reasonable contact characteristics between the CNTs and GST are achieved without material compatibility problem. Due to the small contact size of the CNT to the phase change material, a significant reduction in programming power is achieved compared to metal contact at the same via size. The temperature simulation result shows that the CNT filled via helps to reduce the programing area. The fabricated PCM on CNT filled via is able to endure more than 104 SET/RESET cycles without observable degradation.

Gate contact resistive random access memory in nano scaled FinFET logic technologies

A full logic-compatible embedded gate contact resistive random access memory (GC-RRAM) cell in the CMOS FinFET logic process without extra mask or processing steps has been successfully demonstrated for high-density and low-cost logic nonvolatile memory (NVM) applications. This novel GC-RRAM cell is composed of a transition metal oxide from the gate contact plug and interlayer dielectric (ILD) in the middle, and a gate contact and an n-type epitaxial drain terminal as the top and bottom electrodes, respectively. It features low-voltage operation and reset current, compact cell size, and a stable read window. As a promising embedded NVM solution, the compact one transistor and one resistor (1T1R) cell is highly scalable as the technology node progresses. Excellent data retention and cycling capability have also been demonstrated by the reliability testing results. These superior characteristics make GC-RRAM one of a few viable candidates for logic NVM for future FinFET circuits.

Improvement of the short channel effect in PMOSFETs using cold implantation

In this paper, to suppress transient enhanced dopant diffusion and improve short channel effects, cold implantation (cold-IIP) was applied to contact PLUG implantation in P-channel metal oxide semiconductor field effect transistors (PMOSFETs). A shallow dopant profile was formed by the suppression of transient enhanced diffusion (TED) due to the reduction of end-of-range (EOR) defects. Threshold voltage roll-off and off current (Ioff) increment, which are caused by a reduction in the distance between the gate and contact, were improved compared with room temperature implantation (RT-IIP). Additionally, the drain induced barrier lowering was improved, and the on-current improvement was attributed to reducing the contact resistance through the reduction of EOR defects. The contact resistance was reduced by ∼6% of the RT-IIP. In the DRAM device, the standby current at a short propagation delay time (tPD) was reduced effectively due to the decrease in the Ioff and contact resistance for the cold-IIP case.

Carbon Nanotube Contact Plug on Silicide for CMOS Compatible Interconnect

Carbon nanotube (CNT) filled contact plugs with silicide as the bottom electrode have been demonstrated in this letter. Nickel has been used as the main catalyst to achieve CMOS compatibility. By modifying the catalyst from a pure Ni single layer structure to a Ni/Al/Ni multilayer composite, uniform selective CNT growth on Ti silicide substrate has been achieved. At a low temperature of 450 °C, the vertically aligned CNTs with a density of 1.1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> tubes/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> inside the silicon dioxide contact plug are formed without the need of catalyst patterning. Four-point Kelvin structures are designed to measure the resistance of the CNT filled contact plugs. Measurement results show that an ohmic contact plug resistance of 216 Ω·μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is obtained.

High-Responsivity Low-Voltage 28-Gb/s Ge p-i-n Photodetector With Silicon Contacts

We report a high-performance germanium waveguide photodetectors (WPDs) without doping in germanium or direct metal contacts on germanium, grown on and contacted through a silicon p-i-n diode structure. Wafer-scale measurements demonstrate high responsivities larger than 1.0 A/W across the C-band and low dark current of ~3 nA at -1 V and ~8 nA at -2 V. Owing to its small dimensions, the Ge WPD exhibits a high optoelectrical 3-dB bandwidth of 20 and 27 GHz at low-bias voltages of -1 and -2 V, respectively, which are sufficient for operation at 28 Gb/s. The reduced processing complexity at the tungsten contact plug module combined with the high responsivity makes these Ge WPD devices particularly attractive for emerging low-cost CMOS-Si photonics transceivers.

The Dual-Heterojunction Ge on Si Photodetector

Metal contact plugs are today commonly used to establish electrical connection to the anode and cathode electrodes of Ge on Si integrated photodetectors. While large progress have been made in optimizing these contacts, scattering loss at the metal regions still remains the most important efficiency limiting factor. In addition, the process used to form the contacts is challenging because of the relatively high attack rate of Ge in aqueous solutions. In this paper an alternative way of building and contacting a Ge diode is presented: leveraging the presence of the Si substrate, highly doped n- and p-type Si regions are formed on the sides of the Ge region replacing metal contacts. These both serve to establish the built in potential in the diode as well as offer a low resistance path for the photocurrent extraction

The Dual-Heterojunction Ge on Si Photodetector

Metal contact plugs are today commonly used to establish electrical connection to the anode and cathode electrodes of Ge on Si integrated photodetectors. While large progress has been made in optimizing these contacts, scattering loss at the metal regions still remains the most important efficiency-limiting factor. In addition, the process used to form the contacts is challenging because of the relatively high attack rate of Ge in aqueous solutions. In this paper an alternative way of building and contacting a Ge diode is presented: leveraging the presence of the Si substrate, highly doped n- and p-type regions are formed on the sides of the Ge region. These both serve establishing the built in potential in the diode as well as offering a low resistance path for the photocurrent extraction. Devices built using this approach match and sometime exceed the performance of the classic “PIN” homojunction ones.In this paper experimental results from a number of dual heterojunction Ge on Si devices based on the LuxG process (Luxtera’s integrated sislicon photonic process) will be presented and discussed.

A new laterally conductive bridge random access memory by fully CMOS logic compatible process

This paper proposes a novel laterally conductive bridge random access memory (L-CBRAM) module using a fully CMOS logic compatible process. A contact buffer layer between the poly-Si and contact plug enables the lateral Ti-based atomic layer to provide on/off resistance ratio via bipolar operations. The proposed device reached more than 100 pulse cycles with an on/off ratio over 10 and very stable data retention under high temperature operations. These results make this Ti-based L-CBRAM cell a promising solution for advanced embedded multi-time programmable (MTP) memory applications.

Characterization of TiHfN ternary alloy films as a barrier between Cu plug and Si

A TiHfN ternary alloy film is examined as a candidate reliable barrier to replace W with Cu in contact plug with Si. A low-resistivity Ti12Hf32N56 film (∼120 µΩ cm) is successfully obtained by reactive sputtering. The phase stability of the compound with a N-rich composition is observed. This is because both TiN and HfN, the constituents of this compound, have stable phases with N-rich composition and the same crystalline structure, and the TiHfN compound is considered as an alloy of these constituents. The Cu/Si contact model with a 10-nm-thick TiHfN barrier of nanocrystalline texture showed excellent barrier properties with negligible structural changes owing to annealing for 1 h at 500 °C or higher. The excellent barrier properties and low resistivity obtained are attributed to the structure of the alloy film, in which the alloy has a NaCl structure with Ti and Hf atoms randomly substituted at cation sites.

Electrochemical mechanism of layout-dependent corrosion of tungsten in contact plugs

The investigation elucidates electrochemical effect on tungsten (W) contact plugs and proposes front-end-of-the-line semiconductor manufacture processes that are responsible for corrosion involving source/drain implants, rapid thermal anneal (RTA) and nickel silicide (NixSix). W-filled contacts are commonly used in submicron and even nanometer CMOS technology, and the integrity of W contact plugs becomes increasingly critical as transistors continue to shrink. Incomplete W plugs with a recess on the tops of the contacts were observed in N+/n-well locations following W chemical mechanical polishing (WCMP). This phenomenon arises from anodic corrosion since the under-layer P+/p-well and N+/n-well form a PN junction structure, which has built-in potential and promotes the movement of photo-generated electrons during WCMP. The mechanism of the electrochemical effect is elucidated, and a series of experiments indicates a thin NixSix layer, a heavy dosage of source/drain implants and a high RTA temperature promote the formation of corrosion defects.

Optimized Contact Engineering to Maximize Cell Current in NAND Flash Memory Technology

In this research we have confirmed that Nand flash cell current increases by optimization of contact barrier metal (BM) deposition and plug implantation (IIP) doping condition, which result in improved contact resistance (Rc) and cell leakage. Plug IIP dopant, BF2, which has been applied to P-type Transistor (Tr) for lowering Rc sacrifices contact process margin in cell area of n-type occurred by cell leakage. We could dramatically improve P-type Contact Rc and contact process margin by lowering BM deposition process temperature and adopting plug IIP doping with phosphorous (Ph.) respectively