Contact Plug Research Articles

Accurate Method of Measuring Specific Contact Resistivity of Interface between Silicide and Silicon and Its Application

Reduction of specific contact resistivity is one of the key items for downscaling of device feature size. This paper discusses an accurate method of measuring specific contact resistivity by using our simple four-point probe test structure having a small area, the interface resistance of which is to be measured, fabricated on a substrate that has low sheet resistance. We also show its application for direct specific contact resistivity measurements of several systems that have dopant dependence, i.e., the NiPtSi/Si, NiPtSi/SiGe, and Pt silicide systems, as well as the metal-metal system between silicide and contact plug metal.

Interval Scan Inspection Technique for Contact Failure of Advanced DRAM Process using Electron Beam-Inspection System

We have developed a highly sensitive inspection technique based on an electron beam inspection for detecting the contact failure of a poly-Si plugged layer. It was difficult to distinguish the contact failure from normal landing plugs with high impedance. Normally, the thermal annealing method has been used to decrease the impedance of poly-Si plugs and this method increases the difference of charged characteristics and voltage contrast. However, the additional process made the loss of time and broke down the device characteristics. Here, the interval scanning method without thermal annealing was effectively applied to enhance the difference of surface voltage between well-contacted poly-Si plugs and incomplete contact plugs. It is extremely useful to detect the contact failures of non-annealed plug contacts with high impedance.

Barrier layer thickness analysis for reliable copper plug process in CMOS technology

Copper (Cu) replacing conventional tungsten (W) based 1st contact plug has become necessary for high performance CMOS. For a reliable and well optimized Cu plug, process selection and integration of plug diffusion barrier is an important task. In this work, we investigate barriers for Cu plug technology for CMOS process. Single layer TaN and bi-layer Ta + TaN barrier materials were studied for their effectiveness in preventing Cu diffusion into device active regions for backend thermal stress conditions. The degradation of device characteristics was used as monitor of robustness of barrier reliability. Diffusion of Cu in multilayer plug structure is modeled to explain observed stress behavior. From the model studies, the critical barrier layer thickness needed to prevent Cu diffusion is determined. We show than that a ∼7 nm sidewall barrier is effective in preventing Cu diffusion into Si at up to 350 °C/60 min only, while a minimum thickness of ∼10 nm is needed for blocking copper diffusion at 420 °C/30 min. Using multilayer Cu diffusion model, an optimized process window for reliable, low contact resistance Cu plug technology for CMOS process can be obtained.

Simultaneous Formation of NiSi Contact and Cu Plug/Ti Barrier

As an alternative to the W plug used in MOSFETs, a Cu plug with a NiSi contact using Ta / TaN as a diffusion barrier is currently being considered. Conventionally, Ni was first deposited and then NiSi was formed, followed by the barrier and Cu deposition. In this study, Ti was employed as a barrier material and simultaneous formation of the NiSi contact and Cu plug / Ti barrier was attempted. Cu(100 nm) / Ti / Ni(20 nm) with varying Ti thicknesses were deposited on a Si substrate and annealed at <TEX>$4000^{\circ}C$</TEX> for 30 min. For comparison, Cu/Ti/NiSi thin films were also formed by the conventional method. Optical Microscopy (OM), Scanning Probe Microscopy (SPM), X-Ray Diffractometry (XRD), and Auger Electron Microscopy (AES) analysis were performed to characterize the inter-diffusion properties. For a Ti interlayer thicker than 50 nm, the NiSi formation was incomplete, although Cu diffusion was inhibited by the Ti barrier. For a Ti thickness of 20 nm and less, an almost stoichiometric NiSi contact along with the Cu plug and Ti barrier layers was formed. The results were comparable to that formed by the conventional method and showed that this alternative process has potential as a formation process for the Cu plug/Ti barrier/NiSi contact system.

Low-Resistance Carbon Nanotube Contact Plug to Silicon

We demonstrated the integration of carbon nanotubes (CNTs) as the contact plug to the Si MOSFET. A Ti silicide contact layer was introduced between the CNTs and the Si. The open-ended CNT tip connected the metal one on the other end. We study the contact resistivity of the CNT contact plug using the cross-bridge Kelvin test structure, and compare with the W contact plug. The CNT contact plug also showed excellent thermal stability. The electrical and thermal behavior is closely related to the intermediate layer between the CNT and the Si.

Issues and Challenges of Chemical Mechanical Polishing for Nano-scale Memory Manufacturing

AbstractAs the design rule of memory devices is scaled down to nanoscale, the number of the CMP process has increased considerably due to the complexity of integration scheme. The CMP for isolation has increased significantly because the isolation process of metal contact plugs and damascene metallization at nanoscale has been successfully enabled by the CMP. The CMP selectivity, which depends strongly on the chemistry of the slurry, must be tuned for the various new materials. Recently, in order to get over the limitation in lateral shrinkage of the memory device, several emerging applications have been investigated extensively. A vertical integration needs the new CMP process such as high removal rate Cu CMP. Next generation memories need the CMP process for new materials such as GeSbTe, conductive oxide, and magnetic materials. Since any nano-size scratch will be a killer defect at the nanoscale memory, both the CMP equipment and the consumables must be maintained with tighter degree of control specifications.

Switching Power Reduction in Phase Change Memory Cell Using CVD Ge2Sb2Te5 and Ultrathin TiO2 Films

Phase change memory cells were fabricated using plasma-enhanced cyclic chemical-vapor-deposited (GST) thin films deposited on diameter contact plugs formed in a layer. A 2, 4, and thick atomic deposited layer was interposed between the GST and underlayer containing the contact plug. The necessary reset current and power decreased with increasing the interlayer thickness. Adoption of the optimum thickness layer decreased the necessary reset power to of the cell without the layer. This was attributed mainly to the effective heat insulation by the thick layer. The structural investigation and electrothermal simulation results for the fabricated cells showed a good match between the electrical performance and phase changed volume, which can explain the improvement in switching parameters of the proper layer interposed cell.

Local-Topography-Induced Defects during Tungsten Chemical Mechanical Polishing and Their Impact on Back End of Line

As very large scale integrated fabrication technology continuously scales down, the requirements for contact tungsten chemical mechanical polishing (CMP) become more and more stringent. In this paper, we reported newly observed surface particle defects which were confirmed to be slurry particles or residues. These particles were trapped among W plugs and were difficult to be removed with existing cleaning methods and chemicals. Consequently, these particles may give rise to shorts between metal 1 (M1) and contact plugs or cause severe reliability problems, which have been directly revealed by failure analysis. A mechanism of defect-induced short was proposed. In addition, defect counts were found to have a strong correlation with tungsten plug protrusion. With the reduction of plug protrusion, defect counts decrease significantly. Oxide buff is found to be able to effectively control the local plug protrusion. However, due to the inversely proportional relationship between oxide buff and erosion, erosion may get worse if the oxide buff amount is reduced for the purpose of diminishing plug protrusion. An optimized topography before the oxide buff plays an important role in widening the process margin of the oxide buff. A correlation study of erosion and local protrusion is envisioned to be applicable to other CMP processes.

Observation of three-dimensional elemental distributions of a Si device using a 360°-tilt FIB and the cold field-emission STEM system

A technique for preparation of a pillar-shaped specimen and its multidirectional observation using a combination of a scanning transmission electron microscope (STEM) and a focused ion beam (FIB) instrument has been developed. The system employs an FIB/STEM compatible holder with a specially designed tilt mechanism, which allows the specimen to be tilted through 360° [T. Yaguchi, M. Konno, T. Kamino, T. Hashimoto, T. Ohnishi, K. Umemura, K. Asayama, Microsc. Microanal. 9 (Suppl. 2) (2003) 118; T. Yaguchi, M. Konno, T. Kamino, T. Hashimoto, T. Ohnishi, M. Watanabe, Microsc. Microanal. 10 (Suppl. 2) (2004) 1030]. This technique was applied to obtain the three-dimensional (3D) elemental distributions around a contact plug of a Si device used in a 90-nm technology. A specimen containing only one contact plug was prepared in the shape of a pillar with a diameter of 200 nm and a length of 5 μm. Elemental maps were obtained from the pillar specimen using a 200-kV cold-field emission gun (FEG) STEM model HD-2300C equipped with the EDAX genesis X-ray energy-dispersive spectrometry (XEDS) system through a spectrum imaging technique. In this study, elemental distributions of minor elements with weak signals were enhanced by applying principal component analysis (PCA), which is a superior technique to extract weak signals from a large dataset. The distributions of elements, especially the metallization component Ti and minor dopant As in this particular device, were successfully extracted by PCA. Finally, the 3D elemental distributions around the contact plug could be visualized by reconstruction from the tilt series of maps.

Investigation of Detection Limits of Resistive Contact Plugs in Electron Beam Inspection Using Modeling and Simulation

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Electron beam inspection has been commonly used in the semiconductor fabrication process to inspect wafers for defective metal or polysilicon plugs, plugs that fail to make an electrical contact to the underlying circuitry. Recently, there has been interest in using electron beams to inspect plugs that are not necessarily electrically floating but have a high resistive path to ground. This paper addresses the reliability of such an inspection by examining the minimum resistance value that is detectable for a given column condition and gives guidelines for optimal inspection conditions for finding such a defective plug. The investigation is done using a transient simulation in a general purpose 3-D electron beam simulator that uses Monte Carlo simulations to trace the path of an ensemble of charged particles in an electrostatic field and couples with a general purpose Poisson solver that is also used to update the electrostatic fields from evolving charge profiles. </para>

Effects of TiCl4-Based PECVD-Ti/CVD-TiN Barrier Layers on the BF2-Doped Si for Contact Plug Technology

We have performed the investigation of Ti/TiN barrier layers deposited by PECVD of Ti and CVD of TiN using TiCl4 as a reactant on a heavily boron doped Si substrate. High contact resistance arose from both the boron out-diffusion, and high chlorine content in the Ti film with respect to the relatively high, and low process temperatures of PECVD-Ti deposition, respectively. In the optimized PECVD-Ti process condition with the satisfied boron dose in the Si substrate, comparable yields can be achieved with that using the 110nm deep trench Dynamic Random Access Memory (DRAM) technology with PVD-Ti method. Furthermore, using PECVD-Ti/CVD-TiN method for the contact metallization, it can obtain a uniform thickness of liner in the hole-type contact with aspect ratio to 6.

ELECTRICAL PROPERTIES OF Pb(Zr,Ti)O3 FERROELECTRIC CAPACITOR ON TiN/W PLUG STRUCTURE

ABSTRACT We investigated the electrical properties of ferroelectric Pb(Zr,Ti)O3(PZT) capacitor on TiN/W storage node contact plug that is capacitor over bitline(COB) cell structure for a high density ferroelectric memory. In order to protecting TiN/W contact plug from oxidation failure during furnace annealing of PZT capacitor, the oxidation barrier of Ti1 − x Al x N (x∼ 0.25) film was interposed at between Pt/IrO2/Ir bottom electrode and TiN/W plug of the COB cell, resulting in the robust contact resistance property of 27 ohm per contact plug after furnace annealing performed at 600°C in O2 ambient for 90 min. The remanent polarization value and leakage current density of the fully integrated PZT capacitor with a top electrode area of 1.8 × 1.8 um2 on TiN/W contact plug showed 32 μ C/cm2 and 2.5 × 10− 6A/cm2, respectively.

Analytic models for the kinetics of generating a voltage contrast signal from contact plugs used in integrated circuits

Electron beams are commonly used to inspect wafers for defective contact plugs during the manufacturing of semiconductor integrated circuits. The plugs form a part of the overall electrical connection to the transistors. These plugs can fail to make adequate electrical contact to the underlying circuitry. They may also be connected to faulty circuits. As a result, the voltage from such defective plugs evolves differently upon irradiation by an electron beam. The paths of the secondary electrons emitted from a defective plug respond to this voltage, thereby modifying the fraction of the emitted current that reaches a detector as compared to the fraction obtained from a healthy contact plug. This paper analyzes the fundamental kinetics that ultimately produces this contrast in a scanning electron microscope designed for wafer inspection. In particular, the paper investigates the kinetics of secondary electron emission from an isolated, biased plug embedded in a charge-neutral dielectric. It presents analytic models for the dependence of the electron collection efficiency with the plug voltage and an applied vertical field at the wafer. The analytic results are compared with those from numerical simulations to test the assumptions that enter the models. The mathematical derivations may ultimately be used to estimate the signal that can be extracted from plugs at dissimilar potentials.

Effects of TiCl4-Based PECVD-Ti/CVD-TiN Barrier Layers on the BF2-Doped Si for Contact Plug Technology

not Available.

半導体デバイスのコンタクト底部における界面状態解析

半導体デバイスのコンタクト底部における界面状態解析

Characterization of LSCO/Ir and LSCO/Ru Structure as Diffusion Barrier Layers for Highly Integrated Memory Devices

The integration of ferroelectric capacitors into memory cells requires the bottom electrode material to be placed directly over a contact plug. (LSCO) thin film was deposited using dc magnetron sputter-deposition as an electrode material and a diffusion barrier layer for (PZT) thin-film capacitors. The thermal stability and barrier property of LSCO/Ir/poly-Si and LSCO/Ru/poly-Si contact layers for oxygen diffusion were investigated by Auger electron spectroscopy to find a structure suitable for the bottom electrode of integrated ferroelectric capacitors. The LSCO/Ir/poly-Si composite stack showed lower resistivity compared to LSCO/Ru/poly-Si structure and provided good fatigue performance for PZT capacitors. From these results, the LSCO/Ir/Poly-Si is thought to be the available structure for the fabrication of high-density ferroelectric memory. © 2003 The Electrochemical Society. All rights reserved.

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.

Reduction of Whisker-Originated Short between W Polymetal and Contact Plug

ABSTRACTWhisker-originated short in the self-aligned contact (SAC) W polymetal gate was directly observed for the first time. Short points between gate electrodes and poly-Si plugs in the test structure were identified by emission microscope and cross-sectional TEM samples of those points were made by using focused ion beam (FIB).Whiskers are formed during high-temperature processing such as LP-CVD SiN. We have proposed that NH3 de-oxidation step inserted in the SiN deposition sequence is effective for suppressing whisker growth. [1] In this study it was also confirmed that 600°C NH 3 pre-flow improved leakage current between gate electrode and contact plugs.

Iridium Based Electrodes for Ferroelectric Capacitor Fabrication

AbstractIr and its conductive oxide, IrO2, are candidates to replace Pt as the electrodes in ferroelectric capacitors (FECAPs) because of improved endurance (since e.g. Pt/PZT/Pt shows strong fatigue) and also because of the oxygen barrier properties of Ir/IrO2 stacks that enable the fabrication of stacked FECAPs on top of contact plugs. Two important issues related to these electrodes are the control of the ferroelectric layer orientation on top of these materials, as well as material stability (e.g. oxidation and possible growth of large IrO2 crystallites).In this work, we show that IrO2 bottom electrodes affect the crystallization of sol-gel deposited Pb(Zr,Ti)O3 (PZT). While PZT films deposited on (111) Pt show a (111) preferential orientation, IrO2 electrodes nucleate strongly different oriented PZT. Controlling and changing the microstructure of the bottom electrode allows tuning of these PZT orientations and the resulting grain morphology, and, consequently, their FECAP polarization hysteresis properties.

Formation of Tisi2 Thin Films from Chemical Vapor Deposition Using TiI4

ABSTRACTThe formation of TiSi2 films by chemical vapor deposition was investigated for the application as a contact plug material because of its low resistivity, low contact resistance with n+ and p+ Si, and good chemical stability with Si. TiI4 and SiH4 were used as source gases. Since TiI4 is thermodynamically less stable than TiCl4, the deposition temperature of TiSi2 with TiI4 precursor could be lower than that of TiSi2 from TiCl4 precursor. TiSi2 thin films with C49 phase were formed at 650°C on Si (100) wafer, while a Ti5Si3 phase was formed at 650°C on SiO2 substrate. The resistivity of the C49 phase films was 210 μΩ-cm. The C49 phase was completely transformed into a C54 phase above 800°C annealing in an N2 atmosphere and the resistivity reduced to 34 μΩ-cm. We were able to deposit TiSi2 films at lower temperature using TiI4 precursor, compared to TiCl4 precursor. The Cl and HCI byproducts originated from TiCl4 can be excluded using TiI4 precursor.