Contact Etch Stop Layer Research Articles

Effect of Etch Stop Layer Stress on Negative Bias Temperature Instability of Deep Submicron p-Type Metal–Oxide–Semiconductor Field Effect Transistors with Dual Gate Oxide

Negative bias temperature instability (NBTI) in a dual-gate-oxide complementary metal–oxide–semiconductor (CMOS) process induces threshold voltage (Vt) shift and has become a crucial challenge in designing advanced analog or mixed-signal circuits. In this paper, the impact of the stress from a contact etch stop layer (CESL) on the NBTI of dual-gate-oxide input/output (I/O) p-type MOS field effect transistors (P-MOSFETs) is investigated in detail. Experimental results show that applying tensile stress can suppress NBTI-induced Vt shift more significantly than applying compressive stress, thus becoming a simple and effective method of relieving NBTI.

Nonuniform Mobility-Enhancement Techniques and Their Impact on Device Performance

Nowadays, process-induced stress is the preferential industrial method to enhance circuit performances. One of the most popular techniques is the strain induced by contact etch-stop layer. This technology induces a drain-current enhancement which depends on the device dimensions. This strong behavior has already been reported in the literature. In this paper, we propose a simple semianalytical physical model to understand the origin of this dependence and to highlight the physical limitations of the stress techniques. With this model, after a calibration, it would be possible to predict the MOSFET performance for a given transistor gate length. This approach is validated by experimental data and explains the reduction of the drain-current enhancement that is observed for ultrasmall gate-length MOSFET.

High gate voltage drain current leveling off and its low-frequency noise in 65 nm fully-depleted strained and non-strained SOI nMOSFETs

For fully-depleted SOI MOSFETs, fabricated in standard and strained 65 nm technologies, it is observed that the drain current I normalized for the device length L and width W levels off at sufficiently high gate voltage overdrives. Also the normalized drain current 1/ f noise spectral density S I shows a plateau value for high front gate voltages. For both strained and non-strained devices there exists a relation between the two plateau values and a y ∼ ( x) 1/4 law is found for the experimental data where x = S I plateau ( L 3 / WN ot ) , y = I plateau ( L/t W), S I plateau and I plateau are the plateau values of S I and I, respectively, and N ot is the density of the oxide traps responsible for the 1/ f noise observed. Compared to standard SOI the use of strained SOI (sSOI) increases the magnitude of the plateau and makes its dependence on the device geometry more pronounced, while the impact of a strained contact etch stop layer (sCESL) is limited. The experimental observations are explained by taking into consideration the field and geometry dependence of the mobility and the influence of negative oxide charges on the drain current.

Performance and Interface Characterization for Contact Etch Stop Layer–Strained nMOSFET with HfO[sub 2] Gate Dielectrics under Pulsed-IV Measurement

In this paper, high-performance contact etching stop layer (CESL)-strained n-metal-oxide-semiconductor field effect transistor (nMOSFET) with HfO 2 gate dielectrics has been successfully demonstrated. The effects of the CESL layer to the high-k without trapping behaviors are investigated by the pulse current-voltage (IV) technique for the first time. It is found that a roughly 55 and 60% increase of mobility and I ON , respectively, can be achieved for the 300 nm CESL HfO 2 nMOSFET using pulsed-IV measurement. Furthermore, a superior HfO 2 /Si interface for CESL devices is observed, demonstrated by an obvious interface state density reduction (6 × 10 11 -9 X 10 10 cm -2 ).

PMOS Hole Mobility Enhancement Through SiGe Conductive Channel and Highly Compressive ILD- $\hbox{SiN}_{x}$ Stressing Layer

In this letter, the SiGe-channel PMOS transistors integrated with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiNx stressing layer have been successfully fabricated. The performance improvements of devices with a gate length (Lg )of down to 40 nm were studied. For long-channel SiGe-channel PMOS, the mobility is at least 50% higher than that of the conventional bulk-Si PMOS. Moreover, compared to the conventional short-channel SiGe-channel devices, the highly compressive CESL stressor shows 32% current gain for Lg = 40 nm PMOS with the thinnest 9 A Si-cap. Therefore, integrating the stressed CESL technique into the SiGe-channel structure is an efficient method for improving PMOS device performance.

N-Channel (110)-Sidewall Strained FinFETs With Silicon–Carbon Source and Drain Stressors and Tensile Capping Layer

The performance of n-channel (110)-sidewall trigate fin-shaped field-effect transistors (FinFETs) is seriously compromised as (110) surfaces have significantly lower electron mobility than (100) surfaces. Straining the channel in (110)-sidewall FinFETs using lattice-mismatched silicon-carbon (Si1-yCy) stressors alone was experimentally determined to be far less effective than doing the same with (100)-sidewall FinFETs. By additionally incorporating a tensile silicon nitride contact etch-stop layer, the increase in longitudinal tensile stress and the introduction of vertical compressive stress result in significant further IDsat enhancement, highlighting the importance of the vertical compressive stress component for enhancing (110)-sidewall FinFET performance.

Electrical Performance and Reliability Aspects of Strain Engineered Deep Submicron CMOS Technologies

To keep track with Moore's law, strain engineering based on either a global or a local approach is gaining much interest and has already been successfully implemented for 65 and 45 nm technology nodes. Although the first goal is to improve the drive current by mobility enhancement, other performance parameters such as leakage current, carrier lifetime and low frequency 1/f noise have to be considered. The implementation of stressors also impacts the radiation hardness of the devices. First some general comments are given on strain engineering techniques already used, before discussing more in detail their impact on several electrical device parameters. Attention mainly will be given to illustrate a global approach based on strained Si on strain-relaxed SiGe buffer layers and the use of process-induced stressors such as an embedded SiGe layer and a contact etch stop layer (CESL). Both are gaining strong interest for implementation in a FinFET technology. Some advantages and disadvantages of the different approaches will be outlined.

Stress Hybridization for Multigate Devices Fabricated on Supercritical Strained-SOI (SC-SSOI)

In this letter, we investigate the impact of a hybridized strain technology on the performance of FinFET-based multigate field-effect transistors (MUGFETs). The technology combines the use of supercritical strained-silicon-on-insulator (SC-SSOI) and strained contact etch stop layers (CESLs). We will show that SC-SSOI (top plane orientation ) with tensile CESL (tCESL), when used for MUGFET, leads to higher improvement in electron mobility as compared to standard SOI with tCESL. Therefore, the combination of both mobility boosters is very beneficial for n-channel MOS MUGFET. However, the impact of compressive CESL on p-channel MOS (pMOS) performance is strongly reduced and becomes even negative when used on an SC-SSOI substrate. Local strain relief of the SC-SSOI substrate is mandatory in order to achieve good pMOS device performance.

Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study

This paper presents a study on the effectiveness of strained contact-etch-stop-layer (CESL) technologies in aggressively scaled dense structures. The focus is on nested transistors, which is a technologically very important structure that consists of a chain of gates on one active area. It will be shown that the two main channel stress components introduced by CESL, which are the vertical and parallel stresses, have a different sensitivity toward layout variations, which accordingly leads to different scaling guidelines to obtain a layout-insensitive strained CESL technology. Decreasing the CESL thickness is not enough for technology scaling; also, adapting the spacer dimensions is indispensable to scale a strained CESL technology from one technology node to the next.

The impact of mobility enhanced technology on device performance and reliability for sub-90 nm SOI nMOSFETs

For SOI nMOSFET, the impact of high tensile stress contact etch stop layer (CESL) on device performance and reliability was investigated. In this work, device driving capability can be enhanced with thicker CESL, larger LOD and narrower gate width. With electrical and body potential inspection, serious device’s degradation happened on SOI-MOSFET with narrow gate device because of STI-induced edge current.

Impacts of Notched-Gate Structure on Contact Etch Stop Layer (CESL) Stressed 90-nm nMOSFET

In this letter, mobility improvements by stress contact etch stop layer (CESL) in a strained 90-nm nMOSFET, with and without notched-gate structure, were studied in detail. Compared to the conventional vertical gate, a device with notched gate shows an extra 7% NMOS ION enhancement for the increased stress in the channel region and the less effect of the halo-implanted impurity on channel. Both simulations with TCAD software and measurements confirm that the notched-gate structure efficiently enhances the generation of high tensile stress on the channel region from the CESL and more localized pocket implant

New Negative-Bias-Temperature-Instability Improvement Using Buffer Layer under Highly Compressive Contact Etch Stop Layer for 45-nm-Node Complementary Metal–Oxide–Semiconductor and Beyond

A remarkable 50% drive current enhancement for p-type metal–oxide–semiconductor field-effect-transistors (pMOSFETs) using a highly compressive SiN contact etch stop layer (CESL) has been successfully demonstrated. In this study, we also first proposed that applying a modulated buffer layer prior to the highly compressive CESL could significantly improving negative-bias-temperature-instability (NBTI) and time-dependent-dielectric-breakdown (TDDB) degradation of pMOSFETs using compressive CESL. Without adversely impact the significant drive current enhancement of pMOSFETs, this thin modulated buffer layer can improve the NBTI lifetime of core pMOSFETs by over two orders of magnitude. Instead of the complex and high-costly SiGe refill scheme, this highly compressive CESL layer with a thin modulated buffer layer successfully demonstrates a better candidate for pMOSFETs drive current enhancement of 45-nm-node CMOS and beyond.

Method for Managing the Stress Due to the Strained Nitride Capping Layer in MOS Transistors

Since the 90-nm CMOS technology node, the strained nitride capping layer (i.e., the contact etch stop layer, CESL) is used as a stress-engineering booster that enables transistor improvement. This paper presents a complete mechanical simulation work explaining how the CESL transmits its intrinsic stress to the Si channel. First, it is demonstrated that the CESL stress transmission is the outcome of several CESL parts acting separately (direct effect) or in association (indirect effect) without neglecting the corner effects for small transistors. Then, all the different contributions of these CESL parts on the stress transfer way for long and short channels are explained. Finally, some guidelines are given for a n optimization of the usage of CESL

Extra Bonus on Transistor Optimization with Stress Enhanced Notched-Gate Technology for Sub-90 nm Complementary Metal Oxide Semiconductor Field Effect Transistor

A simple and efficient strain engineering technique for integrating the tensile-stress contact etch stop layer (CESL) process to a notch gate has been reported in detail. The strain engineering technique utilizes slight process modifications to modulate the channel stress and implantation profile for the enhancement of performance without adding any extra process steps. Compared with the conventional vertical-gate complementary metal oxide semiconductor field effect transistor (CMOSFET) with an offset spacer, a device with a notch gate as a self-aligned offset spacer achieves an extra 7% NMOS ION enhancement. The enhancement comes from the larger channel stress induced by the tensile-stress CESL on the notch gate, and is confirmed by technology computer aided design (TCAD) simulation. Moreover, fewer interface defects (Dit) and parasitic capacitances were obtained for the notch-gate samples.

Negligible Effect of Process-Induced Strain on Intrinsic NBTI Behavior

In this letter, we investigate the effects of process-induced strain on negative bias temperature instability (NBTI) by performing a comparative study of devices with and without process-induced strain for poly-Si/SiON gate stacks. Devices with SiGe source/drain with different processing sequences and devices with a combination of SiGe S/D and compressive contact etch stop layer (CESL) were studied and compared to reference devices. We decouple the effect of processing conditions in order to ensure a correct interpretation of the results. In contrast with the previous reports, which did not consider the impact of processing conditions, this letter demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant degradation of intrinsic NBTI behavior is found for devices with a process-induced strain. In addition, we performed an Arrhenius study showing similar activation energies for devices with and without process-induced strain, suggesting similar degradation mechanism. The results indicate that process-induced strain does not create favorable conditions for additional interface state creation

A Novel Strain Method for Enhancement of 90-nm Node and Beyond FUSI-Gated CMOS Performance

A novel strain engineering technique for a fully silicided (FUSI) metal gate called contact etch stop layer (CESL)-enveloped FUSI was developed for the first time. A CESL was deposited prior to the FUSI RTP2 (the second rapid thermal process of FUSI gate formation) to confine the Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Si FUSI. Then, the phase transfer and volume change of the enveloped FUSI after RTP2 induced a tensile stress to enhance I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> . For example, 500 degC RTP2 induced 1-GPa tensile stress on a blanket wafer test and gained 10% improvement in the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> of the n-channel metal-oxide-semiconductor. The mechanisms of the improvement were also nicely supported by transmission-electron-microscope cross-section analysis, X-ray-diffraction spectrum, and simulation confirmation data

Effect of Silicon Thickness on Contact-Etch-Stop-Layer-Induced Silicon/Buried-Oxide Interface Stress for Partially Depleted SOI

In this letter, based on both experimental investigations and simulation confirmation, it was found that a strained contact etch stop layer over the thin silicon layer of a partially depleted silicon-on-insulator (PD-SOI) will induce high stress on the buried-oxide/silicon interface. Additionally, the interface stress increases with decrease of silicon thickness TSI, thus enhancing the current of the MOSFET, e.g., as TSI shrinks from 90 to 50 nm, current enhancement for PD-SOI n-channel MOS increased from 7% to 12% due to the increase of interface stress. The results are expected to be more significant for devices with thinner TSI such as fully depleted silicon-on-insulator and multigate devices

The Geometry Effect of Contact Etch Stop Layer Impact on Device Performance and Reliability for 90-nm SOI nMOSFETs

The thickness effects of a high-tensile-stress contact etch stop layer (HS CESL) and the impact of layout geometry (length of diffusion (LOD) and gate width) on the mobility enhancement of lang100rang/(100) 90-nm silicon-on-insulator (SOI) n-channel MOSFETs (nMOSFETs) were studied in detail. Additionally, the low-frequency characteristics were inspected using low-frequency noise investigation for floating body (FB)-SOI nMOSFETs. Experimental results show that a device with a 1100-Aring HS CESL has worse characteristics and hot-carrier-induced degradations than a device with a 700-Aring; HS CESL due to larger stress-induced defects. The lower plateau of the Lorentzian noise spectrum that was observed from the input-referred voltage noise Svg implies a higher leakage current for devices with a 1100-Aring HS CESL. On the other hand, it was found that devices with narrow gate widths have higher driving capacity for a larger fringing electric field and higher compressive stress in the direction perpendicular to the channel. Because of the more serious impact of compressive stress in a direction parallel to the channel, a device with shorter LOD experiences more serious performance degradation

NBTI Study on PMOS Devices with TiN/HfO2 Gate Stack and Process Induced Strain

We investigate the effect of process induced strain on Negative Bias Temperature Instability (NBTI) for devices with TiN/HfO2 gate stacks. Devices with compressive Contact Etch Stop Layer (CESL), SiGe Source/Drain, and devices with a combination of both SiGe and CESL were studied and compared to reference devices. We decouple the effect of processing conditions in order to assure correct interpretation of the results. Our study demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant degradation of intrinsic NBTI behavior is found for devices with process induced strain. In addition, we performed an Arrhenius study showing that Si-H bonds under strain exhibit similar activation energies as Si-H bonds without strain, indicating that no favorable conditions for interface states generation are created by the strain.

The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90 nm SOI nMOSFETs

The thickness effects of high-tensile-stress contact etch stop layer (HS CESL) and impact of layout geometry (length of diffusion and gate width) on mobility enhancement of 〈100〉/(100) 90 nm SOI nMOSFETs were studied in detail. Additionally, we also inspected the low frequency characteristic with low-frequency noise investigation for FB-SOI nMOSFETs. Experimental results show that devices with 1100 Å HS CESL possess worse characteristics and hot-carrier-induced degradations than devices with 700 Å HS CESL due to serious stress-induced defects happen. The lower plateau of Lorentzian noise spectrum observed from input-referred voltage noise ( S vg) implies higher leakage current for the devices with 1100 Å HS CESL. On the other hand, we found that devices with narrow gate widths possess higher driving capacity because of larger fringing electric fields and higher compressive stress in direction perpendicular to the channel. Owing to the more serious impact of compressive stress in direction parallel to the channel, the device performance was degraded particularly for devices with shorter LOD.