Constant Voltage Stress Research Articles

Lifetime reliability modeling on EMC performance of digital ICs influenced by the environmental and aging constraints: A case study

This paper aims to develop the lifetime reliability model on electromagnetic compatibility (EMC) performance of the Atmel Attiny85 microcontroller integrated circuit (IC) chip samples, depending on the observed variation of the conducted immunity to the electromagnetic interference imposed by the combined influence of various environmental and aging (i.e., thermal and electrical voltage stress) constraints. A constant-stress accelerated degradation tests plan was designed and implemented by applying different constant thermal (i.e., 70 and 110 °C) and electrical voltage (i.e., 4 and 5 V) stress magnitude levels simultaneously in various multiple stress combinations. Direct power injection (DPI) conducted immunity tests were performed in nominal condition on all the programmed device under test (DUT) samples in both the fresh and aged states at various stress time duration. The best-fit EMC degradation paths were generated using regression analysis, followed by evaluating the pseudo time-to-failure (TTF) data and estimating the unknown parameters of the developed degradation path model. The performance metrics for lifetime reliability were evaluated by combining the Weibull distribution function with the generalized Eyring accelerated life test model. The maximum likelihood estimation method was utilized to estimate the relevant reliability model parameters. The developed reliability model was found to have the capability to estimate the electromagnetic unreliability against the lifetime TTF data of all the selected DUT samples with good precision and acceptable accuracy in both nominal and aging stress conditions. It is demonstrated that the non-failure probability of the DUT samples would remain at 1 for the first 1200 h, and that, under nominal conditions, the prediction of corresponding TTF data for all of those IC samples would fluctuate between 1400 and 1600 h.

Enhancing the Forward Gate Bias Robustness in p‐GaN Gate High‐Electron‐Mobility Transistors through Doping Profile Engineering

This article presents a study on the improvement of the gate robustness and reliability of p‐GaN gate high‐electron‐mobility transistors (HEMTs) by doping profile engineering and by performing a thermal treatment. The reduction of the p‐doping concentration at the Schottky interface using a graded magnesium (Mg) profile in the p‐GaN layer and introducing a top Si‐GaN cap layer is proposed, combined with a high‐temperature anneal step after the gate patterning. The results show that the proposed approach enhances the gate breakdown voltage, reduces the gate leakage current, and increases the time to failure under constant voltage stress, while ensuring stable dynamic behavior and off‐state leakage performance under high‐voltage stress.

Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs.

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO2) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown (QBD) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO2 grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO2 grown on SiC and used to deduce the QBD model of the device under test (DUT). Compared with the QBD obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs.

Dielectric breakdown behavior of ferroelectric HfO2 capacitors by constant voltage stress studied by in situ laser-based photoemission electron microscopy

In situ laser-based photoemission electron microscopy observations with time-dependent dielectric breakdown measurements of TiN/Hf0.5Zr0.5O2(HZO)/TiN ferroelectric capacitors were performed to reveal the dielectric breakdown (DB) mechanism. We succeeded in visualizing the hard DB spots through the top electrode. We found that capacitors with short- and long-lifetime distributions were broken down near and far from the edge of the capacitors, respectively. This indicates that the DB is either topography-dependent or film-quality-dependent. This work demonstrates an effective method of detecting DB in a non-destructive manner to provide an insight for achieving higher endurance HfO2-based ferroelectric capacitors.

Time-dependent dielectric breakdown of SiC-CMOS technology for harsh environments

To estimate the failure time of silicon carbide (SiC) integrated circuits in harsh environments, the activation energy (Ea) and field acceleration factor of SiC n-channel MOS (nMOS) and p-channel MOS (pMOS) were measured using time-dependent dielectric breakdown testing at constant voltage stress in the range of 25–350 °C. Ea around 300 °C was 0.7 eV for nMOS and 0.66 eV for pMOS, which was about twice as high as that below 150 °C and did not differ greatly depending on the conductivity type. The gate dielectric breakdown mechanism shifted from the 1/E model to the E model as the temperature rose, and this is thought to have caused the Ea to change. The field acceleration factor in the E model at 300 °C was 2.7 and 2.3 cm/MV for nMOS and pMOS, respectively. The maximum operating electric fields of nMOS and pMOS for a 100-year lifetime are 6.8 and −7.2 MV/cm, which are over 25% lower than the fields at room temperature, mainly due to a shift in the dominant breakdown model. A more conservative failure time design will be required for SiC-ICs exposed to high temperatures.

On-Chip Modification of Titanium Electrothermal Characteristics by Joule Heating: Application to Terahertz Microbolometer.

This study demonstrates the conversion of metallic titanium (Ti) to titanium oxide just by conducting electrical current through Ti thin film in vacuum and increasing the temperature by Joule heating. This led to the improvement of electrical and thermal properties of a microbolometer. A microbolometer with an integrated Ti thermistor and heater width of 2.7 µm and a length of 50 µm was fabricated for the current study. Constant-voltage stresses were applied to the thermistor wire to observe the effect of the Joule heating on its properties. Thermistor resistance ~14 times the initial resistance was observed owing to the heating. A negative large temperature coefficient of resistance (TCR) of -0.32%/K was also observed owing to the treatment, leading to an improved responsivity of ~4.5 times from devices with untreated Ti thermistors. However, this does not improve the noise equivalent power (NEP), due to the increased flicker noise. Microstructural analyses with transmission electron microscopy (TEM), transmission electron diffraction (TED) and energy dispersive X-ray (EDX) confirm the formation of a titanium oxide (TiOx) semiconducting phase on the Ti phase (~85% purity) deposited initially, further to the heating. Formation of TiOx during annealing could minimize the narrow width effect, which we reported previously in thin metal wires, leading to enhancement of responsivity.

Voltage ramp stress based lifetime-prediction model of advanced Al-doped HfO[formula omitted] dielectric for 2.5D MIMCAPs

The reliability of an Al-doped HfO2 dielectric used in a high density 2.5D MIMCAP is investigated by constant voltage stress (CVS) and voltage ramp stress (VRS) measurements. The good agreement of the results from the two techniques allows to propose a model for lifetime prediction based on the breakdown characteristics. The extracted activation energy shows a voltage dependence associated with a change in the degradation characteristics of the high-κ material at high fields.

Lubricant‐Infused Polymeric Interfaces: A Stretchable and Anti‐Fouling Surface for Implantable Biomaterials

AbstractDeveloping thin, highly stretchable coatings that inhibit the undesirable adhesion of biological substances on soft and high‐water‐content biomaterial surfaces is an area of significant interest. In this study, a stretchable antifouling coating named lubricant‐infused poly(1,3,5,7‐tetramethyl‐1,3,5,7‐tetravinyl cyclotetrasiloxane) (V4D4) is introduced interface with perfluoropolymer (L‐VIP). The stretchable adhesive‐perfluoropolymer bilayer comprises stretchable adhesive polymer (V4D4) and perfluoropolymer (1H,1H,2H,2H‐perfluorooctyl methacrylate (FOMA)). The bilayer exhibits a strong affinity with the lubricant, imparting exceptional antifouling and slippery properties. L‐VIP coating displays superior fouling resistance against plasma proteins related to foreign body reactions (FBR) and biofilm‐forming bacteria. The coating exhibits impressive elastic limits exceeding 200% strain and exceptional stability under repeated cyclic stretching (> 2000 cycles at 150% strain) while maintaining its antifouling properties. Furthermore, the coating presents dielectric performance under accelerated aging conditions at a temperature of 70° and constant voltage stress of 10 V s−1 for over 50 days. To assess the biocompatibility of the L‐VIP coating, a series of in vitro and in vivo experiments are conducted, confirming its non‐toxicity for biomedical applications. It is expected that the stretchable L‐VIP coating will enhance medical devices’ longevity and help prevent bacterial infections, the formation of biofilms, and the nonspecific adherence of biological substances after implantation.

Degradation and Failure Mechanism of p-GaN Gate E-Mode GaN HEMTs

GaN-based power transistors are becoming pivotal devices for high power and high voltage operation due to their higher breakdown voltage, higher carrier mobility because of two-dimensional electron gas (2-DEG), better thermal resistance, higher frequency switching, and lower on-state resistance (RON) [1]. P-GaN gate E-mode GaN HEMTs have emerged as a center of extensive research to understand their operation and reliability [2]. However, one of the reasons the E-mode GaN HEMTs are not yet successfully utilized to their maximum potential is the lack of complete understanding of gate breakdown. Gate degradation of p-GaN gate E-mode GaN HEMT is less understood because of the complexities involving the operating conditions and variables such as gate length, the acceptor doping concentration in the p-GaN layer [3], p-GaN gate thickness, and design of the device [4-5]. To outline a consistent degradation mechanism, this work aims to present an electro-physical model of gate breakdown in p-GaN gate E-mode HEMTs.Lateral E-mode GaN HEMT devices with p-GaN gate configuration are used for this study. According to the Scanning Transmission Electron Microscopy (STEM) imaging of a new device, the AlGaN barrier is 10 nm thick, and the p-GaN cap is 65 nm. The gate-source and gate-drain lengths are 0.5 micrometer and 2.5 micrometer, respectively. The gate length defined by the p-GaN layer is 0.5 micrometer and the edges of the gate metal are pulled in from the top edge of the p-GaN layer by 40 nm. A 0.7 micrometer-long, source-connected field plate is over the p-GaN gate. The p-GaN gate is subjected to static stress to induce accelerated breakdown. Devices were stressed with HP 4155 Semiconductor Analyzer. The electrical measurements were performed with the source, drain, and substrate connected to the ground. FEI 200 Nova was used for Scanning Electron Microscopy (SEM) imaging and Focused Ion-Beam (FIB) milling. ARM JEM-200F with a Cs corrector was used for STEM.Our results show that time-to-fail is highly dependent on device operating conditions. We found no correlation between time-to-fail and initial gate current (IG0). Instead, a higher impact of temperature was found on the gate current of the device (IG) and time-to-fail at 100 °C. Gate failure at constant voltage stress was a single-stage failure. Under constant current stress, on the other hand, the gate shows a multi-stage failure. The breakdown mechanism depends on the impact of static stress on the gate degradation, starting with increased gate current leading to Schottky barrier leakage and finally to catastrophic contact failure. Our study shows that the metal/p-GaN interface at the gate finger becomes the weakest part of the gate stack, likely to be the initiation point of degradation. Metal/p-GaN interface and surface defects develop as percolation paths acting as leakage sources, and nano-cracks have been observed in the gate cap. FA also shows physical degradation at the metal/p-GaN cap due to electrical stress. Observed physical damage in the gate region is correlated to the gate leakage characteristics to develop an electro-physical failure model for gate breakdown in p-GaN gate E-mode GaN HEMTs.

Modified buck converter with constant voltage stress using a CDD circuit

Modified buck converter with constant voltage stress using a CDD circuit

Degradation and Failure Mechanism of p-GaN Gate E-Mode GaN HEMTs

This work describes the cause-effect-based degradation process of the p-GaN gate in Enhancement-mode (E-mode) GaN High Electron Mobility Transistors (HEMTs) using gate stressing and failure analysis (FA). We found no correlation between time-to-fail and initial gate current (IG0). Instead, a higher impact of temperature was found on the gate current of the device (IG) and time-to-fail at 100 °C. Gate failure at constant voltage stress was a single-stage failure. Under constant current stress, the gate shows a multi-stage failure. The breakdown starts with increased gate current leading to Schottky barrier leakage and finally to catastrophic contact failure. The metal/p-GaN interface at the gate finger becomes the weakest part of the gate stack. Metal/p-GaN interface and surface defects develop as percolation paths acting as leakage sources, and nano-cracks have been observed in the gate cap. FA also shows physical degradation at the metal/p-GaN cap due to electrical stress.

ALD deposited bipolar HfOx films for silicon surface passivation

Hafnium oxide thin films consist of trap states which can degrade or enhance the device performance depending upon the application. These trap states play a crucial role in silicon surface passivation when using HfOx films. This paper investigates the dependence of crucial surface passivation parameters on different film growth components of thermal ALD process. Our study is focused on understanding different oxide charges present at the HfOx/Si interface using capacitance-voltage and constant voltage stress studies; particularly trap states introduced during thermal atomic layer deposition process. This study is performed for different film growth conditions to understand the origin of traps states. We show that the interfacial layer (IL) grows during the film deposition and therefore two interfaces are formed, i.e., HfOx/SiOx and SiOx/Si. Acting as the tunnelling oxide, this interlayer consists of trap states which are intrinsic in origin. The investigation on MOS structures fabricated using n and p type silicon substrates gives an understanding towards amphoteric nature of the trap states. Their nature (acceptor/donor) depends on the substrate doping type (n-Si/p-Si) giving it bipolar characteristic. However, the interaction of such trap states with the majority carrier band edge of the substrate strongly depends on the IL thickness. Additionally, the trap charge density increases with metal pulsing duration, suggesting that the metal precursor may be the source of these trap charges rather than the oxidant. By shedding light on the nature and behaviour of trap states in HfOx films, our study contributes to a deeper understanding of their impact on device performance. This knowledge can aid in optimizing surface passivation strategies and improving the overall performance of HfOx-based devices in various applications.

Comprehensive Investigation of Constant Voltage Stress Time-Dependent Breakdown and Cycle-to-Breakdown Reliability in Y-Doped and Si-Doped HfO2 Metal-Ferroelectric-Metal Memory.

In this study, we comprehensively investigate the constant voltage stress (CVS) time-dependent breakdown and cycle-to-breakdown while considering metal-ferroelectric-metal (MFM) memory, which has distinct domain sizes induced by different doping species, i.e., Yttrium (Y) (Sample A) and Silicon (Si) (Sample B). Firstly, Y-doped and Si-doped HfO2 MFM devices exhibit domain sizes of 5.64 nm and 12.47 nm, respectively. Secondly, Si-doped HfO2 MFM devices (Sample B) have better CVS time-dependent breakdown and cycle-to-breakdown stability than Y-doped HfO2 MFM devices (Sample A). Therefore, a larger domain size showing higher extrapolated voltage under CVS time-dependent breakdown and cycle-to-breakdown evaluations was observed, indicating that the domain size crucially impacts the stability of MFM memory.

SPICE Simulation of Quantum Transport in Al2O3/HfO2-Based Antifuse Memory Cells

This letter reports a compact SPICE model for the electron transport characteristics of Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based nanolaminates for their use in multilevel one-time programmable (M-OTP) memories. The model comprises three simulation blocks corresponding to the electrical stimulus applied to the device, the equivalent circuit of the memory cell, and the events generator associated with the dielectric breakdown of the insulating layer. For a clear assessment of the quantum effects occurring in these structures, constant voltage stress was used as the primary electrical stimulus. The antifuse (AF) cell is represented by a combination of series and parallel resistances that account for the formation of filamentary conducting paths with quantum properties across the structure. The arrival of successive breakdown events is simulated using a power-law nonhomogeneous Poisson process. Our study indicates that a M-OTP memory device operating in the quantum regime not only is feasible but also that its stochastic features are addressable by circuit simulations.

Impact of Charge-Trapping Effects on Reliability Instability in AlxGa1-xN/GaN High-Electron-Mobility Transistors with Various Al Compositions.

In this study, we present a detailed analysis of trapping characteristics at the AlxGa1-xN/GaN interface of AlxGa1-xN/GaN high-electron-mobility transistors (HEMTs) with reliability assessments, demonstrating how the composition of the Al in the AlxGa1-xN barrier impacts the performance of the device. Reliability instability assessment in two different AlxGa1-xN/GaN HEMTs [x = 0.25, 0.45] using a single-pulse ID-VD characterization technique revealed higher drain-current degradation (∆ID) with pulse time for Al0.45Ga0.55N/GaN devices which correlates to the fast-transient charge-trapping in the defect sites near the interface of AlxGa1-xN/GaN. Constant voltage stress (CVS) measurement was used to analyze the charge-trapping phenomena of the channel carriers for long-term reliability testing. Al0.45Ga0.55N/GaN devices exhibited higher-threshold voltage shifting (∆VT) caused by stress electric fields, verifying the interfacial deterioration phenomenon. Defect sites near the interface of the AlGaN barrier responded to the stress electric fields and captured channel electrons-resulting in these charging effects that could be partially reversed using recovery voltages. The quantitative extraction of volume trap density (Nt) using 1/f low-frequency noise characterizations unveiled a 40% reduced Nt for the Al0.25Ga0.75N/GaN device, further verifying the higher trapping phenomena in the Al0.45Ga0.55N barrier caused by the rougher Al0.45Ga0.55N/GaN interface.

An Investigation of SILC Degradation under Constant Voltage Stress in PDSOI Devices.

The stress-induced leakage current (SILC) degradation of partially depleted silicon in insulator (PDSOI) devices under constant voltage stress (CVS) was studied. Firstly, the behaviors of threshold voltage degradation and SILC degradation of H-gate PDSOI devices under constant voltage stress were studied. It was found that both the threshold voltage degradation and SILC degradation of the device are power functions of the stress time, and the linear behavior between SILC degradation and threshold voltage degradation is good. Secondly, the soft breakdown characteristics of the PDSOI devices were studied under CVS. Thirdly, the effects of different gate stresses and different channel lengths on the threshold voltage degradation and SILC degradation of the device were studied. The results showed SILC degradation of the device under positive CVS and SILC degradation of the device under negative CVS. The shorter the channel length of the device was, the greater the SILC degradation of the device was. Finally, the influence of the floating effect on the SILC degradation of the PDSOI devices was studied, and the experimental results showed that the degree of SILC degradation of the floating device was greater than that of the H-type grid body contact PDSOI device. This showed that the floating body effect can exacerbate the SILC degradation of PDSOI devices.

Experimental investigation of time dependent dielectric breakdown and failure mechanism for Hf0.5Zr0.5O2 ferroelectric field effect transistors

The experimental investigation of the time dependent dielectric breakdown (TDDB) was performed to study the dielectric breakdown mechanisms for Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect transistors (FeFETs) with the SiO2 interfacial layer (IL). Constant voltage stress method combined with the TCAD device simulation was used to study the breakdown mechanism of the TaN/HZO/SiO2/Si gate stack. Due to the much higher electric field in the IL, the breakdown of the SiO2 IL is the major reason for the breakdown of the gate stack. In addition, it is found that the IL breakdown will speed up the disappearance of the memory window (MW), leading to the malfunction of the FeFET as a storage device. Finally, the Weibull distributions of time-to-breakdown (TBD) and charge-to-breakdown (QBD) were characterized, revealing decent TDDB performance of the FeFETs. Careful design of IL thickness is necessary to balance the tradeoff between the device performance and the reliability lifetime of HZO FeFETs.

Investigation of the Gate Degradation Induced by Forward Gate Voltage Stress in p-GaN Gate High Electron Mobility Transistors.

In this work, we investigated the degradation of the p-GaN gate stack induced by the forward gate voltage stress in normally off AlGaN/GaN high electron mobility transistors (HEMTs) with Schottky-type p-GaN gate. The gate stack degradations of p-GaN gate HEMTs were investigated by performing the gate step voltage stress and the gate constant voltage stress measurements. In the gate step voltage stress test, the positive and negative shifts of threshold voltage (VTH) depended on the range of the gate stress voltage (VG.stress) at room temperature. However, the positive shift of VTH in the small gate stress voltage was not observed at 75 and 100 °C and the negative shift of VTH was started from a lower gate voltage at a high temperature compared to room temperature. In the gate constant voltage stress test, the gate leakage current increased with three steps in the off-state current characteristics as the degradation progressed. To investigate the detailed breakdown mechanism, we measured the two terminal currents (IGD and IGS) before and after the stress test. The difference between the gate-source current and the gate-drain current in the reverse gate bias indicated that the increase of the leakage current was attributed to the degradation between the gate and the source while the drain side was not affected.

Ferroelectricity and Oxide Reliability of Stacked Hafnium-Zirconium Oxide Devices.

In this work, we investigate the ferroelectricity of stacked zirconium oxide and hafnium oxide (stacked HfZrO) with different thickness ratios under metal gate stress and simultaneously evaluate the electrical reliability of stacked ferroelectric films. Based on experimental results, we find that the stacked HfZrO films not only exhibited excellent ferroelectricity but also demonstrated a high performance on reliability. The optimized condition of the 45% Zr proportion exhibited a robust ferroelectric polarization value of 32.57 μC/cm2, and a polarization current with a peak value of 159.98 μA. Besides this, the ferroelectric stacked HfZrO also demonstrated good reliability with a ten-year lifetime under >-2 V constant voltage stress. Therefore, the appropriate modulation of zirconium proportion in stacked HfZrO showed great promise for integrating in high-performance ferroelectric memory.

Effects of constant voltage stress on bipolar degradation in 4H-SiC IGBT

The analysis of bipolar degradation in 18 kV SiC IGBT with constant voltage stress was studied. Its fabrication process as well as testing conditions of IGBT device structure were described. The output characteristics were used for analysis in testing of the degraded devices. In addition, it was revealed that the device with no defects on the surface of the epitaxial layer suffers from unexpected degradation under low voltage stress, while the device with poor performance was completely degraded under high voltage stress. The research results will be a good guidance for controlling defects of high-voltage devices in the process of substrate, epitaxy and chip fabrication.