Constant Current Stress Tests Research Articles

Bias-dependent degradation of single quantum well on InGaN-based light emitting diode

This paper investigates the factors that influence the efficiency and the reliability of InGaN-based light emitting diodes. The devices under test have a single InGaN quantum well, with a nominal emission wavelength of 495 nm. From the preliminary characterization, the L-I curve shows an anomalous slope mainly due to: i) high Shockley Read Hall recombination rate, and ii) low electron densities in the explored range of injection, as also confirmed by simulation. The reliability of the devices was investigated by performing a constant current stress test at J = 80 A/cm2 at room temperature. Optical degradation occurs with different trends, depending on the injection regime. For low injection levels, the optical power decay is monotonic. In the high injection range, for I > 10 mA, we can recognize different degradation phases. The optical degradation can be ascribed to the generation and relocation of defects in the active region, as also confirmed by DLOS measurement. The origin of degradation was also investigated by a stress test with photoluminescence measurement. The results suggest that the variation of the optical characteristics can be related to the variation of the intrinsic characteristics of the material.

Degradation of AlGaN-based UV-C SQW LEDs analyzed by means of capacitance deep-level transient spectroscopy and numerical simulations

The lifetime of deep-ultraviolet light-emitting diodes (LEDs) is still limited by a number of factors, which are mainly related to semiconductor defects, and still need to be clarified. This paper improves the understanding of UV LED degradation, by presenting an analysis based on combined deep-level transient spectroscopy (C-DLTS), electro-optical characterization, and simulations, carried out before and during a constant current stress test. The original results of this paper are (i) C-DLTS measurements allowed us to identify three traps, two associated with Mg-related defects, also detected in the unaged device, and one related to point defects that were generated by the ageing procedure. (ii) Based on these results and on TCAD simulations, we explain the variation in the forward I–V by the degradation of the p-contact, due to Mg passivation. (iii) On the other hand, optical degradation is ascribed to an increase in defectiveness of the active region and surrounding areas, which led to a decrease in injection efficiency, to an increase in non-radiative recombination, and to an increase in trap-assisted tunneling processes.

Impact of Generation and Relocation of Defects on Optical Degradation of Multi-Quantum-Well InGaN/GaN-Based Light-Emitting Diode.

The defectiveness of InGaN-based quantum wells increases with low indium contents, due to the compressive strain induced by the lattice mismatch between the InGaN and GaN layers, and to the stronger incorporation of defects favored by the presence of indium. Such defects can limit the performance and the reliability of LEDs, since they can act as non-radiative recombination centers, and favor the degradation of neighboring semiconductor layers. To investigate the location of the layers mostly subjected to degradation, we designed a color-coded structure with two quantum wells having different indium contents. By leveraging on numerical simulations, we explained the experimental results in respect of the ratio between the emissions of the two main peaks as a function of current. In addition, to evaluate the mechanisms that limit the reliability of this type of LED, we performed a constant-current stress test at high temperature, during which we monitored the variation in the optical characteristics induced by degradation. By comparing experimental and simulated results, we found that degradation can be ascribed to an increment of traps in the active region. This process occurs in two different phases, with different rates for the two quantum wells. The first phase mainly occurs in the quantum well closer to the p-contact, due to an increment of defectiveness. Degradation follows an exponential trend, and saturates during the second phase, while the quantum well close to the n-side is still degrading, supporting the hypothesis of the presence of a diffusive front that is moving from the p-side towards the n-side. The stronger degradation could be related to a lowering of the injection efficiency, or an increment of SRH recombination driven by a recombination-enhanced defect generation process.

Fluorine Effects Originating From the CVD-W Process on Charge-Trap Flash Memory Cells

The fluorine (F) effect originating from the chemical vapor deposited (CVD) tungsten (W) process on charge-trap flash memory devices was systematically investigated, and the CVD-W memory was compared with physical vapor deposited (PVD) W memory. The residual F in the CVD-W diffused into Al2O3 and Si3N4 layers, generating shallow charge-trapping sites in each layer. These generated charge-trapping sites were considered to be responsible for the fast-erase and poor-retention characteristics at room temperature in the CVD-W compared to the related characteristics in the PVD-W memory. The generation of charge-trapping sites caused by the residual F in each layer was also supported by the trap density calculation in the Si3N4 and constant current stress test for the Al2O3 layer.

Degradation Mechanisms of Heterogeneous III-V/Silicon 1.55- $\mu \text{m}$ DBR Laser Diodes

This paper reports an extensive analysis of the degradation processes of heterogeneous III-V/Silicon infrared laser diodes designed for integrated telecommunications and interconnects. By submitting the devices to a series of constant current stress tests, a gradual degradation of the main device parameters was observed. In particular, in every stress scenario the devices under test showed: 1) an increase in the threshold current; 2) a decrease of the turn-ON voltage; and 3) an increase in the apparent carrier concentration within the space charge region. The variation of the electrical parameters (turn-ON voltage and apparent charge concentration) was found to be significantly correlated to the optical degradation for long stress times; the results support the hypothesis that degradation originates from an increase in the non-radiative recombination rate, possibly due to the diffusion of defects toward the active region of the devices. In order to investigate the physical origin of those defects, a capacitance deep level transient spectroscopy analysis was performed. The results indicate the presence of five different deep levels, with a main trap located around 0.43 eV above the valence band energy. This trap is compatible with an interface defect located between the In 0.53 Al x Ga 0.47-x As separate confinement heterostructure region and the InP layer.

Lowering the effective work function via oxygen vacancy formation on the GeO2/Ge interface

The use of a GeO2 interfacial layer (IL) between a high-k dielectric and a Ge substrate helps to reduce the interface state density in Ge MOS devices. We report that the presence of the GeO2 IL changes the effective work function (eWF) of the gate stack when annealed after high-k dielectric deposition. The eWF is reduced from 4.31eV to 3.98eV for TaN and from 5.00eV to 4.44eV for Ni. Consequently, the threshold voltage (Vth) decreases from 0.69V to 0.21V for Ni after post deposition annealing. Our investigation confirms that the generation of oxygen vacancies in the GeO2 IL near the Ge substrate is the main cause of the eWF modulation. In addition, the reliability of the GeO2 IL is investigated via the conductance method and a constant-current stress test.

A study of trap-limited conduction influenced by plasma damage on the source/drain regions of amorphous InGaZnO TFTs

This study investigated electrical characteristics and stability variations of amorphous indium gallium zinc oxide thin film transistors (a-IGZO TFTs) with plasma damage on their source/drain (S/D) regions. The influence of the plasma damage on the TFT performance is absent as the channel length is 36–100 μm. When the channel length is decreased to 3–5 μm, the mobility () of the bottom gate TFT (BG TFT) with plasma damage is significantly degraded to 0.6 cm2 (V s)−1, which is much lower than 4.3 cm2 (V s)−1 of a damage-free BG TFT. We utilized the TFT passivation layer and the indium tin oxide (ITO), which was used as the pixel electrode material in the TFT backplane, to be the top gate insulator and top gate electrode of the defective BG TFT to obtain the defective dual-gate TFT. The mobility can be restored to 5.1 cm2 (V s)−1. Additional process steps are not required. Besides, this method is easily implemented and is fully compatible with TFT backplane fabrication process. The transfer curves, hysteresis characteristics, stabilities under constant voltage stress and constant current stress tests were measured to give evidences that the traps created by the plasma damage on the S/D regions indeed can affect electron transport. This trap-limited conduction can be improved by using the top gate. It was proven that the top gate was not for contributing an observably additional current. It was for inducing electrons to electrically passivate the plasma-induced defects near the back channel. Thus, the trapping/detrapping of the electrons transporting in the front channel can be reduced. The trap density near the Fermi level, hopping distance and hopping energy are 1.1 × 1018 cm−3 eV−1, 162 Å, and 52 meV for the BG TFT with plasma damage on the S/D regions.

Examination of the ambient effects on the stability of amorphous indium-gallium-zinc oxide thin film transistors using a laser-glass-sealing technology

The effect of an ambient atmosphere with a positive bias constant current stress (CCS) and a negative bias illumination stress (NBIS) on the stability of amorphous In-Ga-Zn-O thin film transistors (TFTs) is examined by utilizing a glass-hermetic-sealant with a moisture permeability of less than 10−6 g/m2 · day. In the CCS test, the threshold voltage shift (ΔVth) was remarkably suppressed in the glass-sealed TFTs. The unsealed and resin-sealed TFTs exhibited large ΔVth values. During the NBIS tests, the glass-sealed TFTs had almost the same negative ΔVth as the unsealed and resin sealed TFTs. Among the different TFTs, no significant differences were observed in the threshold voltage, the subthreshold swing and the saturation mobility as a function of the photon energy. It is concluded that ambient molecules were the primary origin of the instability of the ΔVth, induced by a CCS, but they were not related to the NBIS instability. The major role of the effective passivation layers in the NBIS test was not to simply block out the ambient effects, but to reduce the extra density of states at/near the surface of the back channel.

Effect of Oxygen Binding Energy on the Stability of Indium-Gallium-Zinc-Oxide Thin-Film Transistors

From a practical viewpoint, the topic of electrical stability in oxide thin-film transistors (TFTs) has attracted strong interest from researchers. Positive bias stress and constant current stress tests on indium-gallium-zinc-oxide (IGZO)-TFTs have revealed that an IGZO-TFT with a larger Ga portion has stronger stability, which is closely related with the strong binding of O atoms, as determined from an X-ray photoelectron spectroscopy analysis.

Reduction of charge trapping in HfO2 film on a Ge substrate by trimethylaluminum pretreatment

AbstractTrimethylaluminum pretreatment prior to HfO2 deposition is introduced for native oxide reduction. It is identified that the trimethylaluminum pretreatment could effectively reduce native oxide, which is transformed to an aluminum oxide interfacial layer. Formation of the thin aluminum oxide layer suppresses Ge diffusion into HfO2, reducing hysteresis in the ca‐ pacitance–voltage curve. Moreover, the device reliability of the trimethylaluminum pretreated sample is improved in a constant current stress test. This work indicates that trimethylaluminum pretreatment is an effective in‐situ method for the gate dielectric stack formation to reduce charge trapping in the HfO2 film on a Ge substrate. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Comparison of the Reliability of Thin $\hbox{Al}_{2} \hbox{O}_{3}$ Gate Dielectrics Prepared by In Situ Oxidation of Sputtered Aluminum in Oxygen Ambient With and Without Nitric Acid Compensation

The electrical characteristics and reliability of the aluminum oxide (Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) metal-oxide-semiconductor (MOS) capacitors were investigated under low-temperature process consideration. The simple cost-effective technique in preparing the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> bilayer structure as the high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> gate dielectrics was demonstrated in this paper. SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> was prepared by room-temperature anodic oxidation, and Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> was fabricated by room-temperature in situ natural oxidation during the dc sputtering of aluminum in Ar/O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ambient. Compared to the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> MOS capacitors without nitric acid (HNO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) compensation, significant improvements in electrical characteristics, reliability, and uniformity were achieved by utilizing HNO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> to moderately oxidize the existing Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> layer. In addition, the charge trapping behaviors of our samples were also studied by time-dependent dielectric breakdown under the 1000-s constant voltage stress and constant current stress tests. It was found that the electron trapping is dominant under a low negative bias stress. However, under a high negative bias stress, the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> MOS capacitors show hole trapping due to the impact ionization near the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interface. The in situ oxidation in sputtering with HNO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> compensation is suitable for future low-temperature dielectric applications.

Comprehensive Modeling of Threshold Voltage Variability Induced by Plasma Damage in Advanced Metal–Oxide–Semiconductor Field-Effect Transistors

Threshold voltage shift (ΔVth) and its variation induced by plasma processing were investigated in detail. Two damage mechanisms occurring in an inductively coupled plasma reactor were focused on in this study; the charging damage induced by the conduction current from plasma and the physical damage attributed to the bombardment of high-energy ions. Regarding the charging damage, ΔVth was found to show a power-law dependence on antenna ratio for both SiO2 and high-k gate dielectrics in metal–oxide–semiconductor field-effect transistors (MOSFETs). The observed dependence was also confirmed from the results of a constant-current stress test, indicating that the plasma plays the role of the current source in terms of the charging damage. As for the physical damage, the recess structure in source/drain extension regions was focused on as a possible cause of ΔVth. The depth of the recess (dR) formed by the physical damage was studied using Si wafers exposed to various plasma conditions and subsequently analyzed for surface damage. The recess depth determined from the experiments and classical molecular dynamics simulations exhibits a power-law dependence on potential drop across the sheath between the plasma and the device surface (Vp-Vdc), which is used as a practical measure of the damage. On the basis of the above results, ΔVth due to the physical damage was calculated by technology computer-aided design (TCAD) device simulation for n- and p-channel MOSFETs with the recess structure. ΔVth shows a linear dependence on recess depth for both n- and p-channel MOSFETs, resulting in the power-law dependence on (Vp-Vdc) via dR. These findings provide a simple relationship among the variations of ΔVth, antenna ratio, and plasma parameters. By taking into account the findings that the MOSFET with high-k dielectrics shows a larger ΔVth due to the charging than that with SiO2, and that the MOSFETs with a smaller gate length indicate a larger ΔVth due to the Si recess structure, we can conclude that larger amount of plasma damage induces the larger ΔVth variations, i.e., the Vth variability induced by the plasma damage is difficult to suppress and will become crucial to the fabrication of future advanced devices. The proposed relationship is useful as a guideline to suppress the ΔVth variations caused by plasma damage.

Effects of Interfacial Dielectric Layers on the Electrical Performance of Top-Gate In-Ga-Zn-Oxide Thin-Film Transistors

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top-gate In-Ga-Znoxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below 200°C, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as Si3N4 and Al2O3, the electrical properties are analyzed. After post-annealing at 200°C for 1 hour in an O2 ambient, the sub-threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative-bias stress tests on TFTs with a Si3N4 IDL, the degradation sources are closely related to unstable bond states, such as Si-based broken bonds and hydrogenbased bonds. From constant-current stress tests of Id = 3 µA, an IGZO-TFT with heat-treated Si3N4 IDL shows a good stability performance, which is attributed to the compensation effect of the original charge-injection and electron-trapping behavior.

Comparative Study of Plasma Source-Dependent Charging Polarity in Metal–Oxide–Semiconductor Field Effect Transistors with High-k and SiO2 Gate Dielectrics

The polarities of charging damage in n- and p-channel metal–oxide–semiconductor field effect transistors (MOSFETs) with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar- and Cl-based gas mixtures) and found to depend on plasma conditions, in contrast to those with conventional SiO2. It was also found that high-k devices were more susceptible to plasma charging damage than SiO2 devices. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-channel MOSFETs with high-k gate stacks suffer from negative charge trapping, whereas for Cl-plasma confirmed to induce less damage, both n- and p-channel MOSFETs with high-k gate stacks suffer from positive charge trapping. The above-mentioned plasma-source-dependent charging damage was also compared on the basis of the results obtained by the plasma diagnostics. From the results of constant-current stress tests, the unique charging polarity observed for the high-k gate stack was attributed to the characteristic hole and electron trapping phenomena, in accordance with the injected stress current and stress time, implying the necessity of taking the intrinsic charge trapping process into consideration for accurate evaluations of charging damage on high-k gate dielectrics.

Reactive ion etching induced damage to SiO2 and SiO2–Si interfaces in polycrystalline Si overetch

The effects of reactive ion etching on the properties of SiO2 and SiO2–Si interfaces have been examined for the case of polycrystalline Si overetch exposures. HBr/Cl2-based polycrystalline Si etch chemistry was used and damage effects for thermally grown oxides with various thicknesses were determined as a function of the overetch exposure times. A large amount of charge was found from capacitance–voltage measurements to be created in the plasma exposed oxides. This charge density increased with increasing overetch time and decreasing initial oxide thickness. Ramp voltage and constant current stress tests were both used to determine the dielectric strength and long-term reliability of these same plasma exposed oxides. A very significant degradation of charge to breakdown was found for the plasma exposed oxides as compared to unexposed control oxides.

After-breakdown conduction through ultrathin SiO 2 films in metal/insulator/semiconductor structures

The dielectric breakdown of ultrathin SiO 2 films has been studied by subjecting chromium-gated metal/oxide/semiconductor structures to wear-out tests. While in constant-current stress tests only one breakdown is observed as a sudden voltage drop, in constant-voltage stress experiments, several breakdown events can be registered as abrupt current increments. No experimental evidence for the occurence of important thermal effects has been found, and the breakdown has been interpreted as a reversible switching between two oxide conduction states of very different conductivities. During our constant-voltage tests, breakdown and “anti-breakdown” events were observed as abrupt changes between well defined current levels which correspond to the presence of a variable number of breakdown spots. The “effective” number of breakdown spots increases with the time of stress, as has been demonstrated by the evolution of the after-breakdown current-voltage characteristic. All these results are understood if one considers that the breakdown is a purely electronic phenomenon related to the degradation of the insulator network. Assuming that the main effect of the degradation of the SiO 2 microscopic structure is the generation of deep electron traps near the injecting interface, trap-assisted resonant tunnelling seems to be a reasonable hypothesis for the breakdown triggering mechanism. Nevertheless, the actual nature of this conduction mechanism is still an open question.

The phenomenology of dielectric breakdown in thin silicon dioxide films: Al cathodes and p-type Si anodes

Various aspects of the phenomenology of dielectric breakdown in Al-SiO2-p-Si metal-oxide-semiconductor planar capacitor structures have been investigated.The different types of breakdown events and their distributions are discussed in light of breakdown data from constant current stress tests and linearly ramped voltage tests with variable ramp rates. Many tests were performed on a wide variety of samples using Weibull-type distribution functions in analyzing the data. Of special interest was the influence of substrate parameters, such as oxygen concentration, surface transition-metal contamination, surface roughness, and the relatively simple surface defects which can form during a single oxidation treatment. Using very careful methods, three general types or ‘‘modes’’ of breakdown distribution are observed, a mode being defined as a subset of the complete distribution exhibiting the same or similar time and field parameters in the Weibull distribution. Two of the distinct modes are related to distributed ‘‘weak spots.’’ The third is apparently ‘‘intrinsic.’’ Implications for device reliability are considered. The origin and elimination of the distributed weak spot modes is discussed as are details of the intrinsic mode.