Constant-coefficient Multipliers Research Articles

Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs

Multipliers are used in virtually all Digital Signal Processing (DSP) applications such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is needed, as in 4K video processing, or where hardware resources are limited, as in mobile and IoT devices. We propose a novel, low-cost, low energy, and high-speed approximate constant coefficient multiplier (CCM) using a hybrid binary-unary encoding method. The proposed method implements a CCM using simple routing networks with no logic gates in the unary domain, which results in more efficient multipliers compared to Xilinx LogiCORE IP CCMs and table-based KCM CCMs (Flopoco) on average. We evaluate the proposed multipliers on 2-D discrete cosine transform algorithm as a common DSP module. Post-routing FPGA results show that the proposed multipliers can improve the {area, area × delay, power consumption, and energy-delay product} of a 2-D discrete cosine transform on average by {30%, 33%, 30%, 31%}. Moreover, the throughput of the proposed 2-D discrete cosine transform is on average 5% more than that of the binary architecture implemented using table-based KCM CCMs. We will show that our method has fewer routability issues compared to binary implementations when implementing a DCT core.

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers

Low-precision arithmetic operations to accelerate deep-learning applications on field-programmable gate arrays (FPGAs) have been studied extensively, because they offer the potential to save silicon area or increase throughput. However, these benefits come at the cost of a decrease in accuracy. In this article, we demonstrate that reconfigurable constant coefficient multipliers (RCCMs) offer a better alternative for saving the silicon area than utilizing low-precision arithmetic. RCCMs multiply input values by a restricted choice of coefficients using only adders, subtractors, bit shifts, and multiplexers (MUXes), meaning that they can be heavily optimized for FPGAs. We propose a family of RCCMs tailored to FPGA logic elements to ensure their efficient utilization. To minimize information loss from quantization, we then develop novel training techniques that map the possible coefficient representations of the RCCMs to neural network weight parameter distributions. This enables the usage of the RCCMs in hardware, while maintaining high accuracy. We demonstrate the benefits of these techniques using AlexNet, ResNet-18, and ResNet-50 networks. The resulting implementations achieve up to 50% resource savings over traditional 8-bit quantized networks, translating to significant speedups and power savings. Our RCCM with the lowest resource requirements exceeds 6-bit fixed point accuracy, while all other implementations with RCCMs achieve at least similar accuracy to an 8-bit uniformly quantized design, while achieving significant resource savings.

FPGA Based Optimized Reconfigurable Base-2 Constant Coefficient Multiplier Architecture for Image Filtering

Image convolution using FPGA has been comprehensively used for noise removal of Reconfigurable computing based image Processing Algorithm. Particularly these filters are widely used in embedded computer vision applications like edge detection and Feature extraction analysis. Practical implementation of filter requires enormous computational requirement. The multiplier plays very important role in the image convolution. The existed multiplier design requires more computational complexity for the 3x3 test image. For this the proposed reconfigurable constant coefficient multiplier uses base-2 Common sub expression algorithm. which reduces the computational complexity in a better way. The proposed 2D-convolution in image application is the value of resultant output is multiplication of image pixel with corresponding kernel value. In this work the realization of 2D convolution to be done using proposed constant coefficient multiplier and analyzed using Xilinx Virtex-5 FPGA platform

Design and FPGA implementation of lattice wave fractional order digital differentiator

This paper deals with the design and FPGA implementation of a fractional order digital differentiator. It is realized using computationally efficient lattice wave digital filter (LWDF) which requires minimum multipliers in comparison to the direct form structure. A nature inspired ant lion optimization (ALO) algorithm is utilized to compute optimal coefficients of the LWDF based digital differentiator. The proposed LWDF based digital differentiator is compared with the existing literature in terms of magnitude response, percentage magnitude error and root mean square magnitude error. LWDF structure comprises of constant coefficient multipliers, adders and delay units which are implemented on FPGA with the help of Xilinx system generator for DSP design tool. For efficient implementation of multipliers, multiplier-less logic through digit recoding techniques such as canonic signed digit (CSD) representation and radix-2r encoding are described through Verilog HDL and incorporated in the implementation model as black box. Post-implementation results show that implementation based on the radix-2r encoding is found to be more efficient than that of the CSD encoding. The design and implementation results are also reported to highlight the improvements.

Algorithms for Multiplierless Multiple Constant Multiplication in Online Arithmetic

Online arithmetic operators offer advantages of reduction in resource utilization and interconnection complexity besides providing pipelining at digit level. Multiplierless constant coefficient multiplication using the shift-and-add technique is widely used in digital signal processing applications. This paper proposes a novel bit serial adaptation of the parallel shift-and-add algorithm to online arithmetic. The proposed multipliers use right shifts instead of the traditional left shifts resulting in causal online implementations. Graph-based and hybrid algorithms are developed for the estimation of the distance of a constant from a set of constants in terms of the number of additions and for the synthesis of online multiple constant multipliers under area and online delay constraints. The computational complexity of the algorithms is determined. Results of implementation on randomly generated constant sets and FIR filter instances show substantial improvements in the number of operations required using the distance heuristic. Further, it is shown that the proposed techniques and algorithms result in significant savings in resource utilization, logic depth, and clock frequency compared to parallel and digit-serial algorithms.

Optimal Single Constant Multiplication Using Ternary Adders

The single constant coefficient multiplication is a frequently used operation in many numeric algorithms. Extensive previous work is available on how to reduce constant multiplications to additions, subtractions, and bit shifts. However, on previous work, only common two-input adders were used. As modern field-programmable gate arrays (FPGAs) support efficient ternary adders, i.e., adders with three inputs, this brief investigates constant multiplications that are built from ternary adders in an optimal way. The results show that the multiplication with any constant up to 22 bits can be realized by only three ternary adders. Average adder reductions of more than 33% compared to optimal constant multiplication circuits using two-input adders are achieved for coefficient word sizes of more than five bits. Synthesis experiments show FPGA average slice reductions in the order of 25% and a similar or higher speed than their two-input adder counterparts.

Reduced-Area Constant-Coefficient and Multiple-Constant Multipliers for Xilinx FPGAs with 6-Input LUTs

Multiplication by a constant is a common operation for many signal, image, and video processing applications that are implemented in field-programmable gate arrays (FPGAs). Constant-coefficient multipliers (KCMs) are often implemented in the logic fabric using lookup tables (LUTs), reserving embedded hard multipliers for general-purpose multiplication. This paper describes a two-operand addition circuit from previous work and shows how it can be used to generate and add pre-computed partial products to implement KCMs. A novel method for pre-computing partial products for KCMs with a negative constant is also presented. These KCMs are then extended to have two to eight coefficients that may be selected by a control signal at runtime to implement time-multiplexed multiple-constant multiplication. Synthesis results show that proposed pipelined KCMs use 27.4% fewer LUTs on average and have a median LUT-delay product that is 12% lower than comparable LogiCORE IP KCMs. Proposed pipelined KCMs with two to eight selectable coefficients use 46% to 70% fewer LUTs than the best LogiCORE IP based alternative and most are faster than using a LogiCORE IP multiplier with a coefficient lookup function. They also outperform the state-of-the-art in the literature, using 22% to 57% fewer slices than the smallest pipelined adder graph (PAG) fusion designs and operate 7% to 30% faster than the fastest PAG fusion designs for the same operand size and number of selectable coefficients. For KCMs and KCMs with selectable coefficients of a given operand size, the placement and routing of LUTs remains the same for all positive and negative constant values, which is advantageous for runtime partial reconfiguration.

Sparse-Iteration 4D CORDIC Algorithms for Multiplying Quaternions

Novel 4D CORDIC algorithms and hardware architecture for multiplying quaternions are presented, aimed at constant-coefficient multipliers. In our solution, microrotations are multiplications by hypercomplex numbers with only one non-zero imaginary part. Such transformations can be described using sparse matrices and implemented using less hardware resources than the iteration of the known quaternion CORDIC algorithm. Chip area can be saved because sparse microrotations can be computed using a permutation network and two-operand adders, without four-operand additions, which are necessary in the known solution. The obtainable area savings depend on the implementation technology and the architectures of adders and bit shifters but can be as large as 45 and 25 percent for ASIC and FPGA circuits, respectively. The circuitry simplifications come at the cost of slowing down computations: our approach improves the area-delay product, and a single sparse iteration can be executed up to 15 percent faster than the conventional one, but more microrotations are usually necessary to achieve the required accuracy. On the other hand, a sparse 4D iteration can be identified with microrotations of two 2D CORDICs which work in parallel. This makes convergence analysis easier than in the previous 4D solution, as it is sufficient to consider only two dimensions.

Design and simulation of MAC unit using combinational circuit and adder

Hardware and timing complexities of MAC unit to perform arithmetic operation like addition or multiplication especially in the field of Digital Signal Processing (DSP) or Elliptic Curve Cryptography (ECC) are the major issues to the designer. The multiplication operation is essential and abundant in DSP Applications. In order to achieve maximum implementation efficiency and timing performance, designing a DSP systems is critical and frequently presents a significant challenge to hardware engineers. There are certain Multiplier that simplifies this challenge by abstracting away FPGA device specifics, while maintaining the required maximum performance and resource efficiency. These multipliers are able to perform parallel multiplication and hence constant coefficient multiplication, both with differing implementation styles. Again with the aid of instantaneous resource estimation, hardware engineers can rapidly select the optimal solution for their system. The latest additions to the IP provide fine control over the latency using the concept of pipelining of the multipliers that are purely combinatorial to be fully pipelined. Here a new compensation method that reduces both the hardware and timing complexities of the multiplier used for DSP application or ECC application has been proposed. The design of the MAC unit based on the proposed compensation method has been dealt here properly using Xilinx 13.2 and compared with array multiplier, Booth multiplier and Vedic multiplier to show its novelty over them. The hardware complexity is reduced to about 60% of the original multiplier. Design results show that the proposed architecture has lower hardware overhead, lower error and fast operating speed as compared with array, Booth and Vedic multiplier.

An improved constant coefficient multiplication algorithm based on cascaded adder graph

In many digital signal processing algorithms, e.g., digital filters, the multiplier coefficients are constant. Hence, it is possible to implement the multiplier using shifts, adders, and subtracters. In this work a new algorithm of constant coefficient multiplication with few adders and registers is proposed. This approach is based on cascaded adder graph. In this paper all cascaded adder graph structures for any integer can be derived, and the analytical method for the number of register and adder occupation is given. Through comparison of occupied resources, the optimal adder graph can be obtained. Finally, comparing with previous optimal algorithms, a design example for finite impulse response (FIR) filter confirms the validity and good engineering practicability of this algorithm.

VLSI Architecture for 8-Point AI-based Arai DCT having Low Area-Time Complexity and Power at Improved Accuracy

A low complexity digital VLSI architecture for the computation of an algebraic integer (AI) based 8-point Arai DCT algorithm is proposed. AI encoding schemes for exact representation of the Arai DCT transform based on a particularly sparse 2-D AI representation is reviewed, leading to the proposed novel architecture based on a new final reconstruction step (FRS) having lower complexity and higher accuracy compared to the state-of-the-art. This FRS is based on an optimization derived from expansion factors that leads to small integer constant-coefficient multiplications, which are realized with common sub-expression elimination (CSE) and Booth encoding. The reference circuit [1] as well as the proposed architectures for two expansion factors α† = 4.5958 and α′ = 167.2309 are implemented. The proposed circuits show 150% and 300% improvements in the number of DCT coefficients having error ≤ 0:1% compared to [1]. The three designs were realized using both 40 nm CMOS Xilinx Virtex-6 FPGAs and synthesized using 65 nm CMOS general purpose standard cells from TSMC. Post synthesis timing analysis of 65 nm CMOS realizations at 900 mV for all three designs of the 8-point DCT core for 8-bit inputs show potential real-time operation at 2.083 GHz clock frequency leading to a combined throughput of 2.083 billion 8-point Arai DCTs per second. The expansion-factor designs show a 43% reduction in area (A) and 29% reduction in dynamic power (PD) for FPGA realizations. An 11% reduction in area is observed for the ASIC design for α† = 4.5958 for an 8% reduction in total power (PT ). Our second ASIC design having α′ = 167.2309 shows marginal improvements in area and power compared to our reference design but at significantly better accuracy.

Formal Design of Arithmetic Circuits Based on Arithmetic Description Language

This paper presents a formal design of arithmetic circuits using an arithmetic description language called ARITH. The key idea in ARITH is to describe arithmetic algorithms directly with high-level mathematical objects (i.e., number representation systems and arithmetic operations/formulae). Using ARITH, we can provide formal description of arithmetic algorithms including those using unconventional number systems. In addition, the described arithmetic algorithms can be formally verified by equivalence checking with formula manipulations. The verified ARITH descriptions are easily translated into the equivalent HDL descriptions. In this paper, we also present an application of ARITH to an arithmetic module generator, which supports a variety of hardware algorithms for 2-operand adders, multi-operand adders, multipliers, constant-coefficient multipliers and multiply accumulators. The language processing system of ARITH incorporated in the generator verifies the correctness of ARITH descriptions in a formal method. As a result, we can obtain highly-reliable arithmetic modules whose functions are completely verified at the algorithm level.

Simplified Design of Constant Coefficient Multipliers

In many digital signal processing algorithms, e.g., linear transforms and digital filters, the multiplier coefficients are constant. Hence, it is possible to implement the multiplier using shifts, adders, and subtracters. In this work two approaches to realize constant coefficient multiplication with few adders and subtracters are presented. The first yields optimal results, i.e., a minimum number of adders and subtracters, but requires an exhaustive search. Compared with previous optimal approaches, redundancies in the exhaustive search cause the search time to be drastically decreased. The second is a heuristic approach based on signed-digit representation and subexpression sharing. The results for the heuristic are worse in only approximately 1% of all coefficients up to 19 bits. However, the optimal approach results in several different optimal realizations, from which it is possible to pick the best one based on other criteria. Relations between the number of adders, possible coefficients, and number of cascaded adders are presented, as well as exact equations for the number of required full and half adder cells. The results show that the number of adders and subtracters decreases on average 25% for 19-bit coefficients compared with the canonic signed-digit representation.

Constant Coefficient Multiplication Using Look-Up Tables

Multiplication is an important but expensive operation in most FPGA-based signal processing systems. Many techniques have been introduced for reducing the size and improving the speed of FPGA-based multipliers. Constant-coefficient multipliers are an important class of such multipliers that reduce FPGA resource requirements by exploiting constant-specific optimizations. This paper reviews and analyzes a constant coefficient multiplier that exploits the fine-grain memory resources of FPGAs by performing table look-up. Several optimizations to this multiplier are introduced and analyzed. This paper will also introduce several techniques for reducing the resources of this multiplier by exploiting modern FPGA architectural enhancements.

Low-power constant-coefficient multiplier generator

Constant-coefficient multipliers are used in many DSP cores. A new low-power constant multiplier, with detailed design procedure, is presented. A generator written in C++ is used to generate technology-independent VHDL code of the constant multiplier for different input specifications (signed/unsigned, word length, etc.). Synthesis results indicate the new design features less power and area consumption while offering similar speed performance when compared with other general-purpose multipliers.

Evolutionary graph generation system with transmigration capability and its application to arithmetic circuit synthesis

The paper presents a novel graph-based evolutionary optimisation technique called evolutionary graph generation (EGG) and its application to the design of fast constant-coefficient multipliers using parallel counter-tree architecture. A unique feature of EGG is its capability to handle the general graph structures directly in the evolution process instead of encoding the graph structures into indirect representations, such as bit strings and trees. The paper also demonstrates that the evolution process of EGG can be accelerated by a simple operation, called 'transmigration', which is to import previously generated good solutions (constant-coefficient multipliers) for creating multipliers with different target coefficients. The authors' observation shows that transmigration accelerates a typical evolutionary run by an average of 8.7 times. This implies that the EGG system can acquire and reuse useful subcircuit structures contained in the previously generated multipliers during the evolution process.

Graph-based evolutionary design of arithmetic circuits

We present an efficient graph-based evolutionary optimization technique, called evolutionary graph generation (EGG), and the proposed approach is applied to the design of combinational and sequential arithmetic circuits based on parallel counter-tree architecture. The fundamental idea of EGG is to employ general circuit graphs as individuals and manipulate the circuit graphs directly using new evolutionary graph operations without encoding the graphs into other indirect representations, such as the bit strings used in genetic algorithm (GA) proposed by Holland (1992) and trees used in genetic programming (GP) proposed by Koza et al. (1997). In this paper, the EGG system is applied to the design of constant-coefficient multipliers and the design of bit-serial data-parallel adders. The results demonstrate the potential capability of EGG to solve the practical design problems for arithmetic circuits with limited knowledge of computer arithmetic algorithms. The proposed EGG system can help to simplify and speed up the process of designing arithmetic circuits and can produce better solutions to the given problem.

Pragmatic method for the design of fast constant-coefficient combinational multipliers

To characterise and analyse the performance of evolutionary graph generation (EGG) on a cluster of PCs, a parallel version of the EGG system, called the distributed EGG (DEGG) system, has been developed using a message-passing interface (MPI). To demonstrate the capability of DEGG, it is applied to find the optimal design of various multipliers. Experimental results substantially clarify that the DEGG system consistently performs better than the EGG system. Moreover, the ability and solution quality of the DEGG system's search can be further enhanced by the use of the self-adaptation mechanism of operator probabilities.

Evolutionary design for high-speed constant-coefficient multipliers

A novel approach, evolutionary graph generation (EGG), is proposed for the optimal design of constant-coefficient multipliers consisting of an adder and shifter. Experimental results prove that the proposed approach consistently outperforms conventional methods.

FIR filter synthesis algorithms for minimizing the delay and the number of adders

As the complexity of digital filters is dominated by the number of multiplications, many works have focused on minimizing the complexity of multiplier blocks that compute the constant coefficient multiplications required in filters. Although the complexity of multiplier blocks is significantly reduced by using efficient techniques such as decomposing multiplications into simple operations and sharing common subexpressions, previous works have not considered the delay of multiplier blocks which is a critical factor in the design of complex filters. In this paper, we present new algorithms to minimize the complexity of multiplier blocks under the given delay constraints. By analyzing multiplier blocks in view of delay, three delay reduction methods are proposed and combined into previous algorithms. Since the proposed algorithms can generate multiplier blocks that meet the specified delay, a trade-off between delay and hardware complexity is enabled by changing the delay constraints. Experimental results show that the proposed algorithms can reduce the delay of multiplier blocks at the cost of a little increase of complexity.