Design and simulation of MAC unit using combinational circuit and adder

Abstract

Hardware and timing complexities of MAC unit to perform arithmetic operation like addition or multiplication especially in the field of Digital Signal Processing (DSP) or Elliptic Curve Cryptography (ECC) are the major issues to the designer. The multiplication operation is essential and abundant in DSP Applications. In order to achieve maximum implementation efficiency and timing performance, designing a DSP systems is critical and frequently presents a significant challenge to hardware engineers. There are certain Multiplier that simplifies this challenge by abstracting away FPGA device specifics, while maintaining the required maximum performance and resource efficiency. These multipliers are able to perform parallel multiplication and hence constant coefficient multiplication, both with differing implementation styles. Again with the aid of instantaneous resource estimation, hardware engineers can rapidly select the optimal solution for their system. The latest additions to the IP provide fine control over the latency using the concept of pipelining of the multipliers that are purely combinatorial to be fully pipelined. Here a new compensation method that reduces both the hardware and timing complexities of the multiplier used for DSP application or ECC application has been proposed. The design of the MAC unit based on the proposed compensation method has been dealt here properly using Xilinx 13.2 and compared with array multiplier, Booth multiplier and Vedic multiplier to show its novelty over them. The hardware complexity is reduced to about 60% of the original multiplier. Design results show that the proposed architecture has lower hardware overhead, lower error and fast operating speed as compared with array, Booth and Vedic multiplier.