Configuration Memory Bits Research Articles

MTTR reduction of FPGA scrubbing: Exploring SEU sensitivity

SRAM-based FPGAs are widely used for developing many critical systems due to their huge capacity, flexibility, and high performance. However, their applicability in the presence of the Single Event Upsets (SEUs) should be ensured using mitigation techniques for specific critical systems e.g. space applications or automotive industry. Among all existing mitigation techniques, the scrubbing scheme is considered the most reliable technique that particularly avoids SEU accumulation in Configuration Memory (CM) that is the most SEU vulnerable component in an SRAM-based FPGAs. In spite of that, the error repair time realized by Mean Time to Repair (MTTR) attained by scrubbing is a pressing concern for real-time systems. To reduce MTTR, the impact of SEU in CM bits on correct circuit operation is considered in state-of-the-art scrubbing methods. In this paper, we examine the MTTR reduction taking into account multiple proposed precision levels to identify CM sensitive bits; i.e. bits have an adverse impact on correct circuit operation when infected by SEU. Two scrubbing methods are proposed based on these precision levels. Experimental results show an average of 20% \\45% \\46.5% MTTR reduction if the proposed precision-aware scrubbing methods taking into account sensitive bits recognized with low \\medium \\high precision compared to with very low precision. Experiments also show that higher MTTR reduction was achievable for non uniform structure like FFT (i.e about 68%). Thus the cost of distinguishing sensitive bits with higher precision is worth only when the circuit has a non-uniform structure in CM.

A comparative radiation analysis of reconfigurable memory technologies: FinFET versus bulk CMOS

This work describes a comparative radiation reliability analysis between two reconfigurable devices with different manufacturing technology: 28 nm CMOS-based and 16 nm FinFET based FPGAs. The analysis is based on a proton radiation test campaign performed at the PSI radiation facility. As application circuit, a multi-core computational engine was implemented on each one of the reconfigurable devices. The radiation sensitivity has been reported in terms of the SEU cross-section of the configuration memory bits. Results have shown a higher sensitivity of 28 nm CMOS with respect to 16 nm FinFET. Moreover, a detailed comparison of detected Single Event Multiple Upsets (SEMUs) clusters for both technology is reported.

Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs

There are many platforms and tools based on field-programmable gate array (FPGA) devices oriented to facilitate the reliability estimation of digital designs, but they are usually focused only on configuration memory errors since the configuration memory represents the majority of the memory elements in an FPGA. However, an FPGA-based platform could also be exploited to support the emulation of transient and permanent errors for designs intended to work in application-specific integrated circuits (ASICs) or radiation-hardened devices such as antifuse FPGAs. In this context, the obtention of a particular set of bits to flip is required to be able to emulate these error models. The main difficulty of this approach lies in determining the mentioned set of bits, which is due to the unavailability of a public description of the bitstream and the lack of FPGA architecture details. To help with this issue, we present a methodology to determine specific configuration memory bits from SRAM-based FPGAs that, when flipped, emulate permanent or transient upsets in any flip-flop element of the design under test. This methodology is proved in recent FPGA technologies and provides great control and precision in reliability experiments for harsh environments.

An Efficient Methodology for On-Chip SEU Injection in Flip-Flops for Xilinx FPGAs

Field-programmable gate array (FPGA)-based single-event upset (SEU) emulation in user flip-flops is essential for reliability evaluation of mapped designs. Previous approaches to inject SEUs in user flip-flops utilized the configuration memory bits that control the set and reset settings of the flip-flops. In contrast, this paper presents a novel approach for SEU emulation in user flip-flops contents through single-frame on-chip partial reconfiguration (PR). The presented methodology exploits the inherent architectural features of the latest Xilinx FPGAs to support state initialization of flip-flops during PR. The proposed approach does not require instrumentation overhead for flip-flops and reduces the fault-injection times by orders of magnitude.

A Methodology to Emulate Single Event Upsets in Flip-Flops Using FPGAs through Partial Reconfiguration and Instrumentation

This paper presents a methodology to emulate Single Event Upsets (SEUs) in Field Programmable Gate Array (FPGA) flip-flops (FFs). Since the content of a FF is not modifiable through the FPGA configuration memory bits, a dedicated design is required for fault injection in the FFs. The method proposed in this paper is a hybrid approach that combines FPGA partial reconfiguration and extra logic added to the circuit under test, without modifying its operation. This approach has been integrated into a fault-injection platform, named NESSY (Non intrusive ErrorS injection SYstem), developed by our research group. Finally, this paper includes results on a Virtex-5 FPGA demonstrating the validity of the method on the ITC’99 benchmark set and a Feed-Forward Equalization (FFE) filter. In comparison with other approaches in the literature, this methodology reduces the resource consumption introduced to carry out the fault injection in FFs, at the cost of adding very little time overhead ( $1.6~\mu\hbox{s}$ per fault).

Multibit Fault Injection for Field-Programmable Gate Arrays with Simple, Portable Fault Injector

Static random-access-memory-based field-programmable gate array devices are an attractive option for onboard data processing in space systems due to higher computational capabilities and a lower power envelope than traditional processing devices. However, field-programmable gate arrays present unique reliability verification challenges because single-event upsets can trigger both data errors and configuration memory errors, which may cause deviations from the expected system functionality. To evaluate system reliability, traditional fault-injection testing uses numerous test vectors to observe the effects induced by a change of a single configuration memory bit at a time. This single-bit fault-injection methodology provides high fault coverage and testing repeatability, but it requires a long fault-injection time due to the large number of test vectors required to verify the entire design’s functionality. Long injection times are further exacerbated as configuration memory size and design complexity increase. To shorten injection time, a Simple, Portable Fault Injector platform is proposed for field-programmable gate arrays used in tandem with a novel multibit fault-injection methodology that modifies multiple configuration memory bits, referred to as a batch, during each test. The proposed methodology is optimized to efficiently detect the faulty bits within a batch, adaptively select the optimal batch size, and optimize the fault-injection sequence based on the design’s placement. Using relevant case studies, Simple, Portable Fault Injector for field-programmable gate arrays augmented with multibit fault-injection methodology reveals up to 50 times the speedup in fault-injection time.

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization

Because of numerous circuit resources of FPGAs, there is a performance gap between FPGAs and ASICs. In this paper, we propose a small-memory logic cell, COGRE, to reduce the FPGA area. Our approach is to investigate the appearance ratio of the logic functions in a circuit implementation. Moreover, we group the logic functions on the basis of the NPN-equivalence class. The results of our investigation show that only small portions of the NPN-equivalence class can cover large portions of the logic functions used to implement circuits. Further, we found that NPN-equivalence classes with a high appearance ratio can be implemented by using a small number of AND gates, OR gates, and NOT gates. On the basis of this analysis, we develop COGRE architectures composed of several NAND gates and programmable inverters. The experimental results show that the logic area of 4-COGRE is smaller than that of 4-LUT and 5-LUT by approximately 35.79% and 54.70%, respectively. The logic area of 8-COGRE is 75.19% less than that of 8-LUT. Further, the total number of configuration memory bits of 4-COGRE is 8.26% less than the number of configuration memory bits of 4-LUT. The total number of configuration memory bits of 8-COGRE is 68.27% less than the number of configuration memory bits of 8-LUT.

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals

Dynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiple-valued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35µm-CMOS/0.60µm-ferroelectric-capacitor process. The transistor count of the proposed multi-context switch block is reduced to 63% in comparison with that of the SRAM-based one.

Effectiveness of TMR-Based Techniques to Mitigate Alpha-Induced SEU Accumulation in Commercial SRAM-Based FPGAs

We present an experimental analysis of alpha-induced soft errors in 90-nm low-end SRAM-based FPGAs. We first assess the relative sensitivity of the configuration memory bits controlling the different resources in the FPGA. We then study how SEU accumulation in the configuration memory impacts on the reliability of unhardened and hardened-by-design circuits. We analyze different hardening solutions comprising the use of a single voter, multiple voters, and feedback voters implemented with a commercial tool. Finally, we present an analytical model to predict the failure rate as function of the number of bit-flips in the configuration memory.

An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Reconfigurable logic devices (RLDs) are classified as the fine-grained or coarse-grained type based on their basic logic cell architecture. In general, each architecture has its own advantage. Therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In the present paper, we propose a variable grain logic cell (VGLC) architecture, which consists of a 4-bit ripple carry adder with configuration memory bits and develop a technology mapping tool. The key feature of the VGLC architecture is that the variable granularity is a tradeoff between coarse-grained and fine-grained types required for the implementation arithmetic and random logic, respectively. Finally, we evaluate the proposed logic cell using the newly developed technology mapping tool, which improves logic depth by 31% and reduces the number of configuration data by 55% on average, as compared to the Virtex-4 logic cell architecture.