An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Motoki Amagasaki,Ryoichi Yamaguchi,Masahiro Iida,Toshinori Sueyoshi,Masahiro Koga

doi:10.1155/2008/180216

Motoki Amagasaki, Ryoichi Yamaguchi + Show 3 more

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https://doi.org/10.1155/2008/180216

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Abstract

Reconfigurable logic devices (RLDs) are classified as the fine-grained or coarse-grained type based on their basic logic cell architecture. In general, each architecture has its own advantage. Therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In the present paper, we propose a variable grain logic cell (VGLC) architecture, which consists of a 4-bit ripple carry adder with configuration memory bits and develop a technology mapping tool. The key feature of the VGLC architecture is that the variable granularity is a tradeoff between coarse-grained and fine-grained types required for the implementation arithmetic and random logic, respectively. Finally, we evaluate the proposed logic cell using the newly developed technology mapping tool, which improves logic depth by 31% and reduces the number of configuration data by 55% on average, as compared to the Virtex-4 logic cell architecture.

Highlights

System large-scale integrated circuits (LSICs), which exhibit high performance and have high densities, are manufactured using advanced process technologies
The novel architecture, which is based on a 4-bit ripple carry adder that includes configuration memory bits, offers a tradeoff between coarse and fine granularity and can be used for efficient mapping in an application
We have proposed a variable grain logic cell (VGLC) architecture and evaluated the area, delay, and configuration data using a technology mapping tool called VGLC-HeteroMap

Summary

Introduction

System large-scale integrated circuits (LSICs), which exhibit high performance and have high densities, are manufactured using advanced process technologies. Their high costs are an enormous disadvantage. A reconfigurable logic device (RLD), which has circuit programmability, is applied to embedded systems as a hardware intellectual property (IP) core. It is possible for designs to be implemented in the shortest turn-around time from specification to implementation. There is a possibility that design complexity and power distribution problems can be solved using a dynamic reconfigurable processor. It becomes necessary to adapt the frequently changing market cycles, such as that of mobile phones

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