Concurrent Execution Research Articles

Improved Parallel Scanner for the Concurrent Execution of Lexical Analysis Tasks on Multi-Core Systems

Purpose: The processing power of machines will continue to accelerate massively. Modern eras of computing are driven by elevated parallel processing by the revolution of multi-core processors. This continuing trend toward parallel architectural paradigms facilitates parallel processing on a single machine and necessitates parallel programming in order to utilize the machine's enormous processing power. As a consequence, scanner generator applications will eventually need to be parallelized in order to fully leverage the throughput benefits of multi-core processors. This article discusses the way of processing the tasks in parallel during the scanning stage of lexical analysis. This is done by recognizing tokens in different lines of the source program in parallel along with auto detection of keyword in a character stream. Tasks are allocated line-by-line to the multiple instances of the lexical analyzer program. Then, each of the instances is run in parallel to detect tokens on different cores that are not yet engaged. Design/Methodology/Approach: Developing a theoretical and experimental approach for parallelizing the lexical scanning process on a multi-core system. Findings/Result: Based on the developed model, the theoretical and practical results indicate that the suggested methodology outperforms the sequential strategy in terms of tokenization consistently. It significantly decreases the amount of time spent on lexical analysis during the compilation process. It is clearly observed that the speedup should increase at or close to the same rate as the number of cores and keywords in the source program increases. This enhancement would improve the overall compilation time even more. Originality/Value: A hybrid model is developed for the concurrent execution of a lexical analyzer on multi-core systems using a dynamic task allocation algorithm and an auto-keyword detection method. Paper Type: Experimental Research.

Improved Parallel Scanner for the Concurrent Execution of Lexical Analysis Tasks on Multi-Core Systems

Improved Parallel Scanner for the Concurrent Execution of Lexical Analysis Tasks on Multi-Core Systems

A Hybrid Multi-GPU Implementation of Simplex Algorithm with CPU Collaboration

The simplex algorithm has been successfully used for many years in solving linear programming (LP) problems. Due to the intensive computations required (especially for the solution of large LP problems), parallel approaches have also extensively been studied. The computational power provided by the modern GPUs as well as the rapid development of multicore CPU systems have led OpenMP and CUDA programming models to the top preferences during the last years. However, the desired efficient collaboration between CPU and GPU through the combined use of the above programming models is still considered a hard research problem. In the above context, we demonstrate here an excessively efficient implementation of standard simplex, targeting to the best possible exploitation of the concurrent use of all the computing resources, on a multicore platform with multiple CUDA-enabled GPUs. More concretely, we present a novel hybrid collaboration scheme which is based on the concurrent execution of suitably spread CPU-assigned (via multithreading) and GPU-offloaded computations. The experimental results extracted through the cooperative use of OpenMP and CUDA over a notably powerful modern hybrid platform (consisting of 32 cores and two high-spec GPUs – Titan Rtx and Rtx 2080Ti) highlight that the performance of the presented here hybrid GPU/CPU collaboration scheme is clearly superior to the GPU-only implementation under almost all conditions. The corresponding measurements validate the value of using all resources concurrently, even in the case of a multi-GPU configuration platform. Furthermore, the given implementations are completely comparable (and slightly superior in most cases) to other related attempts in the bibliography, and clearly superior to the native CPU implementation with 32 cores. Keywords—Parallel Computing; Linear Programming; Simplex Method; Multicore Platform; Hardware Acceleration, GPGPU; OpenMP; CUDA

Early scheduling on steroids: Boosting parallel state machine replication

State machine replication (SMR) is a standard approach to fault tolerance in which replicas execute requests deterministically and often serially. For performance, some techniques allow concurrent execution of requests in SMR while keeping determinism. Such techniques exploit the fact that independent requests can execute concurrently. A promising category of early scheduling solutions trades scheduling freedom for simplicity, allowing to expedite decisions during scheduling. This paper generalizes early scheduling and proposes a general method to schedule requests to threads, restricting scheduling overhead. Moreover, it explores improvements to the original early scheduling mechanism, namely the use of busy-wait synchronization and work-stealing techniques. We integrate early scheduling and its proposed improvements to a popular SMR framework. Performance results of the basic mechanism and its improvements are presented and compared to more classic approaches, where it is shown that early scheduling with our proposed enhancements can outperform the original early scheduling and other systems by a large margin in many scenarios.

GPU-accelerated and pipelined methylation calling.

The third-generation DNA sequencing technologies, such as Nanopore Sequencing, can operate at very high speeds and produce longer reads, which in turn results in a challenge for the computational analysis of such massive data. Nanopolish is a software package for signal-level analysis of Oxford Nanopore sequencing data. Call-methylation module of Nanopolish can detect methylation based on Hidden Markov Model (HMM). However, Nanopolish is limited by the long running time of some serial and computationally expensive processes. Among these, Adaptive Banded Event Alignment (ABEA) is the most time-consuming step, and the prior work, f5c, has already parallelized and optimized ABEA on GPU. As a result, the remaining methylation score calculation part, which uses HMM to identify if a given base is methylated or not, has become the new performance bottleneck. This article focuses on the call-methylation module that resides in the Nanopolish package. We propose Galaxy-methyl, which parallelizes and optimizes the methylation score calculation step on GPU and then pipelines the four steps of the call-methylation module. Galaxy-methyl increases the execution concurrency across CPUs and GPUs as well as hardware resource utilization for both. The experimental results collected indicate that Galaxy-methyl can achieve 3×-5× speedup compared with Nanopolish, and reduce the total execution time by 35% compared with f5c, on average. The source code of Galaxy-methyl is available at https://github.com/fengyilin118/.

Multi-Agent Real-Time Advanced Metering Infrastructure Based on Fog Computing

This effort to make the power grid more intelligent is tightly coupled with the deployment of advanced metering infrastructure (AMI) as an integral part of the future vision of smart grid. The goal of AMI is to provide necessary information for the consumers and utilities to accurately monitor and manage energy consumption and pricing in real time. Immediate benefits are enhanced transparency and efficiency of energy usage and the improvement of customer services. Although the road map toward successful AMI deployment is clearly defined, many challenges and issues are to be solved regarding the design of AMI. In this paper, a multi-agent AMI based on the fog-computing approach is presented. Architecture follows structural decomposition of AMI functionalities encapsulated in a form of local and area-specific service components that reside at the different tiers of hierarchically organized AMI deployment. Fog computing concepts provide the framework to effectively solve the problems of creating refined and scalable solutions capable of meeting the requirements of the AMI as a part of future smart grid. On the other hand, agent-based design enables concurrent execution of AMI operations across the distributed system architecture, in the same time improving performance of its execution and preserving the scalability of the AMI solution. The real-time performance of the proposed AMI solution, related to the periodic and on-demand acquisition of metering data from the connected electricity meters, was successfully verified during one year of pilot project operation. The detailed analysis of the performance of AMI operation regarding data collection, communication and data availability across the deployed pilot AMI, covering several transformer station areas with diverse grid topologies, is also presented.

A Multisize no Migration Island-Based Differential Evolution Algorithm With Removal of Ineffective Islands

The paper is a continuation of our previous research where a novel concept of multisize island model was proposed. Such multisize approach facilitates the design of island-based algorithms and brings such benefits as: improved fitness dynamics throughout the entire time of operation even without the migration of solutions between the islands. The absence of migration eliminates the need to establish the topology and the policy of migration. It also makes the efficiency of multisize island-based algorithms independent of the particular islands’ size and eliminates the need of tuning the size of islands which is usually done in the case of the canonical island model. All these features indicate the superiority of the multisize island model over the canonical one. In this paper we improved earlier proposed multisize island-based DE algorithm by adding to it the ability to automatically optimize the number of islands in operation. This feature enables the release of most computational units before the algorithm completes its operation in the case of concurrent execution of the algorithm on multiple computational units, or reduction of the algorithm running time in the case of its execution on a single computational unit. The proposed algorithm was tested by solving computationally difficult scheduling problem, which is the discrete-continuous scheduling with continuous resource discretization.

ARTe: Providing real-time multitasking to Arduino

In the last decade, thanks to its modular hardware and straightforward programming model, the Arduino ecosystem became a reference for learning the development of embedded systems by various users, ranging from amateurs and students to makers. However, while the latest released platforms are equipped with modern microcontrollers, the programming model is still tied to a single-threaded, legacy approach. This limits the exploitation of the underlying hardware platform and poses limitations in new application scenarios, such as IoT and UAVs.This paper presents the Arduino real-time extension (ARTe), which seamlessly extends the Arduino programming model to enable the concurrent execution of multiple loops at different rates configurable by the programmer. This is obtained by embedding a low-footprint, real-time operating system in the Arduino framework. The adherence to the original programming model, together with the hidden support for managing the inherent complexity of concurrent software, allows expanding the applicability of the Arduino framework while ensuring a more efficient usage of the computational resources. Furthermore, the proposed approach allows a finer control of the latencies and the energy consumption. Experimental results show that such advantages are obtained at the cost of a small additional overhead and memory footprint. To highlight the benefits introduced by ARTe, the paper finally presents two case studies, one of such in which ARTe has been leveraged to rapidly prototype a mechanical ventilator for acute COVID-19 cases. We found that ARTe allowed our ventilator design to rapidly adapt to changes in the available components and to the evolving needs of Intensive Care Units (ICU) in the Americas.

Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks

In this paper, we present hardware accelerators created with high-level synthesis techniques for sparse and dense matrix multiplication operations. The cores can operate with different precisions and are designed to be integrated in a heterogeneous CPU-FPGA system for Edge AI applications. The methodology involves quantization-sparsity aware training and it is applied to a case study consisting of human activity classification. We initially investigate the effects of quantization and sparsity on the accuracy of neural networks with convolution, dense and recurrent layers observing better tolerance to pruning when recurrent layers are present. Then, we propose the hardware accelerators that can switch precision at run-time and work with any matrix size up to a maximum configured at compile time. We compare the performance of these accelerators at different levels of precision and sparsity levels and create a performance model to enable workload balancing. The results show that the proposed sparse matrix multipliers can outperform dense multipliers when sparsity levels are higher than 70% and the improvements are more evident when higher precision arithmetic or structural pruning is used. Additionally, sparsity levels as high as 99% can maintain the level of accuracy required in the network especially when recurrent layers are deployed. Overall, the balance between sparse and dense performance depends on matrix shape, precision, structural pruning and sparsity levels and performance modelling can be used to balance concurrent execution in a heterogeneous configuration.

Knowledge Dynamics and Behavioural Equivalences in Multi-Agent Systems

We define a process calculus to describe multi-agent systems with timeouts for communication and mobility able to handle knowledge. The knowledge of an agent is represented as sets of trees whose nodes carry information; it is used to decide the interactions with other agents. The evolution of the system with exchanges of knowledge between agents is presented by the operational semantics, capturing the concurrent executions by a multiset of actions in a labelled transition system. Several results concerning the relationship between the agents and their knowledge are presented. We introduce and study some specific behavioural equivalences in multi-agent systems, including a knowledge equivalence able to distinguish two systems based on the interaction of the agents with their local knowledge.

Deciding while moving: Cognitive interference biases value-based decisions

When people act, they repeatedly have to make value-based decisions about the further course of actions. For example, when driving on the highway, they must decide whether to overtake other cars by changing lanes to arrive at their destination quicker; concurrently, they are required to stay on their momentary lane by controlling the steering wheel. Embodied choice models predict that concurrent action execution modulates value-based decisions. Here, we examined whether value-based decisions are influenced by a change of action costs and/or cognitive interference between concurrent actions and decision making. In a novel, computerized multilane tracking task paradigm, participants (N = 50) controlled a cursor moving on one of three horizontal lanes. During tracking (concurrent action), participants had to switch to other lanes to avoid obstacles or collect rewards (value-based decisions). The action costs associated with a lane switch depended on the cursor position relative to the currently tracked lane, and this relationship varied between conditions. Results showed that value-based lane switching decisions were biased by the cursor state. While this influence was partly attributed to minimizing action costs, a considerable part of the influence could be attributed to cognitive interference. Our findings provide further evidence for embodied choice models, showing that both cognitive interference as well as action costs bias value-based decisions.

Research on resource allocation strategy of data center based on cloud computing

With the development of Internet and information technology, cloud computing has attracted extensive attention from industry and academia. The large scale of resources, concurrent execution of multiple tasks and dynamic changes of application resource requests make the resource allocation of data center face severe challenges. To solve the problem of low balance of traditional resource allocation, this paper focuses on the resource allocation optimization of data center, and proposes the resource allocation strategy of data center based on cloud computing, so as to complete the effective resource allocation and assignment. This paper also verifies the designed resource allocation method through example research. The research shows that the distribution balance degree of resource allocation strategy based on cloud computing is significantly higher than the control group, which proves that the designed resource allocation strategy can solve the problem of low balance of traditional resource allocation.

Barriers and Facilitators that Influence on Adopting Healthy Lifestyles in People with Cardiovascular Disease.

Objective:To measure lifestyle changes and describe the barriers and facilitators perceived that influence on adopting healthy lifestyles in people with cardiovascular diseases.Methods:Mixed study of concurrent execution in the public health center of the municipality of Tausa, Colombia. The quantitative phase corresponded to a longitudinal analytical method in which the FANTASTICO instrument was applied to 28 patients in this program between 0 and 120 days after a brief nursing intervention (face-to-face meetings and telephone calls). The qualitative phase was carried out with a micro-ethnographic approach applying a semi-structured interview to 12 out of 28 participants, 120 days after the intervention.Results:During the quantitative phase, a statistically significant change (p < 0.05) was the improvement of the total score and in the domains of activity, type of personality and insight between day 0 and 120. During the qualitative phase, 13 categories arose regarding barriers and facilitators to adopt a healthy lifestyle: four facilitators and one barrier for physical activity, three facilitators and three barriers for feeding, and two facilitators for stress management. By integrating the results, it is possible to explain that, for the change in eating behaviors, physical activity and stress management, personal biological and psychological factors, interpersonal and situational influences coincide with the assumptions and propositions of the Health Promotion Model by Nola Pender.Conclusion:The participants’ lifestyles changed positively in three of the domains and the total of the instrument, which can be explained by simultaneous triangulation, by the facilitators and perceived barriers as influential on adopting behaviors to acquire a healthy lifestyle.

The reads-from equivalence for the TSO and PSO memory models

The verification of concurrent programs remains an open challenge due to the non-determinism in inter-process communication. One recurring algorithmic problem in this challenge is the consistency verification of concurrent executions. In particular, consistency verification under a reads-from map allows to compute the reads-from (RF) equivalence between concurrent traces, with direct applications to areas such as Stateless Model Checking (SMC). Importantly, the RF equivalence was recently shown to be coarser than the standard Mazurkiewicz equivalence, leading to impressive scalability improvements for SMC under SC (sequential consistency). However, for the relaxed memory models of TSO and PSO (total/partial store order), the algorithmic problem of deciding the RF equivalence, as well as its impact on SMC, has been elusive. In this work we solve the algorithmic problem of consistency verification for the TSO and PSO memory models given a reads-from map, denoted VTSO-rf and VPSO-rf, respectively. For an execution of n events over k threads and d variables, we establish novel bounds that scale as n k +1 for TSO and as n k +1 · min( n k 2 , 2 k · d ) for PSO. Moreover, based on our solution to these problems, we develop an SMC algorithm under TSO and PSO that uses the RF equivalence. The algorithm is exploration-optimal , in the sense that it is guaranteed to explore each class of the RF partitioning exactly once, and spends polynomial time per class when k is bounded. Finally, we implement all our algorithms in the SMC tool Nidhugg, and perform a large number of experiments over benchmarks from existing literature. Our experimental results show that our algorithms for VTSO-rf and VPSO-rf provide significant scalability improvements over standard alternatives. Moreover, when used for SMC, the RF partitioning is often much coarser than the standard Shasha-Snir partitioning for TSO/PSO, which yields a significant speedup in the model checking task.

Generating Concurrent Programs From Sequential Data Structure Knowledge Using Answer Set Programming

We tackle the problem of automatically designing concurrent data structure operations given a sequential data structure specification and knowledge about concurrent behavior. Designing concurrent code is a non-trivial task even in simplest of cases. Humans often design concurrent data structure operations by transforming sequential versions into their respective concurrent versions. This requires an understanding of the data structure, its sequential behavior, thread interactions during concurrent execution and shared memory synchronization primitives. We mechanize this design process using automated commonsense reasoning. We assume that the data structure description is provided as axioms alongside the sequential code of its algebraic operations. This information is used to automatically derive concurrent code for that data structure, such as dictionary operations for linked lists and binary search trees. Knowledge in our case is expressed using Answer Set Programming (ASP), and we employ deduction and abduction -- just as humans do -- in the reasoning involved. ASP allows for succinct modeling of first order theories of pointer data structures, run-time thread interactions and shared memory synchronization. Our reasoner can systematically make the same judgments as a human reasoner, while constructing provably safe concurrent code. We present several reasoning challenges involved in transforming the sequential data structure into its equivalent concurrent version. All the reasoning tasks are encoded in ASP and our reasoner can make sound judgments to transform sequential code into concurrent code. To the best of our knowledge, our work is the first one to use commonsense reasoning to automatically transform sequential programs into concurrent code. We also have developed a tool that we describe that relies on state-of-the-art ASP solvers and performs the reasoning tasks involved to generate concurrent code.

Distinct dynamics of neuronal activity during concurrent motor planning and execution

The smooth conduct of movements requires simultaneous motor planning and execution according to internal goals. So far it remains unknown how such movement plans are modified without interfering with ongoing movements. Previous studies have isolated planning and execution-related neuronal activity by separating behavioral planning and movement periods in time by sensory cues. Here, we separate continuous self-paced motor planning from motor execution statistically, by experimentally minimizing the repetitiveness of the movements. This approach shows that, in the rat sensorimotor cortex, neuronal motor planning processes evolve with slower dynamics than movement-related responses. Fast-evolving neuronal activity precees skilled forelimb movements and is nested within slower dynamics. We capture this effect via high-pass filtering and confirm the results with optogenetic stimulations. The various dynamics combined with adaptation-based high-pass filtering provide a simple principle for separating concurrent motor planning and execution.

Smart resource allocation of concurrent execution of parallel applications

AbstractThread‐level parallelism (TLP) has been widely exploited to optimize computational resource usage in high‐performance systems. However, as many applications do not scale as the number of threads increase, resources will be wasted when the application executes with the maximum possible number of threads (i.e., the default execution) rather than fewer threads (thread throttling) that may use the resources more efficiently. Hence, instead of executing only one application with as many threads as possible, one can run more applications simultaneously by applying thread throttling to each one. The primary outcome of this strategy is a significant reduction in the total execution time and energy consumption when the system needs to execute a list of applications. Given that, we propose a smart resource allocation (SRA) for concurrent parallel application execution. It automatically finds the ideal degree of TLP for each application and guides the simultaneous parallel applications execution. When running 25 well‐known benchmarks on three multicore systems and comparing SRA to state‐of‐the‐art strategies (e.g., Batch, Equal policy, and Scalability), SRA improves the EDP by 87.4% over the Batch strategy; 75.5% over the Equal policy; and 38.8% over the scalability strategy.

Sifter: A Service Isolation Strategy for Internet Applications

Service oriented architecture (SOA) provides a flexible platform to build collaborative Internet applications by composing existing self-contained and autonomous services. However, the implicit interactions among the concurrently provisioned services may introduce interference to Internet applications and cause them behave abnormally. It is thus desirable to isolate services to safeguard their application consistency. Existing approaches mostly address this problem by restricting concurrent execution of services to avoid all the implicit interactions. These approaches, however, compromise the performance and flexibility of Internet applications due to the long running nature of services. This paper presents Sifter, a new service isolation strategy for Internet applications. We devise in this strategy a novel static approach to analyze the potential implicit interactions among the services and their impacts on the consistency of the associated Internet applications. By locating only those afflicted implicit interactions that may violate the application consistency, a novel approach based on exception handling and behavior constraints is customized to involved services to eliminate their impacts. We show that this approach exempts the consistency property of Internet applications from being interfered at runtime. The experimental results show that our approach has a better performance than existing solutions.

Towards Faster Execution of Ensemble ML Bootstrap Based Techniques.

Algorithms for ensemble methods (EM) based on bootstrap aggregation often perform copious amount of redundant computations (RC) thus limiting their practicality. Given this constraint, we propose a framework that views these algorithms as a collection of computational units (cu), a tightly coupled set of both mathematical operations and data. This view facilitates a reduction in RC (RRC), thereby allowing for faster execution plans. Inspired by the floor tiling approach in VLSI, we look to engineer solutions for RRC while possibly reconfiguring the underlying computing system's compiler technology stack. We start by showing that under the assumption that the computational system has unbounded but finite memory (i.e., the memory is large enough to hold all intermediate values) and that each cu has a uniform cost, our approach reduces to a well-studied directed bandwidth problem for the directed acyclic graphs (DAGs). Next, we consider a more realistic scenario where the computing system has limited memory and concurrent execution while still assuming a uniform cost. Using a new notion of (r,s) set cover of a DAG (nodes representing computational units and edges representing their interdependencies) we formulate the problem of reducing redundant computational steps in EM as a variation of a directed bandwidth problem. We show that the graph's minimum bandwidth is closely related to memory requirements for studying RRC. Finally, our preliminary experimental results are supportive of the proposed approach for RRC and promising that it can be applied to a broader set of algorithms in decision sciences.

Power and Performance Evaluation of Memory-Intensive Applications

In terms of power and energy consumption, DRAMs play a key role in a modern server system as well as processors. Although power-aware scheduling is based on the proportion of energy between DRAM and other components, when running memory-intensive applications, the energy consumption of the whole server system will be significantly affected by the non-energy proportion of DRAM. Furthermore, modern servers usually use NUMA architecture to replace the original SMP architecture to increase its memory bandwidth. It is of great significance to study the energy efficiency of these two different memory architectures. Therefore, in order to explore the power consumption characteristics of servers under memory-intensive workload, this paper evaluates the power consumption and performance of memory-intensive applications in different generations of real rack servers. Through analysis, we find that: (1) Workload intensity and concurrent execution threads affects server power consumption, but a fully utilized memory system may not necessarily bring good energy efficiency indicators. (2) Even if the memory system is not fully utilized, the memory capacity of each processor core has a significant impact on application performance and server power consumption. (3) When running memory-intensive applications, memory utilization is not always a good indicator of server power consumption. (4) The reasonable use of the NUMA architecture will improve the memory energy efficiency significantly. The experimental results show that reasonable use of NUMA architecture can improve memory efficiency by 16% compared with SMP architecture, while unreasonable use of NUMA architecture reduces memory efficiency by 13%. The findings we present in this paper provide useful insights and guidance for system designers and data center operators to help them in energy-efficiency-aware job scheduling and energy conservation.