Computer Architecture Community Research Articles

Architectural CO2 Footprint Tool: Designing Sustainable Computer Systems With an Architectural Carbon Modeling Tool

Given the performance and efficiency optimizations realized by the computer systems and architecture community over the last decades, the dominating source of computing’s carbon footprint is shifting from operational emissions to embodied emissions. These embodied emissions owe to hardware manufacturing and infrastructure-related activities. Despite the rising embodied emissions, there is a distinct lack of architectural modeling tools to quantify and optimize the end-to-end carbon footprint of computing. This work proposes ACT, an architectural carbon footprint modeling framework, to enable carbon characterization and sustainability-driven early design space exploration. Using ACT we demonstrate optimizing hardware for carbon yields distinct solutions compared to optimizing for performance and efficiency. We construct use cases, based on the three tenets of sustainable design—Reduce, Reuse, Recycle—to highlight future methods that enable strong performance and efficiency scaling in an environmentally sustainable manner

Intel Wins in Four Decades, but AMD Catches Up

Reports on the history, development, and applications supported by Intel's microprocessor product line. Microprocessors have evolved substantially since the introduction of the Intel 4004 half a century ago. Over the years, several processors have stood out for their innovative designs, commercial successes, forays into new application domains, and significant performance and efficiency enhancements compared to their competitors. We polled the computer architecture community, and received votes from 254 processor designers and engineers, researchers from academia and industry, faculty, and graduate students, identifying their favorite processors from every decade since the 1970s, as well as their favorite processor of all time. The results of the poll are presented in this article.

Characterization and Analysis of Deep Learning for 3D Point Cloud Analytics

A point cloud is a collection of points, which is measured by time-of-flight information from LiDAR sensors, forming geometrical representations of the surrounding environment. With the algorithmic success of deep learning networks, point clouds are not only used in traditional application domains like localization or HD map construction but also in a variety of avenues including object classification, 3D object detection, or semantic segmentation. While point cloud analytics are gaining significant traction in both academia and industry, the computer architecture community has only recently begun exploring this important problem space. In this paper, we conduct a detailed, end-to-end characterization on deep learning based point cloud analytics workload, root-causing the frontend data preparation stage as a significant performance limiter. Through our findings, we discuss possible future directions to motivate continued research in this emerging application domain.

Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade

Racetrack memory (RTM) is a novel spintronic memory-storage technology that has the potential to overcome fundamental constraints of existing memory and storage devices. It is unique in that its core differentiating feature is the movement of data, which is composed of magnetic domain walls (DWs), by short current pulses. This enables more data to be stored per unit area compared to any other current technologies. On the one hand, RTM has the potential for mass data storage with unlimited endurance using considerably less energy than today’s technologies. On the other hand, RTM promises an ultrafast nonvolatile memory competitive with static random access memory (SRAM) but with a much smaller footprint. During the last decade, the discovery of novel physical mechanisms to operate RTM has led to a major enhancement in the efficiency with which nanoscopic, chiral DWs can be manipulated. New materials and artificially atomically engineered thin-film structures have been found to increase the speed and lower the threshold current with which the data bits can be manipulated. With these recent developments, RTM has attracted the attention of the computer architecture community that has evaluated the use of RTM at various levels in the memory stack. Recent studies advocate RTM as a promising compromise between, on the one hand, power-hungry, volatile memories and, on the other hand, slow, nonvolatile storage. By optimizing the memory subsystem, significant performance improvements can be achieved, enabling a new era of cache, graphical processing units, and high capacity memory devices. In this article, we provide an overview of the major developments of RTM technology from both the physics and computer architecture perspectives over the past decade. We identify the remaining challenges and give an outlook on its future.

Hardware-Conscious Stream Processing

Data stream processing systems (DSPSs) enable users to express and run stream applications to continuously process data streams. To achieve realtime data analytics, recent researches keep focusing on optimizing the system latency and throughput. Witnessing the recent great achievements in the computer architecture community, researchers and practitioners have investigated the potential of adoption hardware-conscious stream processing by better utilizing modern hardware capacity in DSPSs. In this paper, we conduct a systematic survey of recent work in the field, particularly along with the following three directions: 1) computation optimization, 2) stream I/O optimization, and 3) query deployment. Finally, we advise on potential future research directions.

Top Picks in Computer Architecture from Conferences in 2018

The author introduces the top picks selection of papers in computer architecture that were published in 2018. This is the 16th year of publication of what has now become a tradition in the computer architecture community. Each year, the MICRO Top Picks selection committee, which I chaired for this year, selects 12 papers for this special issue, to highlight for the IEEE Micro readership, a sample of the papers published in 2018 that have architectural contributions of potentially high impact and significance. After a short review of the selection process the papers are briefly summarized.

A Survey of Computer Architecture Simulation Techniques and Tools

Computer architecture simulators play an important role in advancing computer architecture research. With wider research directions and the increased number of simulators that have been developed, it becomes harder to choose a particular simulator to use. This paper reviews the fundamentals of different computer architecture simulation techniques. It also surveys many computer architecture simulators and classifies them into different groups based on their simulation models. Comparing computer architecture simulators with each other and validating their accuracy have been demanding tasks for architects. In addition to providing a survey of computer architecture simulation tools, we measured the experimental error of six contemporary computer architecture simulators: gem5, MARSS×86 , Multi2Sim, PTLsim, Sniper, and ZSim. We also performed a detailed comparison of these simulators based on other features such as flexibility and micro-architectural details. We believe that this paper will be a very useful resource for the computer architecture community especially for early-stage computer architecture and systems researchers to gain exposure to the existing architecture simulation options.

Extending Flash Lifetime in Embedded Processors by Expanding Analog Choice

We extend the lifetime of Flash memory in embedded processors by exploiting the fact that data from sensors is inherently analog. Prior work in the computer architecture community has assumed that all data is digital and has overlooked the opportunities available when working with analog data, such as the data recorded by sensors. In this paper, we introduce redundancy into the quantization of sensor data in order to provide several alternative representations. Notably, we tradeoff distortion—the difference between the sensed analog value and the digital quantization of that value—to improve lifetime. Our simulations show that when combining rate, distortion, and lifetime tradeoffs we can extend Flash lifetime at a far smaller capacity cost compared to prior work. More specifically the simulated system shows that it is possible to achieve up to $2.75 \times$ less capacity cost compared to redundant Flash memory and $1.29 \times$ less capacity cost compared to the state of the art coding schemes.

Databases on Modern Hardware: How to Stop Underutilization and Love Multicores

Abstract Data management systems enable various influential applications from high-performance online services (e.g., social networks like Twitter and Facebook or financial markets) to big data analytics (e.g., scientific exploration, sensor networks, business intelligence). As a result, data management systems have been one of the main drivers for innovations in the database and computer architecture communities for several decades. Recent hardware trends require software to take advantage of the abundant parallelism existing in modern and future hardware. The traditional design of the data management systems, however, faces inherent scalability problems due to its tightly coupled components. In addition, it cannot exploit the full capability of the aggressive micro-architectural features of modern processors. As a result, today's most commonly used server types remain largely underutilized leading to a huge waste of hardware resources and energy. In this book, we shed light on the challenges present whi...

Power Density

<fig orientation="portrait" position="float" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <graphic orientation="portrait" position="float" xlink:href="henke-2667640.tif"/> </fig> <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Power density</b> is one of the most stringent constraints in designing on-chip systems. This seems surprising at first sight considering that the switching energy of a transistor in current CMOS technology is only about a 1/1000 of what it used to be a quarter century ago. Still, power density is rapidly increasing. One of the main causes is that voltage can hardly be scaled further down (see also “Dennard Scaling”). As a result, not all the core of many multicore chips can run simultaneously at the highest performance level. Cooling is either too expensive or simply impossible. This observation led to the notion of “Dark Silicon.” It was initially coined in a paper from the computer architecture community (“Dark silicon and the end of multicore scaling,” ISCA 2011) and later on, it was adapted by the design automation community with various special session and invited talks on major conferences which sparked new ideas. It implied that a large amount of cores would need to be idle (stay “dark”) in order to cope with the power density. It is clear though that the silicon footprint is too expensive to let cores idle. This special issue on “Dark Silicon” takes this challenge and presents various ways to make the best use of all on-chip cores even though power density is at a limit. Many thanks to the Guest Editors Muhammad Shafique, Siddharth Garg, and Vikas Chandra, who brought this interesting topic to the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IEEE Design&amp;Test</i> with five papers plus a comprehensive survey on the topic.

Cloud Server Benchmark Suite for Evaluating New Hardware Architectures

Adding new hardware features to a cloud computing server requires testing both the functionality and the performance of the new hardware mechanisms. However, commonly used cloud computing server workloads are not well-represented by the SPEC integer and floating-point benchmark and Parsec suites typically used by the computer architecture community. Existing cloud benchmark suites for scale-out or scale-up computing are not representative of the most common cloud usage, and are very difficult to run on a cycle-accurate simulator that can accurately model new hardware, like gem5. In this paper, we present PALMScloud, a suite of cloud computing benchmarks for performance evaluation of cloud servers, that is ready to run on the gem5 cycle-accurate simulator. We conduct a behavior characterization and analysis of the benchmarks. We hope that these cloud benchmarks, ready to run on a dual-machine gem5 simulator or on real machines, can be useful to other researchers interested in improving hardware micro-architecture and cloud server performance.

Research Infrastructures for Hardware Accelerators

Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors, and extensive research infrastructure has been developed to support research efforts in this domain. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, computer architects must add accelerator-related research infrastructures to their toolboxes to explore future heterogeneous systems. This book serves as a primer for the field, as an overview of the vast literature on accelerator architectures and their design flows, and as a resource guidebook for researchers working in related areas.

When data management systems meet approximate hardware

Recently, approximate hardware designs have got many research interests in the computer architecture community. The essential idea of approximate hardware is that the hardware components such as CPU, memory and storage can trade off the accuracy of results for increased performance, reduced energy consumption, or both. We propose a DBMS ApproxiDB with its design, implementation and optimization aware of the underlying approximate hardware. ApproxiDB will run on a hybrid machine consisting of both approximate hardware and precise hardware (i.e., the conventional hardware without sacrificing the accuracy). With approximate hardware, ApproxiDB can efficiently support the concept of approximate query processing, without the overhead of pre-computed synopses or sampling techniques. More importantly, ApproxiDB is also beneficial to precise query processing, by developing non-trivial hybrid execution mechanisms on both precise and approximate hardware. In this vision paper, we sketch the initial design of ApproxiDB, discuss the technical challenges in building this system and outline an agenda for future research.

Top Picks from the 2013 Computer Architecture Conferences

This special issue is the eleventh in an important tradition in the computer architecture community: IEEE Micro's Top Picks from the Computer Architecture Conferences. This tradition provides a means for sharing a sample of the best papers published in computer architecture in 2013 with the IEEE Micro readership and researchers in the computer architecture community.

A survey of memory architecture for 3D chip multi-processors

3D chip multi-processors (3D CMPs) combine the advantages of 3D integration and the parallelism of CMPs, which are emerging as active research topics in VLSI and multi-core computer architecture communities. One significant potentiality of 3D CMPs is to exploit the diversity of integration processes and high volume of vertical TSV bandwidth to mitigate the well-known “Memory Wall” problem. Meanwhile, the 3D integration techniques are under the severe thermal, manufacture yield and cost constraints. Research on 3D stacking memory hierarchy explores the high performance and power/thermal efficient memory architectures for 3D CMPs. The micro-architectures of memories can be designed in the 3D integrated circuit context and integrated into 3D CMPs. This paper surveys the design of memory architectures for 3D CMPs. We summarize current research into two categories: stacking cache-only architectures and stacking main memory architectures for 3D CMPs. The representative works are reviewed and the remaining opportunities and challenges are discussed to guide the future research in this emerging area.

Effective and efficient microprocessor design space exploration using unlabeled design configurations

Ever-increasing design complexity and advances of technology impose great challenges on the design of modern microprocessors. One such challenge is to determine promising microprocessor configurations to meet specific design constraints, which is called Design Space Exploration (DSE). In the computer architecture community, supervised learning techniques have been applied to DSE to build regression models for predicting the qualities of design configurations. For supervised learning, however, considerable simulation costs are required for attaining the labeled design configurations. Given limited resources, it is difficult to achieve high accuracy. In this article, inspired by recent advances in semisupervised learning and active learning, we propose the COAL approach which can exploit unlabeled design configurations to significantly improve the models. Empirical study demonstrates that COAL significantly outperforms a state-of-the-art DSE technique by reducing mean squared error by 35% to 95%, and thus, promising architectures can be attained more efficiently.

재구성 가능한 라스트 레벨 캐쉬 구조를 위한 코어 인지 캐쉬 교체 기법

멀티코어 프로세서에서 라스트 레벨 캐쉬는 코어와 메모리의 속도 차이를 줄여주는 역할을 하는 중요한 하드웨어 자원이다. 때문에 라스트 레벨 캐쉬의 효율적인 관리는 프로세서의 성능에 큰 영향을 미친다. 라스트 레벨 캐쉬를 구성하는 공유/비공유 캐쉬는 코어들이 공유하는 데이터와 각 코어의 독립된 데이터를 각각 적재한다. 최근 많은 연구를 통해 라스트 레벨 캐쉬 관리기법이 연구되었지만 주로 공유 캐쉬에 대한 연구만 이뤄지고 있으며 라스트 레벨 캐쉬의 비공유 캐쉬에 대한 연구는 아직 미약하다. 라스트 레벨 캐쉬의 비공유 캐쉬는 각 코어에 동일한 영역이 할당되기 때문에 코어별 작업량이 다를 경우 캐쉬 관리가 효과적이지 않다. 본 논문에서는 라스트 레벨 캐쉬 중 비공유 캐쉬의 효율적인 관리를 위해 코어 인지 캐쉬 교체 기법을 제안한다. 제안된 코어 인지 캐쉬 교체 기법은 비공유 캐쉬를 동적으로 재구성함으로써, 라스트 레벨 캐쉬의 적중률을 향상시킨다. 또한, 우리는 캐쉬 교체 기법의 성능 향상을 위해 2비트 포화 카운터를 적용하였다. 실험 결과 기존의 교체 기법과 비교하여 9.23%의 적중률 향상과 12.85%의 라스트 레벨 캐쉬 접근 시간 감소의 효과가 있었다. In multi-core processors, Last Level Cache(LLC) can reduce the speed gap between the memory and the core. For this reason, LLC has big impact on the performance of processors. LLC is composed of shared cache and private cache. In computer architecture community, most researchers have mainly focused on the management techniques for shared cache, while management techniques for private cache have not been widely researched. In conventional private LLC, memory is statically assigned to each core, resulting in serious performance degradation when the workloads are not fairly distributed. To overcome this problem, this paper proposes the replacement policy for managing private cache of LLC efficiently. As proposed core-aware cache replacement policy can reconfigure LLC dynamically, hit rate of LLC is increases drastically. Moreover, proposed policy uses 2-bit saturating counters to improve the performance. According to our simulation results, the proposed method can improve hit rates by 9.23% and reduce the access time by 12.85% compared to the conventional method.

Security Basics for Computer Architects

Abstract Download Free Sample Design for security is an essential aspect of the design of future computers. However, security is not well understood by the computer architecture community. Many important security aspects have evolved over the last several decades in the cryptography, operating systems, and networking communities. This book attempts to introduce the computer architecture student, researcher, or practitioner to the basic concepts of security and threat-based design. Past work in different security communities can inform our thinking and provide a rich set of technologies for building architectural support for security into all future computers and embedded computing devices and appliances. I have tried to keep the book short, which means that many interesting topics and applications could not be included. What the book focuses on are the fundamental security concepts, across different security communities, that should be understood by any computer architect trying to design or evaluate secu...

DNA-based molecular architecture with spatially localized components

Performing computation inside living cells offers life-changing applications, from improved medical diagnostics to better cancer therapy to intelligent drugs. Due to its bio-compatibility and ease of engineering, one promising approach for performing in-vivo computation is DNA strand displacement. This paper introduces computer architects to DNA strand displacement "circuits", discusses associated architectural challenges, and proposes a new organization that provides practical composability. In particular, prior approaches rely mostly on stochastic interaction of freely diffusing components. This paper proposes practical spatial isolation of components, leading to more easily designed DNA-based circuits. DNA nanotechnology is currently at a turning point, with many proposed applications being realized [20, 9]. We believe that it is time for the computer architecture community to take notice and contribute.

Top Picks from the 2012 Computer Architecture Conferences

This special issue is the tenth in an important tradition in the computer architecture community: IEEE Micro's Top Picks from the Computer Architecture Conferences. This tradition provides a means for sharing a sample of the best papers published in computer architecture in 2012 with the IEEE Micro readership and researchers in the computer architecture community.