Power Density

Abstract

<fig orientation="portrait" position="float" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <graphic orientation="portrait" position="float" xlink:href="henke-2667640.tif"/> </fig> <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Power density</b> is one of the most stringent constraints in designing on-chip systems. This seems surprising at first sight considering that the switching energy of a transistor in current CMOS technology is only about a 1/1000 of what it used to be a quarter century ago. Still, power density is rapidly increasing. One of the main causes is that voltage can hardly be scaled further down (see also “Dennard Scaling”). As a result, not all the core of many multicore chips can run simultaneously at the highest performance level. Cooling is either too expensive or simply impossible. This observation led to the notion of “Dark Silicon.” It was initially coined in a paper from the computer architecture community (“Dark silicon and the end of multicore scaling,” ISCA 2011) and later on, it was adapted by the design automation community with various special session and invited talks on major conferences which sparked new ideas. It implied that a large amount of cores would need to be idle (stay “dark”) in order to cope with the power density. It is clear though that the silicon footprint is too expensive to let cores idle. This special issue on “Dark Silicon” takes this challenge and presents various ways to make the best use of all on-chip cores even though power density is at a limit. Many thanks to the Guest Editors Muhammad Shafique, Siddharth Garg, and Vikas Chandra, who brought this interesting topic to the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IEEE Design&amp;Test</i> with five papers plus a comprehensive survey on the topic.