Computational Units Research Articles

A Visual Comparison of Silent Error Propagation.

High-performance computing (HPC) systems play a critical role in facilitating scientific discoveries. Their scale and complexity (e.g., the number of computational units and software stack) continue to grow as new systems are expected to process increasingly more data and reduce computing time. However, with more processing elements, the probability that these systems will experience a random bit-flip error that corrupts a program's output also increases, which is often recognized as silent data corruption. Analyzing the resiliency of HPC applications in extreme-scale computing to silent data corruption is crucial but difficult. An HPC application often contains a large number of computation units that need to be tested, and error propagation caused by error corruption is complex and difficult to interpret. To accommodate this challenge, we propose an interactive visualization system that helps HPC researchers understand the resiliency of HPC applications and compare their error propagation. Our system models an application's error propagation to study a program's resiliency by constructing and visualizing its fault tolerance boundary. Coordinating with multiple interactive designs, our system enables domain experts to efficiently explore the complicated spatial and temporal correlation between error propagations. At the end, the system integrated a nonmonotonic error propagation analysis with an adjustable graph propagation visualization to help domain experts examine the details of error propagation and answer such questions as why an error is mitigated or amplified by program execution.

High-performance unified modular multiplication algorithm and hardware architecture over G(2m)

The finite field Modular Multiplier (MM) over GF (2m) based on the National Institute of Standards and Technology (NIST) recommended polynomials can be used as a critical component in many cryptosystems. But much of the research suffers from the problems of only supporting a single curve or being very inefficient. In this paper, we present a KA-based unified algorithm (hybrid field size) and its corresponding architecture for high-performance implementation of the systolic modular multiplier over GF (2m), which can support all the NIST recommended polynomials. A number of efficient techniques have been explored and used to realize a high-performance implementation of the multiplier. First, we propose a three-term KA based MM approach and make it fit for systolic implementation. Second, we propose a configurable, unified irreducible polynomial that can support all five curves recommended by NIST and the corresponding modular reduction method. Third, the corresponding systolic structure is also designed in accordance with (1) and (2) to improve efficiency, and we adopt register sharing and computation unit sharing methods to reduce the space complexity of the proposed structure. Additionally, parallel computation of two163-width MMs is employed to improve resource utilization further. From the synthesis results on ASIC, it is shown that the proposed multipliers have significantly lower latency and higher performance than the existing designs. e.g., the proposed structure could achieve up to a 73 % reduction in area-delay product (ADP) over the existing structures.

Stable coding of aversive associations in medial prefrontal populations.

The medial prefrontal cortex (mPFC) is at the core of numerous psychiatric conditions, including fear and anxiety-related disorders. Whereas an abundance of evidence suggests a crucial role of the mPFC in regulating fear behaviour, the precise role of the mPFC in this process is not yet entirely clear. While studies at the single-cell level have demonstrated the involvement of this area in various aspects of fear processing, such as the encoding of threat-related cues and fear expression, an increasingly prevalent idea in the systems neuroscience field is that populations of neurons are, in fact, the essential unit of computation in many integrative brain regions such as prefrontal areas. What mPFC neuronal populations represent when we face threats? To address this question, we performed electrophysiological single-unit population recordings in the dorsal mPFC while mice faced threat-predicting cues eliciting defensive behaviours, and performed pharmacological and optogenetic inactivations of this area and the amygdala. Our data indicated that the presence of threat-predicting cues induces a stable coding dynamics of internally driven representations in the dorsal mPFC, necessary to drive learned defensive behaviours. Moreover, these neural population representations primary reflect learned associations rather than specific defensive behaviours, and the construct of such representations relies on the functional integrity of the amygdala.

Numerical simulation method and deterioration analysis of load-bearing performance of tunnel linings containing cold joints in plain concrete

Cracking in tunnel linings is a common issue in tunnel engineering, with the main cause being construction-induced defects. As a construction-induced defect in a lining, a cold joint affects the bearing capacity of the lining, and the effect of cold joints on the bearing performance deterioration of linings remains unclear. In this study, 180 high-speed railroad tunnels built in Grade III surrounding rock areas were investigated to determine their degradation states, and the distribution of lining cracks in these tunnels was explored on the basis of different factors. Subsequently, three-point bending experiments were conducted on concrete components with different pouring interval cold joint. Based on the experimental results, a computational unit applicable to cold joint simulation was proposed, and the unit parameters were inverted. Finally, the unit was applied to establish a tunnel model with cold joints and to analyze the deterioration effect of cold joints on the bearing performance of the lining. The cracks caused by cold joints in the lining of a structure were found to extend perpendicular to the lining surface, and this can greatly affect the overall strength of the structure. It's important to consider the impact of cold joints on the lining. In order to simulate these cold joints, cohesive elements were used to calculate the maximum stress and stiffness degradation of the lining with and without cold joint elements. The results showed that there were only small differences, indicating that cohesive elements are effective for simulating cold joints. Two cracking patterns were identified, the dorsal tension misalignment model and the medial tension misalignment model, which are related to the stress state of the cold joints. It's necessary to pay attention to cold joints in the inner tensioned area of the lining and those that exceed the final setting time of concrete during pouring.

Large-scale single-neuron speech sound encoding across the depth of human cortex

Understanding the neural basis of speech perception requires that we study the human brain both at the scale of the fundamental computational unit of neurons and in their organization across the depth of cortex. Here we used high-density Neuropixels arrays1–3 to record from 685 neurons across cortical layers at nine sites in a high-level auditory region that is critical for speech, the superior temporal gyrus4,5, while participants listened to spoken sentences. Single neurons encoded a wide range of speech sound cues, including features of consonants and vowels, relative vocal pitch, onsets, amplitude envelope and sequence statistics. Neurons at each cross-laminar recording exhibited dominant tuning to a primary speech feature while also containing a substantial proportion of neurons that encoded other features contributing to heterogeneous selectivity. Spatially, neurons at similar cortical depths tended to encode similar speech features. Activity across all cortical layers was predictive of high-frequency field potentials (electrocorticography), providing a neuronal origin for macroelectrode recordings from the cortical surface. Together, these results establish single-neuron tuning across the cortical laminae as an important dimension of speech encoding in human superior temporal gyrus.

A General Approach to Dropout in Quantum Neural Networks

AbstractIn classical machine learning (ML), “overfitting” is the phenomenon occurring when a given model learns the training data excessively well, and it thus performs poorly on unseen data. A commonly employed technique in ML is the so called “dropout,” which prevents computational units from becoming too specialized, hence reducing the risk of overfitting. With the advent of quantum neural networks (QNNs) as learning models, overfitting might soon become an issue, owing to the increasing depth of quantum circuits as well as multiple embedding of classical features, which are employed to give the computational nonlinearity. Here, a generalized approach is presented to apply the dropout technique in QNN models, defining and analyzing different quantum dropout strategies to avoid overfitting and achieve a high level of generalization. This study allows to envision the power of quantum dropout in enabling generalization, providing useful guidelines on determining the maximal dropout probability for a given model, based on overparametrization theory. It also highlights how quantum dropout does not impact the features of the QNN models, such as expressibility and entanglement. All these conclusions are supported by extensive numerical simulations and may pave the way to efficiently employing deep quantum machine learning (QML) models based on state‐of‐the‐art QNNs.

Toddler monitoring system in vehicle using single shot detector mobilenet and single shot detector-inception on Jetson Nano

<p>Road vehicles are today’s primary form of transportation; the safety of children passengers must take precedence. Numerous reports of toddler death in road vehicles, include heatstroke and accidents caused by negligent parents. In this research, we report a system developed to monitor and detect a toddler's presence in a vehicle and to classify the toddler's seatbelt status. The objective of the toddler monitoring system is to monitor the child's conditions to ensure the toddler's safety. The device senses the toddler's seatbelt status and warns the driver if the child is left in the car after the vehicle is powered off. The vision-based monitoring system employs deep learning algorithms to recognize infants and seatbelts, in the interior vehicle environment. Due to its superior performance, the Nvidia Jetson Nano was selected as the computational unit. Deep learning algorithms such as faster region-based convolutional neural network (R-CNN), single shot detector (SSD)- MobileNet, and single shot detector (SSD)-Inception was utilized and compared for detection and classification. From the results, the object detection algorithms using Jetson Nano achieved 80 FPS, with up to 82.98% accuracy, making it feasible for online and real-time in-vehicle monitoring with low power requirements</p>

Hierarchies in Visual Pathway: Functions and Inspired Artificial Vision.

The development of artificial intelligence has posed a challenge to machine vision based on conventional complementary metal-oxide semiconductor (CMOS) circuits owing to its high latency and inefficient power consumption originating from the data shuffling between memory and computation units. Gaining more insights into the function of every part of the visual pathway for visual perception can bring the capabilities of machine vision in terms of robustness and generality. Hardware acceleration of more energy-efficient and biorealistic artificial vision highly necessitates neuromorphic devices and circuits that are able to mimic the function of each part of the visual pathway. In this paper, wereview the structure and function of the entire class of visual neurons from the retina to the primate visual cortex within reach (Chapter 2) are reviewed. Based on the extraction of biological principles, the recent hardware-implemented visual neurons located in different parts of the visual pathway are discussed in detail in Chapters 3 and 4. Furthermore, valuable applications of inspired artificial vision in different scenarios (Chapter 5) are provided. The functional description of the visual pathway and its inspired neuromorphic devices/circuits are expected to provide valuable insights for the design of next-generation artificial visual perception systems.

Design and analysis of hybrid 10T adder for low power applications

Recently, a growing focus has been on the need for ultra-low-voltage (ULV) functioning to reduce energy usage. The full adder is a fundamental computational arithmetic unit in various image and signal processing applications. This study presents a novel architectural design for a 1-bit adder that utilizes 10 transistors. The concept relies on an energy-efficient hybrid logic multiplexer approach incorporating Gate Diffusion Input (GDI) logic. The primary goal of the suggested design for a hybrid full adder is to decrease power consumption while concurrently decreasing the required area. The suggested innovative architectural design for a full adder incorporates level restoration carry logic and ensures a complete swing output voltage. The designs have been analyzed in a standard environment using 45-nm CMOS process technology, with various supply voltages utilized. The evaluation of the adder cells focuses on speed, power consumption, power-delay-product (PDP), and space efficiency compared to the existing full adders. The recommended full adder cells were subjected to comprehensive simulation tests utilizing the Mentor Graphics environment. The results suggest that these cells surpass their counterparts, exhibiting a minimum of 80 % enhancements in their power-delay product (PDP) parameters. Also the comparisons have been made between the proposed full adders with and without level restoration techniques. The proposed level restoration technique based full adder yields better performance in terms of power and delay when compared to proposed full adder without level restoration.

Time series quantum classifiers with amplitude embedding

Quantum Machine Learning was born during the past decade as the intersection of Quantum Computing and Machine Learning. Today, advances in quantum computer hardware and the design of simulation frameworks able to run quantum algorithms in classic computers make it possible to extend classic artificial intelligence models to a quantum environment. Despite these achievements, several questions regarding the whole quantum machine learning pipeline remain unanswered, for instance the problem of classical data representation on quantum hardware, or the methodologies for designing and evaluating quantum models for common learning tasks such as classification, function approximation, clustering, etc. These problems become even more difficult to solve in the case of Time Series processing, where the context of past historical data may influence the behavior of the decision-making model. In this piece of research, we address the problem of Time Series classification using quantum models, and propose an efficient and compact representation of time series in quantum data using amplitude embedding. The proposal is capable of representing a time series of length n in log2(n)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$log_2(n)$$\\end{document} computational units, and experiments conducted on benchmark time series classification problems show that quantum models designed for classification can also outperform the accuracy of classic methods.

Exploring machine learning to hardware implementations for large data rate x-ray instrumentation

Over the past decade, innovations in radiation and photonic detectors considerably improved their resolution, pixel density, sensitivity, and sampling rate, which all contribute to increased data generation rates. This huge data increases the amount of storage required, as well as the cabling between the source and the storage units. To overcome this problem, edge machine learning (EdgeML) proposes to move computation units near the detectors, utilizing machine learning (ML) models to emulate non-linear mathematical relationships between detector’s output data. ML algorithms can be implemented in digital circuits, such as application-specific integrated circuits and field-programmable gate arrays, which support both parallelization and pipelining. EdgeML has both the benefits of edge computing and ML models to compress data near the detectors. This paper explores the currently available tool-flows designed to translate software ML algorithms to digital circuits near the edge. The main focus is on tool-flows that provide a diverse range of supported models, optimization techniques, and compression methods. We compare their accessibility, performance, and ease of use, and compare them for two high data-rate instrumentation applications: (1) CookieBox, and (2) billion-pixel camera.

Utilizing blockchains in opportunistic networks for integrity and confidentiality

Opportunistic networks (OppNets) are usually a set of smart, wearable, and portable devices or entities with mobility that connect wirelessly without requiring infrastructure. Such a network is of great importance in data transmission, particularly in incidents and disasters, whether man-made or natural. However, message integrity and confidentiality are of concern when dealing with vital and physiological data transmission under strict privacy regulations. In this work, we propose a structure to classify messages based on their priority in different queues. Furthermore, due to the decentralized architecture of OppNets, we propose a blockchain-based structure for providing security for high-priority messages. It contains three sequences of functional blocks with a light and simplified implementation that make it suitable for battery-powered wearable devices that are limited in energy consumption and computational units. The simulation results show that by increasing the number of nodes in the network, the average of the changes in block sizes is neglectable, which addresses the computation bottleneck. Furthermore, we analyze the performance of the proposed structure in terms of message delivery and network overhead compared with the Epidemic and Prophet routing algorithms. These results indicate advancing the overall performance of the proposed algorithm.

Latency Reduction and Packet Synchronization in Low-Resource Devices Connected by DDS Networks in Autonomous UAVs.

Real-time flight controllers are becoming dependent on general-purpose operating systems, as the modularity and complexity of guidance, navigation, and control systems and algorithms increases. The non-deterministic nature of operating systems creates a critical weakness in the development of motion control systems for robotic platforms due to the random delays introduced by operating systems and communication networks. The high-speed operation and sensitive dynamics of UAVs demand fast and near-deterministic communication between the sensors, companion computer, and flight control unit (FCU) in order to achieve the required performance. In this paper, we present a method to assess communications latency between a companion computer and an RTOS open-source flight controller, which is based on an XRCE-DDS bridge between clients hosted in the low-resource environment and the DDS network used by ROS2. A comparison based on the measured statistics of latency illustrates the advantages of XRCE-DDS compared to the standard communication method based on MAVROS-MAVLink. More importantly, an algorithm to estimate latency offset and clock skew based on an exponential moving average filter is presented, providing a tool for latency estimation and correction that can be used by developers to improve synchronization of processes that rely on timely communication between the FCU and companion computer, such as synchronization of lower-level sensor data at the higher-level layer. This addresses the challenges introduced in GNC applications by the non-deterministic nature of general-purpose operating systems and the inherent limitations of standard flight controller hardware.

Ultrafast SET/RESET operation for optoelectronic hybrid phase-change memory device cells based on Ge2Sb2Te5 material using partial crystallization strategy

Combination of nonvolatile storage and in-memory computing promises to break through the “memory bottleneck” that computing device adopts von Neumann architecture with individual computing and memory unit. Thus, the advanced nonvolatile memory device with ultrafast operation speed is urgently required. Here, the optoelectronic hybrid phase-change memory based on the Ge2Sb2Te5 material is proposed, where the picosecond laser induced reversible phase-change is utilized to write and erase the information while the resistance difference is adopted to realize the accurate information readout. Due to the significant difference in resistance between crystalline and amorphous states, a partial crystallization strategy can be adopted to achieve ultrafast SET operation. Results indicate that SET operation speed of the Ge2Sb2Te5 film and device unit can be as fast as 52 and 130 ps, respectively, while the RESET speed reaches 13 ps. In parallel, the resistance ratio of RESET to SET state is still as high as two orders of magnitude. By using partial crystallization strategy, the phase-change induced by picosecond laser only occurs from amorphous to face-centered-cubic crystalline state with low crystallinity and the defective octahedral motif is observed in the Ge2Sb2Te5 film, which is beneficial to achieve the ultrafast operation speed. At the same time, the ordered clusters existed in the as-deposited and picosecond laser induced RESET films can accelerate the nucleation process of the Ge2Sb2Te5 film, which is one of the important reasons for achieving ultrafast SET speed. The optoelectronic hybrid phase-change memory with ultrafast operation speed may be one of the promising solutions for the in-memory computing.

Digital Modeling on Large Kernel Metamaterial Neural Network.

Deep neural networks (DNNs) utilized recently are physically deployed with computational units (e.g., CPUs and GPUs). Such a design might lead to a heavy computational burden, significant latency, and intensive power consumption, which are critical limitations in applications such as the Internet of Things (IoT), edge computing, and the usage of drones. Recent advances in optical computational units (e.g., metamaterial) have shed light on energy-free and light-speed neural networks. However, the digital design of the metamaterial neural network (MNN) is fundamentally limited by its physical limitations, such as precision, noise, and bandwidth during fabrication. Moreover, the unique advantages of MNN's (e.g., light-speed computation) are not fully explored via standard 3×3 convolution kernels. In this paper, we propose a novel large kernel metamaterial neural network (LMNN) that maximizes the digital capacity of the state-of-the-art (SOTA) MNN with model re-parametrization and network compression, while also considering the optical limitation explicitly. The new digital learning scheme can maximize the learning capacity of MNN while modeling the physical restrictions of meta-optic. With the proposed LMNN, the computation cost of the convolutional front-end can be offloaded into fabricated optical hardware. The experimental results on two publicly available datasets demonstrate that the optimized hybrid design improved classification accuracy while reducing computational latency. The development of the proposed LMNN is a promising step towards the ultimate goal of energy-free and light-speed AI.

Dedicated Instruction Set for Pattern-Based Data Transfers: An Experimental Validation on Systems Containing In-Memory Computing Units

In-Memory Computing (IMC) aims at solving the performance gap between CPU and memories introduced by the memory wall. However, general-purpose IMC does not consider the optimization of data transfers for patterns such as stencils and convolutions. This paper proposes a new Instruction Set Architecture (ISA) and a novel pattern encoding for IMC to transfer and organize data streams in order to perform efficiently computation. This instruction set is implemented on the Data-locality Management Unit (DMU) as a subset of the Computational SRAM (C-SRAM) Instruction Set Architecture. A programming model to interact with the DMU at languagelevel is also presented in this paper. This DMU ISA is evaluated on six applications run on three different system nodes. These system nodes are based on existing RISC-V cores and range from embedded to high-performance computing domain. Experiments show on average a speed-up of W8.81, an energy reduction factor of W6.81 and an improvement of the number of operations per cycle of W4.59, for The C-SRAM architecture integrating the proposed ISA of the DMU compared to a reference implementation on embedded systems. Results also show an improvement of the number of operations per cycle of W2.99 compared to a reference implementation on all system nodes.

MDCIM: MRAM-Based Digital Computing-in-Memory Macro for Floating-Point Computation with High Energy Efficiency and Low Area Overhead

Computing-in-Memory (CIM) is a novel computing architecture that enormously improves energy efficiency and reduces computing latency by avoiding frequent data movement between the computation and memory units. Currently, digital CIM is regarded as more suitable for high-precision operations represented in floating-point arithmetic, as it is not limited by the bit width of ADC/DAC in analog CIM. However, the development of DCIM still faces two problems: On the one hand, mainstream SRAM-based DCIM memory cells introduce large area overheads, which contain at least six transistors per cell. On the other hand, existing DCIM solutions can only support the computing precision up to FP32, failing to meet the demands of high-accuracy application scenarios. To overcome these problems, this work designs a novel SOT-MRAM-based digital CIM macro (MDCIM) with higher area/energy efficiency and achieves double-precision floating-point (FP64) computation with a modified fused multiply–accumulate (FMA) module. The proposed design is synthesized with a 55 nm CMOS technology node, achieving 0.62 mW power consumption, 26.9 GOPS/W, and 0.332 GOPS/mm2 energy efficiency at 150 MHz with 1.08 V supply. Circuit level simulation results show that the MDCIM can achieve higher area utilization compared to previous SRAM-based CIM designs.

Efficient Hardware Implementation of Elliptic-Curve Diffie–Hellman Ephemeral on Curve25519

Hardware architecture optimized for implementing the elliptic-curve Diffie–Hellman ephemeral (ECDHE) on 256-bit Montgomery elliptic curves presents unique challenges, particularly for resource-constrained IoT and mobile devices. This work aims to provide an efficient hardware implementation of ECDHE on Curve25519, including a dedicated finite state machine (FSM) designed to handle point multiplication and ECDHE operations, utilizing constant-time algorithms and a unified memory block for resource management. Additionally, we introduce an optimized modular computation unit that covers modular addition, subtraction, multiplication, and inversion. Our proposed hardware architecture enhances the efficiency of ECDHE operations while maintaining low resource utilization, considerably reduced latency, and low power consumption. Synthesized on the Xilinx Artix-7 platform, our design boasts 64,000 Slices and a clock speed of 102 MHz, and it computes an ECDHE scalar multiplication operation in 1.1 ms, consuming 117 mW. The proposed hardware design can be applied to various platforms, including mobile devices and IoT systems.

Spin Qubit in a 2D GdIII NaI -Based Oxamato Supramolecular Coordination Framework.

Qubits are the basic unit of quantum information and computation. To realize quantum computing and information processing, the decoherence times of qubits must be long enough. Among the studies of molecule-based electron spin qubits, most of the work focused on the ions with the spin S=1/2, where only single-bit gates can be constructed. However, quantum operations require the qubits to interact with each other, so people gradually carry out relevant research in ions or systems with S>1/2 and multilevel states. In this work, a two-dimensional (2D) oxygen-coordinated GdIII NaI -based oxamato supramolecular coordination framework, Na[Gd(4-HOpa)4 (H2 O)] ⋅ 2H2 O (1, 4-HOpa=N-4-hydroxyphenyloxamate), was selected as a possible carrier of qubit. The field-induced slow magnetic relaxation shows this system has phonon bottleneck (PB) effect at low temperatures with a very weak magnetic anisotropy. The pulse electron paramagnetic resonance studies show the spin-lattice and spin-spin relaxation times are T1 =1.66 ms at 4 K and Tm =4.25 μs at 8 K for its diamagnetically diluted sample (1Gd0.12 %). It suggested that the relatively long decoherence time is mainly ascribed to its near isotropic and the PB effect from resonance phonon trapped for pure sample, while the dilution further improves its qubit performance.

The Role of Information Technology in Increasing the Effectiveness of Taxation at the Jakarta Kemayoran Pratama Tax Service Office

This study discusses the effectiveness of the use of Information Technology in improving the tax system at the Tax Office pratama jakarta kemayoran. The purpose of this study was to analyze the effectiveness of the use of Information Technology in improvin g the tax system at the Tax Office Pratama Jakarta Kemayoran, analyze the entity inhibiting the effectiveness of the use of Information Technology in improving the tax system at the Tax Office Pratama Jakarta Kemayoran and analyze the entity driving the effectiveness of the use of Information Technology in improving the tax system at the Tax Office Pratama Jakarta Kemayoran. The research methods used for this study are descriptive qualitative. Data collection using observation, interviews, and documentation. The results of this research for KPP Pratama Jakarta Kemayoran prepare the availability of computer units in accordance with service needs. It can be said that the effectiveness of the service is due to the availability of 7 units of computers and can be used by wp itself. the system and mechanism of taxpayer database storage is very confidential and only located at the DGT headquarters. to improve the effectiveness of taxation using several programs, software, and applications including: service TPT program, tax amnesty program, voluntary disclosure program (PPS), etc. The obstacles faced are from the taxation of this online system, because there are still taxpayers who do not understand the online system of taxation from the way it operates so that it can take time to learn things related to taxation. Efforts that can be done is to continue to improve performance, especially in terms of delivering comprehensive education and socialization so that taxpayers can know well the latest information, especially taxation.