Tree Compression Research Articles

Lossless Compression of Binary Trees with Correlated Vertex Names.

Compression schemes for advanced data structures have become a central modern challenge. Information theory has traditionally dealt with conventional data such as text, images, or video. In contrast, most data available today is multitype and context-dependent. To meet this challenge, we have recently initiated a systematic study of advanced data structures such as unlabeled graphs [8]. In this paper, we continue this program by considering trees with statistically correlated vertex names. Trees come in many forms, but here we deal with binary plane trees (where order of subtrees matters) and their non-plane version (where order of subtrees doesn't matter). Furthermore, we assume that each name is generated by a known memoryless source (horizontal independence), but a symbol of a vertex name depends in a Markovian sense on the corresponding symbol of the parent vertex name (vertical Markovian dependency). Such a model is closely connected to models of phylogenetic trees. While in general the problem of multimodal compression and associated analysis can be extremely complicated, we find that in this natural setting, both the entropy analysis and optimal compression are analytically tractable. We evaluate the entropy for both types of trees. For the plane case, with or without vertex names, we find that a simple two-stage compression scheme is both efficient and optimal. We then present efficient and optimal compression algorithms for the more complicated non-plane case.

An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks

Binary weight convolutional neural networks (BCNNs) can achieve near state-of-the-art classification accuracy and have far less computation complexity compared with traditional CNNs using high-precision weights. Due to their binary weights, BCNNs are well suited for vision-based Internet-of-Things systems being sensitive to power consumption. BCNNs make it possible to achieve very high throughput with moderate power dissipation. In this paper, an energy-efficient architecture for BCNNs is proposed. It fully exploits the binary weights and other hardware-friendly characteristics of BCNNs. A judicious processing schedule is proposed so that off-chip I/O access is minimized and activations are maximally reused. To significantly reduce the critical path delay, we introduce optimized compressor trees and approximate binary multipliers with two novel compensation schemes. The latter is able to save significant hardware resource, and almost no computation accuracy is compromised. Taking advantage of error resiliency of BCNNs, an innovative approximate adder is developed, which significantly reduces the silicon area and data path delay. Thorough error analysis and extensive experimental results on several data sets show that the approximate adders in the data path cause negligible accuracy loss. Moreover, algorithmic transformations for certain layers of BCNNs and a memory-efficient quantization scheme are incorporated to further reduce the energy cost and on-chip storage requirement. Finally, the proposed BCNN hardware architecture is implemented with the SMIC 130-nm technology. The postlayout results demonstrate that our design can achieve an energy efficiency over 2.0TOp/s/W when scaled to 65 nm, which is more than two times better than the prior art.

A compressed graph representation for services composition

Service-oriented computing enhances business scalability and flexibility. Providers who expect to benefit from it may bring the explosive growth of web services. As a result, the huge storage required in searching a composition solution may be too much to afford. In this paper, we apply a compressed data structure to tackle this challenging issue. We propose a system model to solves web service composition (WSC) problem. In this model, we use a compressed tree to represent the search graph. This work innovatively solve the composition problem with compressed graph representation. The proposed model is verified through theoretical analysis and experimental study. The obtained experimental results show that this system may handle a large number of web services with small space requirement.

Optical Emission Spectrum Processing Using Wavelet Compression During Wafer Fabrication

This paper describes the application of discrete-wavelet transform (DWT)-based algorithms to compress optical emission spectral intensity data collected during wafer fabrication. The major goal is to seek computationally efficient compression algorithms that can significantly reduce the data storage requirement but also are capable of retaining enough data authenticity critical for diagnostic purposes. The potential benefits will provide a promising foundation for an integrated data collection and compression tool. The optical emission data are treated in this paper either as images for the whole spectrum or bands of time series and are treated accordingly using appropriate DWT compression approaches. We have found through representative simulation examples that using the set partitioning in hierarchical trees compression algorithm it is achievable to obtain better than 99% storage reduction for optical emission spectrum (OES) images. For OES time series we have achieved around 95% storage reduction with Daubechies and Haar wavelets. The storage reductions are achieved while maintaining sufficient authenticity to retain the dynamic nature of OES data for diagnostic purposes.

Improved Synthesis of Generalized Parallel Counters on FPGAs Using Only LUTs

Generalized parallel counters (GPCs) are frequently used to construct high speed compressor trees on field programmable gate arrays (FPGAs). The introduction of fast carry-chain in FPGAs has greatly improved the performance of these elements. Evidently, a large number of GPCs have been proposed in literature that use a combination of look-up tables (LUTs) and carry-chains. In this paper, we take an alternate approach and try to eliminate the carry-chain from the GPC structure. We present a heuristic that aims at synthesizing GPCs on FPGAS using only the general LUT fabric. The resultant GPCs are then easily pipelined by placing registers at the output node of each LUT. We have used our heuristic on various GPCs reported in prior work. Our heuristic successfully eliminates the carry-chain from the GPC structure with an increase in LUT count in some GPCs. Experimentation using Xilinx FPGAs shows that filter systems constructed using our GPCs show an improvement in speed and power performance and a comparable area performance.

LUT Based Generalized Parallel Counters for State - of - art FPGAs

Generalized Parallel Counters (GPCs) are frequently used in constructing high speed compressor trees. Previous work has focused on achieving efficient mapping of GPCs on FPGAs by using a combination of general Look-up table (LUT) fabric and specialized fast carry chains. The resulting structures are purely combinational and cannot be efficiently pipelined to achieve the potential FPGA performance. In this paper, we take an alternate approach and try to eliminate the fast carry chain from the GPC structure. We present a heuristic that maps GPCs on FPGAS using only general LUT fabric. The resultant GPCs are then easily re-timed by placing registers at the fan-out nodes of each LUT. We have used our heuristic on various GPCs reported in prior work. Our heuristic successfully eliminates the carry chain from the GPC structure with the same LUT count in most of the cases. Experimental results using Xilinx Kintex-7 FPGAs show a considerable reduction in critical path and dynamic power dissipation with same area utilization in most of the cases.

Limited Carry-Propagate Multiply-Accumulate Unit Design for Reconfigurable Systems

Counter and compressor arrays are frequently employed in multiplier design to efficiently reduce partial products in VLSI design. On the other hand, in reconfigurable systems, fast carry chains boost the performance of carry-propagate adders. So that, in reconfigurable systems, to save logic element area, counter and compressor trees are not employed as much since they require more area than carry-propagate scheme. In this work, carry-propagate multi-operand adders are employed in smaller blocks and the outputs are merged using double carry-save encoding to increase performance in reconfigurable systems. Hence, a more compact structure is achieved, compared to full redundant partial product reduction scheme providing comparable speed performance with counter array based carry-save structure. To show the effectiveness of the implementation, fused multiply-accumulate (MAC) units are designed for various bit-widths. The structure is implemented on AlteraTM Stratix III and Cyclone III FPGAs and the results show that, using least depth of pipeline, the throughput is better than regular carry-propagate and fully redundant carry-save reduction schemes.DOI: http://dx.doi.org/10.5755/j01.eie.23.2.17997

High Performance Multi-Operand Adder for Medical Images

AbstractThe Internet of Things (IoT) gives a new path for future Internet through which it had boosted the growth in number of devices ranging from home automation to medical devices. Security in IoT is a research topic, which involves security for low memory footprint devices. Hence light weighted cryptographic algorithms plays a major role in providing data integrity for IoT devices. The term light weightiness begins from gate level to system level. Multi-operand addition, which is widely used in block ciphers and hash functions. This work presents different approaches for realization of highly efficient multi-operand addition for medical IoT field devices. The use of conventional adders in the multipliers for summation of the intermediate results leads to area and delay overhead. Multi-operand addition and compressor trees can be used more efficiently for decimal operations, which will reduce the delay without much overhead in area. The proposed approach is experimented with different multipliers for i...

Approximation of smallest linear tree grammar

A simple linear-time algorithm for constructing a linear context-free tree grammar of size O(rg+rglog⁡(n/rg)) for a given input tree T of size n is presented, where g is the size of a minimal linear context-free tree grammar for T, and r is the maximal rank of symbols in T (which is a constant in many applications). This is the first example of a grammar-based tree compression algorithm with a good, i.e. logarithmic in terms of the size of the input tree, approximation ratio. The analysis of the algorithm uses an extension of the recompression technique from strings to trees.

An efficient approach towards compressed parameterized word matching using wavelet tree

Parameterized matching is said to exist between two strings, if either string is convertible to another using any bijective mapping. It is applicable in various fields such as: detecting isomorphism in graphs, plagiarism detection, software maintenance, molecular biology and image processing. Compressed parameterized matching performs matching on text and pattern both in compressed form without decompressing any one of them. Compressing the text gives the advantage of reduced saving space and reduction in execution time. This paper presents an algorithm that tries to optimize parameterized word matching on compressed domain. The proposed algorithm uses Word Based Tagged Code (WBTC) for compression and Wavelet tree for efficient searching. Major advantage of the algorithm is that it does not require any additional verification process unlike in existing algorithms. The proposed algorithm has better execution time also.

Energy-efficient Compressed Sensing for ambulatory ECG monitoring

Advances in Compressed Sensing (CS) are enabling promising low-energy implementation solutions for wireless Body Area Networks (BAN). While studies demonstrate the potential of CS in terms of overall energy efficiency compared to state-of-the-art lossy compression techniques, the performance of CS remains limited. The aim of this study is to improve the performance of CS-based compression for electrocardiogram (ECG) signals. This paper proposes a CS architecture that combines a novel redundancy removal scheme with quantization and Huffman entropy coding to effectively extend the Compression Ratio (CR). Reconstruction is performed using overcomplete sparse dictionaries created with Dictionary Learning (DL) techniques to exploit the highly structured nature of ECG signals. Performance of the proposed CS implementation is evaluated by analyzing energy-based distortion metrics and diagnostic metrics including QRS beat-detection accuracy across a range of CRs. The proposed CS approach offers superior performance to the most recent state-of-the-art CS implementations in terms of signal reconstruction quality across all CRs tested. Furthermore, QRS detection accuracy of the technique is compared with the well-known lossy Set Partitioning in Hierarchical Trees (SPIHT) compression technique. The proposed CS approach outperforms SPIHT in terms of achievable CR, using the area under the receiver operator characteristic (ROC) curve (AUC). For an application where a minimum AUC performance threshold of 0.9 is required, the proposed technique extends the CR from 64.6 to 90.45 compared with SPIHT, ensuring a 40% saving on wireless transmission costs. Therefore, the results highlight the potential of the proposed technique for ECG computer-aided diagnostic systems.

Secure image deduplication through image compression

Cloud technology has empowered its users with remarkable expediency in terms of unlimited storage, accessibility, and availability of data. It has also contributed to the tremendous growth of digital data. To encounter this frenziedly growth, data deduplication has become a central approach for Cloud Storage Providers (CSPs) since it allows them to remove the identical data from their storages successfully. Currently, images are among the most common shared types of data found on cloud storages, and they are a good candidate for deduplication. In this paper, a novel compression scheme is proposed that achieves a secure deduplication of images in the cloud storages. Its design consists of embedding a partial encryption and a unique image hashing into the Set Partitioning In Hierarchical Trees (SPIHT) compression algorithm. The partial encryption scheme is meant to ensure the security of the proposed scheme against a semi honest CSP whereas the image hashing scheme is meant for classifying the identical compressed and encrypted images so that deduplication can be performed on them, resulting to a secure deduplication strategy with no extra computational overhead incurred for image encryption, hashing and deduplication. Experimental results and security analysis are provided to validate the stated goals.

Algorithmic height compression of unordered trees

By nature, tree structures frequently present similarities between their sub-parts. Making use of this redundancy, different types of tree compression techniques have been designed in the literature to reduce the complexity of tree structures. A popular and efficient way to compress a tree consists of merging its isomorphic subtrees, which produces a directed acyclic graph (DAG) equivalent to the original tree. An important property of this method is that the compressed structure (i.e. the DAG) has the same height as the original tree, thus limiting partially the possibility of compression. In this paper we address the problem of further compressing this DAG in height. The difficulty is that compression must be carried out on substructures that are not exactly isomorphic as they are strictly nested within each-other. We thus introduced a notion of quasi-isomorphism between subtrees that makes it possible to define similar patterns along any given path in a tree. We then proposed an algorithm to detect these patterns and to merge them, thus leading to compressed structures corresponding to DAGs augmented with return edges. In this way, redundant information is removed from the original tree in both width and height, thus achieving minimal structural compression. The complete compression algorithm is then illustrated on the compression of various plant-like structures.

Implementation of Fast Radix-10 BCD Multiplier in FPGA

Background: Multiplication is the basic operation in any signal processing systems and financial applications, all these applications requires multiplication to be performed in a faster and efficient manner on a silicon chip. Methods: This paper describes the algorithm and architecture of a BCD parallel multiplier. The design exploits two properties of redundant BCD codes to speed up its computation. Namely, the redundant BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In addition to this, number of new techniques are used in order to reduce significantly latency, area and for implementation on FPGA compared to existing implementations. Findings: Parallel architecture is used for generating partial products using radix-10 recoding technique for signed-digit of a BCD multiplier having set of digits between the range [–5, 5] and a positive set of multiplicand multiples coded in XS-3. Use of this encoding has various advantages like, as XS-3 is a self-complementing code, finding a negative of it is by just complementing the bits of respective number. Also the redundancy in XS-3 code is utilized for generating multiplicand multiples in a simple, faster and a carry-free way. Implemented design has three stages. Partial product generation, reduction and final conversion to BCD. For to implement the design in hardware the partial product reduction architecture is modified here to use a bank of ripple carry adder trees. ODDS representation uses 4-bit binary encoding technique which is similar to non-redundant BCD code, for this reason conventional VLSI circuit techniques such as carry-save adders and compression trees can be used effectively to perform operations on decimal numbers. Conclusion: To show the advantages of the resulted design, RTL model for 8 × 8-digit and 16 × 16-digits multiplication has been synthesized and implemented in Virtex-5 FPGA device. Results shows that the multiplier is about 10–15% delay efficient with existing work and about 14–18% area efficient.

Tree compression with top trees

We introduce a new compression scheme for labeled trees based on top trees. Our compression scheme is the first to simultaneously take advantage of internal repeats in the tree (as opposed to the classical DAG compression that only exploits rooted subtree repeats) while also supporting fast navigational queries directly on the compressed representation. We show that the new compression scheme achieves close to optimal worst-case compression, can compress exponentially better than DAG compression, is never much worse than DAG compression, and supports navigational queries in logarithmic time.

High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs

Generalized parallel counters (GPCs) are used in constructing high speed compressor trees. Prior work has focused on utilizing the fast carry chain and mapping the logic onto Look-Up Tables (LUTs). This mapping is not optimal in the sense that the LUT fabric is not fully utilized. This results in low efficiency GPCs. In this work, we present a heuristic that efficiently maps the GPC logic onto the LUT fabric. We have used our heuristic on various GPCs and have achieved an improvement in efficiency ranging from 33% to 100% in most of the cases. Experimental results using Xilinx 5th-, 6th-, and 7th-generation FPGAs and Stratix IV and V devices from Altera show a considerable reduction in resources utilization and dynamic power dissipation, for almost the same critical path delay. We have also implemented GPC-based FIR filters on 7th-generation Xilinx FPGAs using our proposed heuristic and compared their performance against conventional implementations. Implementations based on our heuristic show improved performance. Comparisons are also made against filters based on integrated DSP blocks and inherent IP cores from Xilinx. The results show that the proposed heuristic provides performance that is comparable to the structures based on these specialized resources.

TreeTalk: Composition and Compression of Trees for Image Descriptions

We present a new tree based approach to composing expressive image descriptions that makes use of naturally occuring web images with captions. We investigate two related tasks: image caption generalization and generation, where the former is an optional subtask of the latter. The high-level idea of our approach is to harvest expressive phrases (as tree fragments) from existing image descriptions, then to compose a new description by selectively combining the extracted (and optionally pruned) tree fragments. Key algorithmic components are tree composition and compression, both integrating tree structure with sequence structure. Our proposed system attains significantly better performance than previous approaches for both image caption generalization and generation. In addition, our work is the first to show the empirical benefit of automatically generalized captions for composing natural image descriptions.

Extremely Low Bit-Rate Nearest Neighbor Search Using a Set Compression Tree.

The goal of this work is a data structure to support approximate nearest neighbor search on very large scale sets of vector descriptors. The criteria we wish to optimize are: (i) that the memory footprint of the representation should be very small (so that it fits into main memory); and (ii) that the approximation of the original vectors should be accurate. We introduce a novel encoding method, named a Set Compression Tree (SCT), that satisfies these criteria. It is able to accurately compress 1 million descriptors using only a few bits per descriptor. The large compression rate is achieved by not compressing on a per-descriptor basis, but instead by compressing the set of descriptors jointly. We describe the encoding, decoding and use for nearest neighbor search, all of which are quite straightforward to implement. The method, tested on standard benchmarks (SIFT1M and 80 Million Tiny Images), achieves superior performance to a number of state-of-the-art approaches, including Product Quantization, Locality Sensitive Hashing, Spectral Hashing, and Iterative Quantization. For example, SCT has a lower error using 5 bits than any of the other approaches, even when they use 16 or more bits per descriptor. We also include a comparison of all the above methods on the standard benchmarks.

Research on a frequent maximal induced subtrees mining method based on the compression tree sequence

Most complex data structures can be represented by a tree or graph structure, but tree structure mining is easier than graph structure mining. With the extensive application of semi-structured data, frequent tree pattern mining has become a hot topic. This paper proposes a compression tree sequence (CTS) to construct a compression tree model; and save the information of the original tree in the compression tree. As any subsequence of the CTS corresponds to a subtree of the original tree, it is efficient for mining subtrees. Furthermore, this paper proposes a frequent maximal induced subtrees mining method based on the compression tree sequence, CFMIS (compressed frequent maximal induced subtrees). The algorithm is primarily performed via four stages: firstly, the original data set is constructed as a compression tree model; then, a cut-edge reprocess is run for the edges in which the edge frequent is less than the threshold; next, the tree is compressed after the cut-edge based on the different frequent edge degrees; and, last, frequent subtree sets maximal processing is run such that, we can obtain the frequent maximal induced subtree set of the original data set. For each iteration, compression can reduce the size of the data set, thus, the traversal speed is faster than that of other algorithms. Experiments demonstrate that our algorithm can mine more frequent maximal induced subtrees in less time.

Fast Radix-10 Multiplication Using Redundant BCD Codes

We present the algorithm and architecture of a BCD parallel multiplier that exploits some properties of two different redundant BCD codes to speedup its computation: the redundant BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In addition, new techniques are developed to reduce significantly the latency and area of previous representative high-performance implementations. Partial products are generated in parallel using a signed-digit radix-10 recoding of the BCD multiplier with the digit set [-5, 5], and a set of positive multiplicand multiples (0X, 1X, 2X, 3X, 4X, 5X) coded in XS-3. This encoding has several advantages. First, it is a self-complementing code, so that a negative multiplicand multiple can be obtained by just inverting the bits of the corresponding positive one. Also, the available redundancy allows a fast and simple generation of multiplicand multiples in a carry-free way. Finally, the partial products can be recoded to the ODDS representation by just adding a constant factor into the partial product reduction tree. Since the ODDS uses a similar 4-bit binary encoding as non-redundant BCD, conventional binary VLSI circuit techniques, such as binary carry-save adders and compressor trees, can be adapted efficiently to perform decimal operations. To show the advantages of our architecture, we have synthesized a RTL model for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math>$16\times 16$</tex-math></inline-formula> -digit and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math>$34\times 34$</tex-math></inline-formula> -digit multiplications and performed a comparative survey of the previous most representative designs. We show that the proposed decimal multiplier has an area improvement roughly in the range 20-35 percent for similar target delays with respect to the fastest implementation.