Compressor Circuit Research Articles

Energy Efficient Compressor Cell for Low Power Computing

As the use of multimedia devices is rising, power management is becoming a major challenge. Various types of compressors have been designed in this study. Compressor circuits are designed using several circuits of XOR-XNOR gates and multiplexers. XOR-XNOR gate combinations and multiplexer circuits have been used to construct the suggested compressor design. The performance of the proposed compressor circuits using these low-power XOR-XNOR gates and multiplexer blocks has been found to be economical in terms of space and power. This study proposes low-power and high-speed 3-2, 4-2, and 5-2 compressors for digital signal processing applications. A new compressor has also been proposed that is faster and uses less energy than the traditional compressor. The full adder circuit, constructed using various combinations of XOR-XNOR gates, has been used to develop the proposed compressor. The proposed 3-2 compressor shows average power dissipation 571.7 nW and average delay 2.41 nS, 4-2 compressor shows average power dissipation 1235 nW and average delay 2.7 nS while 5-2 compressor shows average power dissipation 2973.50 nW and average delay 3.75 nS.

Booth Multiplier Based on Low Power High Speed Full Adder With Fin_FET Technology

This paper proposes a novel Fin FET-based HSFA for the multiplier in order to overcome the issues of low speed operation. It is advantageous to use Fin FETs to construct the arithmetic circuit while assessing the available works. The carry propagation and slow operation of the old technique are disadvantages. The CMOS-based compressor circuit, on the other hand, suffers from leakage current, which reduces its driving capabilities. High current DSP applications are well matched to the design's specifications. Even with a supply voltage of 1 volt, the proposed device has a decent driving capability. As a result, the circuit runs more quickly and has less latency. A transmission gate is used in the design of the suggested adder structure to selectively block or transfer data from the input to output. Half adder and adder are shown in the following illustrations. The smaller the transistor count, the less power it uses. The suggested Fin FET design for the smaller transistors has a superior driving capability than the CMOS equivalent. Additionally, when cascading, the Fin FET based adder may contribute to superior switch performance, such as when using ripple carry adder. There is also the possibility of a low operation, which may operate at Low wattage Electronic designs for high-performance and small devices have become increasingly dependent on the use of VLSI circuits. The power of a processor is determined in large part by the multiplier used in its design. Multiplier factor booth coding is being used to reorder the input bits in order to reduce facility use. The booth decoder works by rearranging the specified booth equivalent. The Booth decoder has the ability to expand the range of zeros. As a result, the power consumption of the design will be decreased even more. As soon as the input bit constant drops below zero, related rows or columns of an adder must be disabled, if possible.

Air Drying in an Industrial Compressor

In many industrial applications where compressed air is used it is necessary to increase the quality of the air by decreasing its humidity. This is done by either a condensation or adsorption dryer in the compressor circuit. In this article, the focus is on an industrial adsorption air dryer. The dryer is briefly described together with its function and a selected range of adsorbents suitable for air drying. The paper further deals with the development of a mathematical model of air humidity adsorption which is based on the Pseudo Gas-side Controlled (PGC) model. This paper contains a detailed description of the model and describes its implementation in MATLAB. Finally, the results of the simulations are discussed.

Dynamic Evaluation: Centrifugal Compressor’s Operation in Determining Anti-Surge Controller

Anti-surging is developed for a compressor system consisting of a booster compressor and a high-pressure compressor in a serial circuit. This evaluation presented 6 options of anti-surge systems with variations of the number of Anti-surge Valve (ASV) and its combination with the addition of a Hot Gas Bypass Valve (HGBV) and Cold Gas Bypass Valve (CGBV). From the model evaluation, the option that involves a special ASV (dedicated) for each compressor and coupled with a dedicated CGBV or HGBV is the best because the compressor can be back to normal in less than 1 second (maximum time to return to normal condition is 3 seconds. Referring to these options, a dedicated ASV for each compressor provides more benefits to the security of compressor operation. However, the most appropriate option in the field will return to the issue of cost or ease of modification. For facilities that are running (brownfield), the use of tools that already exist in the field and do a little modification is the most appropriate option, while for the new facility (grassroots project), the single ASV for a compressor circuit is the most optimum as it only involves minimum equipment and configuration as simple as possible piping/instrumentation.

Efficient partial product reduction for image processing application using approximate 4:2 compressor

PurposeThis paper aims to improve the performance of approximate multiplier in terms of peak signal to noise ratio (PSNR) and quality of the image.Design/methodology/approachThe paper proposes an approximate circuit for 4:2 compressor, which shows a significant amount of improvement in performance metrics than that of the existing designs. This paper also reports a hybrid architecture for the Dadda multiplier, which incorporates proposed 4:2 compressor circuit as a basic building block.FindingsHybrid Dadda multiplier architecture is used in a median filter for image de-noising application and achieved 20% more PSNR than that of the best available designs.Originality/valueThe proposed 4:2 compressor improves the error metrics of a Hybrid Dadda multiplier.

An efficient VLSI architecture of 2‐D finite impulse response filter using enhanced approximate compressor circuits

AbstractThe very large‐scale integration (VLSI) design‐based architectures of 2‐D filters must have low power consumption and high speed rather than accuracy for image processing applications. The inexact computations reduce the delay, area, and power in arithmetic architectures, and utilizing this advantage an approximation can be introduced in 2‐D digital filters. In this work, circular symmetry is adopted to optimize the 2‐D finite impulse response (FIR) filter architecture, and it is implemented using imprecise multipliers and approximate compressors with acceptable accuracy. The exact 4:2 compressor is modified into an approximate 4:2 compressor by ignoring few inputs. Hence, hardware requirement and delay parameters are improved. The proposed compressor is designed by mixed logic rather than complete complementary metal‐oxide semiconductor (CMOS) logic. The dual value logic (DVL), transmission gate logic (TGL), and CMOS mixed logic gates are used to decrease the number of transistors in the circuits. The proposed compressors are used in the approximate Dadda multiplier (ADM). The ADMs are utilized to implement the 2‐D FIR filter architecture. The designed filter is coded in Verilog and implemented using field programmable gate array (FPGA). The hardware utilization is analyzed and compared with exact 2‐D FIR filters. Next, the proposed architecture is synthesized using Cadence genus tools, and physical design is carried out by Cadence Innovus tools in 45‐nm CMOS technology. The final physical design layout‐area, power, and delay reports are correlated with existing state‐of‐artworks. It is found that the proposed 2‐D FIR filter outperforms the existing works.

Compressor based approximate multiplier architectures for media processing applications

Approximate computing is an attractive technique to gain substantial improvement in the area, speed, and power in applications where exact computation is not required. This paper proposes two improved multiplier designs based on a new 4:2 approximate compressor circuit to simplify the hardware at the partial product reduction stage. The proposed multiplier designs are targeted towards error-tolerant applications. Exhaustive error and hardware analysis has been carried out on the existing and proposed multiplier designs. The results prove that the proposed approximate multiplier architecture performs better than the existing architectures without significant compromise on quality metrics. Experimental results show that die-area and power consumed are reduced upto 28%, and 25.29% respectively in comparison with the existing designs without significant compromise on accuracy.

The nonlinear effect in the performance of 4:2 Compressor

In this article, we have designed a novel 4:2 QCA Compressor with a nonlinear effect. This can be considered as a new vision to design approximate Majority circuits with more than five-input. The main advantages of these ideas are the reduced number of QCA cells as well as power dissipation, increased speed, and improved cell area In addition, a novel hierarchy is introduced to optimize digital systems. The 4:2 Compressor circuit is selected as a benchmark. This circuit is simulated with some technologies such as CMOS, CNT, and QCA in different architectures. All results from power respective were compared. We have used QCADesigner and QCAPro for QCA Circuits, Hspice with 20nm-nfet PTM-MG model for CMOS circuits and Stanford CNFET 20nm model for CNT circuits as simulation tools to evaluate circuits.

Accuracy evaluation of a trained neural network by energy efficient approximate 4:2 compressor

Automation techniques and machine learning algorithms are playing a crucial role in almost all fields in recent times. In this research, a 4:2 compressor circuit is approximated using the probabilistic pruning technique. An artificial neural network is designed for the proposed 4:2 compressor and is trained to obtain the train and test accuracies. The neural network with equal train and test accuracies has been considered as the best approximate circuit. The training of the neural network has been performed using a supervised machine learning algorithm by applying truth table of the proposed approximate 4:2 compressor as the dataset. The proposed compressor has only 19 transistors and consumes less energy i.e.,0.2015 nJ with less silicon area of 14.36 um2. The performance of the Dadda multiplier is improved by replacing the proposed approximate 4:2 compressor into its partial product reduction stage.

Hardware-efficient approximate multiplier architectures for media processing applications

PurposeMultipliers that form the basic building blocks in most of the error-resilient media processing applications are computationally intensive and power-hungry modules. Therefore, improving the multiplier’s performance in terms of area, critical path delay and power has become an important research area. This paper aims to propose two improved multiplier designs based on a new approximate compressor circuit to reduce the hardware complexity at the partial product reduction stage. The proposed approximate 4:2 compressor design significantly reduces the overall hardware cost of the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure.Design/methodology/approachThe multiplier designs implemented using the proposed approximate 4:2 compressor are targeted for error-resilient applications. For fair comparisons, various multiplier designs, including the proposed one, are implemented in MATLAB. The quality analysis is carried out using standard images, and metrics such as structural similarity index are computed to quantify the result of proposed designs with the existing architectures. Next, Verilog gate-level designs are synthesized to compute area, delay and power to prove the efficacy of the proposed designs.FindingsExhaustive error and hardware analysis have been carried out for the existing and proposed multiplier architectures. Error analysis carried out using MATLAB proves that the proposed designs achieve better quality metrics than existing designs. Hardware results show that area, the power consumed and critical path delay are reduced up to 39.8%, 51.7% and 15.9%, respectively, compared to the existing designs. Toward the end, the proposed designs impact is quantified and compared with existing designs on real-time image sharpening and image multiplication applications.Originality/valueThe area, delay and power metrics of the multiplier can be improved using an approximate compressor in an error-resilient application. Accordingly, in this work, a new compressor is proposed that reduces the hardware complexity in the multiplier architecture. However, the proposed approximate compressor, while reducing the computational complexity, tends to introduce error in the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure. With the help of the approximate compressor and a technique of input realignment, hardware efficient and highly accurate multiplier designs are achieved.

Designing a New 4:2 Compressor Using an Efficient Multi-Layer Full-Adder Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is novel prominent nanotechnology. It promises a substitution to Complementary Metal–Oxide–Semiconductor (CMOS) technology with a higher scale integration, smaller size, faster speed, higher switching frequency, and lower power consumption. It also causes digital circuits to be schematized with incredible velocity and density. The full adder, compressor, and multiplier circuits are the basic units in the QCA technology. Compressors are an important class of arithmetic circuits, and researchers can use quantum compressors in the structure of complex systems. In this paper, first, a novel three-input multi-layer full-adder in QCA technology is designed, and based on it, a new multi-layer 4:2 compressor is presented. The proposed QCA-based full-adder and compressor uses an XOR gate. The proposed design offers good performance regarding the delay, area size, and cell number comparing to the existing ones. Also, in this gate, the output signal is not enclosed, and we can use it easily. The accuracy of the suggested circuits has been assessed with the utilization of QCADesigner 2.0.3. The results show that the proposed 4:2 compressor architecture utilizes 75 cell and 1.25 clock phases, which are efficient than other designs.

Performance Analysis of 5:2 compressor with 58 transistors

In the present generation of VLSI domain, designing a circuit with less power, area, and delay has become challenge for every designer. In this article we have design and implemented a design for 5:2 compressor which is the vital component in CMOS multiplier circuits. The proposed compressor circuit design requires less transistor count i.e. 58 transistors. The Simulation results of proposed 5:2 compressor has substantially expanded the performance of power delay in contrast to earlier designs.

Efficient Ternary Compressor Design Using Capacitive Threshold Logic in CNTFET Technology

Ternary logic is a promising alternative to classical binary logic as it offers the benefits of reduced interconnect, higher operating speed and smaller chip area. In this paper, a new approach is proposed to implement the 3–2 compressor and 4–2 compressor circuits using the futuristic carbon nanotube field-effect transistors (CNTFET). A CNTFET unique feature of geometry dependent threshold variation is utilized in threshold detector circuits which have been used to perform ternary to binary conversion. The high power consumption of capacitive based designs is reduced by minimizing the occurrence of voltage division by performing intermediate processing on binary literals rather than performing the computation directly on ternary signals. It exploits the combination of ternary logic and binary logic design technique to achieve enhanced performance. The proposed compressor designs are examined exhaustively using the Synopsys HSPICE simulator with 32 nm Stanford CNTFET model under various test conditions such as different supply voltages, temperatures, load capacitors, and operational frequencies. The simulation results indicate the superiority of the proposed design in terms of power and power delay product as compared to earlier reported designs.

Design of 9:2 compressor using FinFET

Multiplier is an essential component that is used commonly in any digital circuits. In general, for any digital circuits, multipliers occupy larger area; have long latency and their power consumption is more. Thereby, enhancing the performance of multipliers is quite important. Compressors are used to reduce the partial products so that the improved performance of multipliers can be achieved. In this paper, a new structure of 9:2 compressor is proposed in which the circuit is implemented with different combinations of 3:2, 4:2, 5:2 and 6:2 compressors. In this work, instead of bulk CMOS technology, circuits are implemented using FINFETs as they provide better gate control property, lower short channel effects. All the compressor circuits have been implemented using Cadence Virtuoso Simulator with FINFET 32nm technology. All the circuits are implemented to analyze the performance in terms of power, delay and transistor count.

Stability of the 7-3 Compressor Circuit for Wallace Tree. Part I

Summary To evaluate our formal verification method on a real-size calculation circuit, in this article, we continue to formalize the concept of the 7-3 Compressor (STC) Circuit [6] for Wallace Tree [11], to define the structures of calculation units for a very fast multiplication algorithm for VLSI implementation [10]. We define the circuit structure of the tree constructions of the Generalized Full Adder Circuits (GFAs). We then successfully prove its circuit stability of the calculation outputs after four and six steps. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability, and to implement the applications of the reliable logic synthesizer and hardware compiler [5].

A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication

Approximate computing is an emerging approach for reducing the energy consumption and design complexity in many applications where accuracy is not a crucial necessity. In this study, ultra-efficient imprecise 4:2 compressor and multiplier circuits as the building blocks of the approximate computing systems are proposed. The proposed compressor uses only one majority gate which is different from the conventional design methods using AND - OR and XOR logics. Furthermore, the majority gate is the fundamental logic block in many of the emerging majority-friendly nanotechnologies such as quantum-dot cellular automata ( QCA ) and single-electron transistor ( SET ). The proposed circuits are designed using FinFET as a current industrial technology and are simulated with HSPICE at 7nm technology node. The results indicate that our imprecise compressor is superior to its previous counterparts in terms of delay, power consumption, power delay product (PDP) and area, and improves these parameters on average by 32%, 68%, 78%, and 66%, respectively. In addition, the proposed efficient approximate multiplier is utilized in image multiplying as an important image processing application. The HSPICE and MATLAB simulations indicate that the proposed inexact multiplier provides a significant compromise between accuracy and design efficiency for approximate computing.

High-Performance Low-Power 5:2 Compressor With 30 CNTFETs Using 32 nm Technology

Background: The advent of High Performance Computing (HPC) applications and big data applications has made it imparitive to develop hardware that can match the computing demands. In such high performance systems, the high speed multipliers are the most sought after components. A compressor is an important part of the multiplier; it plays a vital role in the performance of multiplier, also it contributes to the efficiency enhancement of an arithmetic circuit. The 5:2 compressor circuit design proposed here improves overall performance and efficiency of the arithmetic circuits in terms of power consumption, delay and power delay product. The proposed 5:2 compressor circuit was implemented using both CMOS and Carbon Nano Tube Field Effect Transistor (CNTFET) technologies and it was observed that the proposed circuit has yielded better results with CNTFETs as compared to MOSFETs. Methods/Results: The proposed 5:2 compressor circuit was designed with CMOS technology simulated at 45 nm with voltage supply 1.0 V and compared it with the existing 5:2 compressor designes to validate the improvements. Thereafter, the proposed design was implemented with CNTFET technology at 32 nm and simulated with voltage supply 0.6 V. The comparision results of proposed 5:2 compressor with existing designs implemented using CMOS. The results also compare the proposed design on CMOS and CNTFET technologies for parameters like power, delay, power delay product. Conclusion: It can be concluded that the proposed 5:2 compressor gives better results as compared to the existing 5:2 compressor designs implemeted using CMOS. The improvement in power, delay and power delay product is approx 30%, 15% and 40% respectively. The proposed circuit of 5:2 compressor is also implemented using CNTFET technology and compared, which further enhances the results by 30% (power consumption and PDP). Hence, the proposed circuit implemented using CNTFET gives substantial improvements over the existing circuits.

Design and Implementation of Compressor based 32-bit Multipliers for MAC Architecture

Arithmetic operations play a major role in digital circuit design like adders, multipliers etc. Multiplication is an important fundamental arithmetic operation in high performance systems such as microprocessor and digital signal processors circuits. Implementation of multipliers using compressor circuit over conventional adders will reduce the number of levels of addition, which will in turn reduces the latency of the multiplier. Multiplier module is most likely the essential part of MAC (Multiplier-Accumulator) unit design. Compressor based multipliers in MAC architecture design results high performance. FPGA and ASIC implementations of 4:2 compressor based 32-bit Wallace and Dadda multipliers can be done by using Xilinx Vivado and Cadence CMOS technology tools. These results are compared with other multiplier designs with respect to area, latency and power dissipation.

Design and Analysis of MCML Carry Circuit with and without Sleep Transistor for Compressor Circuit Applications

Design and Analysis of MCML Carry Circuit with and without Sleep Transistor for Compressor Circuit Applications

Design of New Multi-Column 5,5:4 Compressor Circuit Based on Double-Gate UTBSOI Transistors

Abstract In the modern electronic devices, compressor circuits are used to speed up the partial product addition (PPA) stage in the multipliers. This paper presents an architecture of multi-column 5,5:4 compressor whose new transistor level implementation has been carried out through the ultra-thin-body silicon-on-insulator (UTBSOI) transistors. Such compressor has been simulated in Cadence-spectre, and the performance parameters like power consumption and delay has been calculated at the rising and falling edge transition of input pulses. Advantage of the UTBSOI-compressor is further clarified from its comparison with the CMOS based design (CMOS-compressor). Simulation results reveal that the PDP exhibited by the UTBSOI-compressor is reduced by 79.89% than that of CMOS counterparts. Furthermore, to showcase the advantage of such compressor, it has been applied in the multiplier for PPA which offers ≈11.5% improvement in terms of power-delay-product (PDP) in the Virtex 6 platform.