Efficient Ternary Compressor Design Using Capacitive Threshold Logic in CNTFET Technology

Abstract

Ternary logic is a promising alternative to classical binary logic as it offers the benefits of reduced interconnect, higher operating speed and smaller chip area. In this paper, a new approach is proposed to implement the 3–2 compressor and 4–2 compressor circuits using the futuristic carbon nanotube field-effect transistors (CNTFET). A CNTFET unique feature of geometry dependent threshold variation is utilized in threshold detector circuits which have been used to perform ternary to binary conversion. The high power consumption of capacitive based designs is reduced by minimizing the occurrence of voltage division by performing intermediate processing on binary literals rather than performing the computation directly on ternary signals. It exploits the combination of ternary logic and binary logic design technique to achieve enhanced performance. The proposed compressor designs are examined exhaustively using the Synopsys HSPICE simulator with 32 nm Stanford CNTFET model under various test conditions such as different supply voltages, temperatures, load capacitors, and operational frequencies. The simulation results indicate the superiority of the proposed design in terms of power and power delay product as compared to earlier reported designs.