Design of a High Performance Carry Generation Circuit for Ternary Full Adder Using CNTFET

Abstract

The Full Adder is one of the most important and basic units of arithmetic logics which is used to design many complex circuits. Further, ternary logic is a promising alternative to the conventional binary logic in VLSI design as it provides the advantages of reduced interconnects, higher operating speeds and smaller chip area. The present work aims to design high performance ternary full adder (TFA) by using carbon nanotube field effect transistors (CNTFET). The proposed TFA designs were simulated using HSPICE to obtain critical delay, power delay product (PDP) and maximum operating frequency. Further the circuit performance also has been compared with recently reported TFA. The factors which are considered for comparison are transistor count, delay, PDP and maximum operating frequency. The comparison results infer that the proposed TFA gives outstanding performance as compared to the reported one. The proposed TFA has been demonstrated delay, PDP and maximum operating frequency improvement up to 29%, 20% and 39% respectively. The transistor counts for the proposed circuits are also reduced by almost 15%.