Complex Matrix Multiplication Research Articles

Developing a Static Kinematic Model for Continuum Robots Using Dual Quaternions for Efficient Attitude and Trajectory Planning

Kinematic modeling is essential for planning and controlling continuum robot motion. The traditional Denavit Hartenberg (DH) model involves complex matrix multiplication operations, resulting in computationally intensive inverse solutions and trajectory planning. Solving position and orientation changes in continuum robots using the double quaternion rule can reduce computational complexity. However, existing dual quaternion methods are direct equational transformations of DH rules and do not give a complete modeling process. They usually require more interpretability when applying continuum robot kinematic modeling. This paper uses the dual quaternion method to establish a kinematic model of a continuum robot. It uses a two-section continuum robot model to compare the advantages of dual quaternion and traditional modeling methods. In addition, this paper proposes a five-polynomial interpolation algorithm based on the dual quaternion method for trajectory planning of continuum robots. This method accurately models spatial bending and torsional motions of singularity-free continuum robots.

Performance analysis of compressive sensing and reconstruction by LASSO and OMP for audio signal processing applications

Audio signal processing is used in acoustic IoT sensor nodes which have limitations in data storage, computation speed, hardware size and power. In most audio signal processing systems, the recovered data constitutes far less fraction of the sampled data providing scope for compressive sensing (CS) as an efficient way for sampling and signal recovery. Compressive sensing is a signal processing technique in which a sparse approximated signal is reconstructed at the receiving node by a signal recovery algorithm, using fewer samples compared to traditional sampling methods. It has two main stages: sparse approximation to convert the signal into a sparse domain and reconstruction through sparse signal recovery algorithms. Recovery algorithms involve complex matrix multiplication and linear equations in sampling and reconstruction, increasing the computational complexity and leading to highly resourceful hardware implementations. This work reconstructs the sparse audio signal using LASSO and orthogonal matching pursuit (OMP) algorithm. OMP is an iterative greedy algorithm involving least square method that takes a compressed signal as input and recovers it from the sparse approximation, while LASSO is L1 norm based with a controlled L2 penalty. The paper reviews the reconstruction and study of sparsity and error obtained for reconstructing an audio signal by OMP and LASSO.

Dynamic Synchrophasor Estimation Based on Weighted Real-Valued Sinc Interpolation Method

Phasor measurement units (PMUs) are the cornerstone of intelligent sensing and monitoring of power systems. The superiority of the sinc interpolation function-based least squares (SLS) method, a signal processing algorithm for PMUs, has been proven in harmonic phasor estimation. However, the SLS-based estimators suffer from spectral interferences and heavy computational burden. To this end, a real-valued sinc weighted least squares (SWLS-R) method is proposed to track the dynamic synchrophasor accurately and quickly. First, the weighted vector, i.e., window function, is introduced to enhance the SLS estimator’s behavior by mitigating the impact of spectral interference. Then, the complex-valued system matrix is transformed into the real-valued system matrix to lower the computational burden by avoiding complex matrix multiplication. Finally, an explicit and fast solution is designed to calculate the pseudoinverse matrix of the SWLS-R, which aims to further improve computational efficiency. The accuracy and effectiveness of the proposed method are validated by simulations. These are designed, under steady and dynamic conditions, according to the M-class requirements of the Standard IEC/IEEE 60255-118-1.

A high-performance two-dimensional transform architecture of variable block sizes for the VVC standard.

The versatile video coding standard H.266/VVC release has been accompanied with various new contributions to improve the coding efficiency beyond the high-efficiency video coding (HEVC), particularly in the transformation process. The adaptive multiple transform (AMT) is one of the new tools that was introduced in the transform module. It involves five transform types from the discrete cosine transform/discrete sine transform families with larger block sizes. The DCT-II has a fast computing algorithm, while the DST-VII relies on a complex matrix multiplication. This has led to an additional computational complexity. The approximation of the DST-VII can be used for the transform optimization. At the hardware level, this method can provide a gain in power consumption, logic resources use and speed. In this paper, a unifed two-dimensional transform architecture that enables exact and approximate DST-VII computation of sizes 8times 8, 8times 16, 8times 32, 16times 8, 16times 16, 16times 32, 32times 8, 32times 16 and 32times 32 is proposed. The exact transform computation can be processed using either multipliers or the MCM algorithm, while the approximate transform computation is based on additions and bit-shifting operations. All the designs are implemented under the Arria 10 FPGA device. The synthesis results show that the proposed design implementing the approximate transform matrices is the most efficient method with only 4% of area consumption. It reduces the logic utilization by more than 65% compared to the multipliers-based exact transform design, while about 53% of hardware cost saving is obtained when compared to the MCM-based computation. Furthermore, the approximate-based 2D transform architecture can operate at 78 MHz allowing a real-time coding for 2K and 4K videos at 100 and 25 frames/s, respectively.

Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures

The Complex Matrix Multiplication (CMM) algorithm is known to require a high computing performance and presenting exceptional challenges in real-life applications. Recent advances in Very Long Instruction Word (VLIW) based Digital Signal Processors (DSP) demonstrated high computing capabilities with a very low power consumption. In this work, we propose three ultra-fast, parallel and efficient VLIW implementation approaches of the CMM algorithm which could be used to meet tighter real-time constraints of several signal and image processing applications like radars. A novel parallel kernel, task mapping strategy and low-level optimization techniques are suggested, to fit a set of modern VLIW architectures. Additionally, an original memory access management technique was adopted to accelerate the algorithm by avoiding cache misses and bank conflicts. The experimental results showed the effectiveness of the proposed approaches where a peak performance of 15.89 GFLOPS was achieved on one C66x DSP core with a core utilization of 99% and a speedup of about 1.61, 3 and 10 compared to the state-of-the-art, the most optimized vendor and the conventional approaches, respectively.

Extended use of error-free transformation for real matrix multiplication to complex matrix multiplication

The presence of rounding errors is frequently inevitable when performing arithmetic operations in computers due to the use of floating-point number system whose elements have finite precision. Consequently, error-free transformation algorithms are proposed as solutions, and a particular instance of these is the error-free transformation algorithm for real matrix multiplication. Based on the previously mentioned algorithm, this study proposes two error-error free transformation algorithms for complex matrix multiplication. By conducting the numerical experiment, one finds that the combination of both proposed algorithms with an accurate summation algorithm generates the most accurate results, but it also suffers from a notable increase in the computing time ratio. On the other hand, the second proposed algorithm, which is simply another form of the first one with the change of order in summation, combined with the pure floating-point addition produces results that are nearly as accurate as those generated by the former combination. Since these results are achieved with significantly smaller computing time ratio, then the study concludes that the last combination is the best method for complex matrix multiplication in terms of accuracy and computing time efficiency.

Low Complexity FFT Factorization for CS Reconstruction

In this paper is presented a novel area efficient Fast Fourier transform (FFT) for real-time compressive sensing (CS) reconstruction. Among various methodologies used for CS reconstruction algorithms, Greedy-based orthogonal matching pursuit (OMP) approach provides better solution in terms of accurate implementation with complex computations overhead. Several computationally intensive arithmetic operations like complex matrix multiplication are required to formulate correlative vectors making this algorithm highly complex and power consuming hardware implementation. Computational complexity becomes very important especially in complex FFT models to meet different operational standards and system requirements. In general, for real time applications, FFT transforms are required for high speed computations as well as with least possible complexity overhead in order to support wide range of applications. This paper presents an hardware efficient FFT computation technique with twiddle factor normalization for correlation optimization in orthogonal matching pursuit (OMP). Experimental results are provided to validate the performance metrics of the proposed normalization techniques against complexity and energy related issues. The proposed method is verified by FPGA synthesizer, and validated with appropriate currently available comparative analyzes.

Forward-Inverse 2D Hardware Implementation of Approximate Transform Core for the VVC Standard

The future video coding standard named Versatile Video Coding (VVC) is expected by the end of 2020. VVC will enable better coding efficiency than the current High Efficiency Video Coding (HEVC) standard. This coding gain is brought by several coding tools. The Multiple Transform Selection (MTS) is one of the key coding tools that have been introduced in VVC. The MTS concept relies on three transform types including Discrete Cosine Transform (DCT)-II, Discrete Sine Transform (DST)-VII and DCT-VIII. Unlike the DCT-II that has fast computing algorithms, the DST-VII and DCT-VIII rely on more complex matrix multiplication. In this paper an approximation approach is proposed to reduce the computational cost of the DST-VII and DCT-VIII. The approximation consists in applying adjustment stages, based on sparse block-band matrices, to a variant of DCT-II family mainly DCT-II and its inverse. Genetic algorithm is used to derive the optimal coefficients of the adjustment matrices. Moreover, an efficient hardware implementation of the forward and inverse approximate transform module is proposed. The architecture design includes a pipelined and reconfigurable forward-inverse DCT-II core transform as it is the main core for DST-VII and DCT-VIII computations. The proposed 32-point 1D architecture including low cost adjustment stages allows the processing of a video in 2K and 4K resolutions at 1095 and 273 frames per second, respectively. A unified 2D implementation of forward-inverse DCT-II, approximate DST-VII and DCT-VIII is also presented. The synthesis results show that the design is able to sustain a video in 2K and 4K resolutions at 386 and 96 frames per second, respectively, while using only 12% of Alms, 22% of registers and 30% of DSP blocks of the Arria10 SoC platform.

Implementing High-performance Complex Matrix Multiplication via the 3m and 4m Methods

In this article, we explore the implementation of complex matrix multiplication. We begin by briefly identifying various challenges associated with the conventional approach, which calls for a carefully written kernel that implements complex arithmetic at the lowest possible level (i.e., assembly language). We then set out to develop a method of complex matrix multiplication that avoids the need for complex kernels altogether. This constraint promotes code reuse and portability within libraries such as Basic Linear Algebra Subprograms and BLAS-Like Library Instantiation Software (BLIS) and allows kernel developers to focus their efforts on fewer and simpler kernels. We develop two alternative approaches—one based on the 3 m method and one that reflects the classic 4 m formulation—each with multiple variants, all of which rely only on real matrix multiplication kernels. We discuss the performance characteristics of these “induced” methods and observe that the assembly-level method actually resides along the 4 m spectrum of algorithmic variants. Implementations are developed within the BLIS framework, and testing on modern hardware confirms that while the less numerically stable 3 m method yields the fastest runtimes, the more stable (and thus widely applicable) 4 m method’s performance is somewhat limited due to implementation challenges that appear inherent in nature.

Empirical Analysis of HPC Using Different Programming Models

During the last decade, Heterogeneous systems are emerging for high performance computing [1]. In order to achieve high performance computing (HPC), existing technologies and programming models aims to see rapid growth toward intra-node parallelism [2]. The current high computational system and applications demand for a massive level of computation power. In last few years, Graphical processing unit (GPU) has been introduced an alternative of conventional CPU for highly parallel computing applications both for general purpose and graphic processing. Rather than using the traditional way of coding algorithms in serial by single CPU, many multithreading programming models has been introduced such as CUDA, OpenMP, and MPI to make parallel processing by using multicores. These parallel programming models are supportive to data driven multithreading (DDM) principle [3]. In this paper, we have presented performance based preliminary evaluation of these programming models and compared with the conventional single CPU serial processing system. We have implemented a massive computational operation for performance evaluation such as complex matrix multiplication operation. We used data driven multithreaded HPC system for performance evaluation and presented the results with a comprehensive analysis of these parallel programming models for HPC parallelism.

A 1.3 mW 48 MHz 4 Channel MIMO Baseband Receiver With 65 dB Harmonic Rejection and 48.5 dB Spatial Signal Separation

A four-channel multi-input multi-output (MIMO) complex baseband receiver for spectrum and space-aware cognitive radio applications is presented. The MIMO baseband receiver comprises a capacitive harmonic-rejection downconverting mixer (HRM) receiver and a signal-separation multi-input multi-output analog core (MAC) on a single integrated circuit. The HRM receiver performs frequency selection of the incoming RF signals by programmable spectral downconversion and filtering with minimal harmonic folding. The subsequent MAC separates the spectrally overlapping but spatially diverse signals by weighted complex matrix multiplication. The entire signal path is implemented using energy-efficient $g_m$ - $C$ analog circuits with digitally controlled capacitive weighting for configurable baseband down-/upconversion ranging from $-$ 24 to $+$ 24 MHz in the HRM, and programmable spatial filtering with 4 $\times$ 4 complex (8 $\times$ 8 real) 14-bit coefficients in the MAC. Measurements demonstrate greater than 65 dB harmonic-folding rejection by the HRM, and greater than 48.5 dB spatial signal separation by the MAC. The 65 nm CMOS IC occupies 3.27 $\text{mm}^{2}$ active area, and consumes 480 $\upmu$ W digital power at 45 MHz LO and 840 $\upmu$ W analog power at 3 MHz baseband from a 1.2 V supply.

Implementation of LTE spatial multiplexing based on FPGA

Through the analysis of Field-Programmable Gate Array(FPGA)-based spatial multiplexing coding problem in Long Term Evolution(LTE),an implementation of codebook-based precoding was proposed.According to the parameters of the upper informed carried on the table look-up in the mathematical table and the addition and subtraction relations table,the data of layer mapping first carried on coefficient multiplication,and then with addition and subtraction,thus this has replaced the complex matrix multiplication operation.Therefore,this method can greatly reduce the complex matrix multiplication operation in the precoding procedure,and reduce the complexity of encoding process,improve the speed of the encoding operation.The experimental results indicate that the proposed algorithm can achieve a good system performance.

An Efficient DCT Compression Technique using Strassen's Matrix Multiplication Algorithm

compression' minimizes the problem that we face in storing and transmitting large amount of data. It reduces the size of data required to represent a digital image. In this procedure, DCT plays an important role. It separates information by using different frequencies. In Discrete Cosine Transformation (DCT), Quantization and encoding are the steps involved in the compression of the JPEG image. In this whole work, while using DCT, we have used Stassen's matrix multiplication algorithm for reducing the complex matrix multiplication problems. As per the result obtained from experiment, the performance of DCT is improved by using Stassen's matrix multiplication algorithm. The performance analysis is carried out through Peak signal to noise ratio (PSNR), and the different compression ratio (CR) for the different images. Keywords— compression, strassen's matrix multiplication, CR, DCT, JPEG, PSNR.

FPGA realization of high performance large size computational functions: multipliers and applications

In this paper, efficient design methodologies and systematic approaches for realizing large size signed multipliers based on the use of small-size embedded blocks in FPGAs are presented. Two algorithms, delay table and dynamic programming addition optimizations, are used to efficiently organize the addition of partial products. To demonstrate the effectiveness of our approaches, two large size operand computations are realized using our optimized large size multipliers. These functions are complex multiplication and matrix multiplication. The implementations target Xilinx' and Altera's FPGAs. When our approaches are compared to those of traditional techniques, the results show improvements of performance and area usage for both applications.

An 8-bit systolic AES architecture for moderate data rate applications

The complexity involved in mapping an algorithm to hardware is a function of the controller logic and data path. Minimizing data path size can lead to significant savings in hardware area and power dissipation. This paper presents an implementation of a novel architectural transformation technique for mapping a word bit wide algorithm to byte vector serial architecture. The technique divides the input word to several bytes and then traces each byte for extracting architectural transformation. The technique is applied on Advanced Encryption Standard (AES) algorithm which is non-linear in nature. Using this technique, the 32-bit AES algorithm is transformed into a byte-systolic architecture. The novelty of the technique is more pronounced around the mix column design which is the most complex part of the AES algorithm. The complex matrix multiplication component and standard transformations of the 32-bit AES algorithm are transformed to support 8-bit operations. The resulted AES architectures reuse same logic resources for key expansion and encryption/decryption. The proposed design offers moderate data rates in the range of 41 Mbps for encryption and 37 Mbps for decryption while utilizing 236 and 280 slices, respectively, on Xilinx Virtex II xc2v1000-6 FPGA. Comparison results show significant gain in throughput when compared with other 8-bit designs. This makes it a viable data/communication security solution for a variety of embedded and consumer electronics.

Phase analysis of an optical complex array multiplication system

The phase accuracy of an optical system for complex matrix multiplication is examined by using a novel harmonic analysis approach and a stochastic model for the complex optical transfer function spatial light modulators. The output phase bias and standard deviation are evaluated for matched and unmatched channel power gains. The conclusions drawn appear to be of general value in the numerous applications of spatial light modulators to optical information-processing systems.

Stability of a Method for Multiplying Complex Matrices with Three Real Matrix Multiplications

By use of a simple identity, the product of two complex matrices can be formed with three real matrix multiplications and five real matrix additions, instead of the four real matrix multiplications and two real matrix additions required by the conventional approach. This alternative method reduces the number of arithmetic operations, even for small dimensions, achieving a saving of up to 25 percent. The numerical stability of the method is investigated. The method is found to be less stable than conventional multiplication but stable enough to warrant practical use. Issues involved in the choice of method for complex matrix multiplication are discussed, including the relative efficiency of real and complex arithmetic and the backward stability of block algorithms.

Fast algorithms for complex matrix multiplication using surrogates

Novel fast algorithms for multiplying square complex matrices are presented. The algorithms are based on concepts from fast methods of complex multiplication in which a surrogate is used for the square root of minus one. Previous methods imposed the structure of a finite ring or field on the problem. The novel algorithms also use a surrogate, but do not require the imposed structure and its inherent rounding. The number of real matrix multiplications required can be reduced from four to two for even dimension, and to 2+1/N/sup 2/ for odd dimension N. The disadvantage of the algorithms is the imposition of a requirement on the structure of one of the two complex matrices being multiplied. The 2*2 case of the algorithm can be adapted to computing Givens rotations, resulting in a 17% savings in real matrix multiplications. >

Comparison of theoretical and experimental behaviour of supermirrors and discussion of limitations

The theoretical behaviour of reflectivity and transmission of multilayers using a complex index of refraction resulting from the optical theorem is calculated numerically by a complex matrix multiplication method. It is applied to the antireflecting layer and for different layer sequences of supermirrors and compared with measurements. Resulting limits and some ways to overcome these are discussed.