Complex Logic Device Research Articles

More Than a Device: Function Implementation in a Multi-Gate Junctionless FET Structure

The miniaturization of the transistor sizes to keep up with Moore's Law in Integrated Circuits (ICs) is rapidly approaching the physical limits. To push the horizons of Moore's Law, among the various approaches available in the literature, single device-based computing shows promise by achieving more functionality in a smaller footprint. However, a single device-based computing approach either mainly embeds only the primitive logic hence inefficient in performance, or requires exotic devices like spin logic devices, and memristor which involve non-conventional costly manufacturing steps. Previously, we introduced the concept of embedding logic in a single device based on Crosstalk Computing, where deterministic signal interference between nano-metal lines is leveraged for logic computation. This paper elaborates upon the methodology of realizing complex Boolean functions through TCAD-based modeling and simulations, quantifying results, and compares against existing approaches. Core to our approach is a multi-gate Junctionless FET-based device, methodical placement of the independent gates, manipulation of device parameters, and dimension. This paper shows the implementation of various complex logic functions along with the primitive gates in the proposed device. Our benchmark results show 8x density benefits and 8x less power consumption on average than CMOS-based implementation. For the case of delay, elementary and complex logic devices show comparable characteristics with 14 nm PTM counterparts. Such realization of complex functions in a stand-alone device is compatible with the existing fabrication process.

All-Optical 2 $ \times $ 2-Bit Multiplier at 40 Gb/s Based on Canonical Logic Units-based Programmable Logic Array (CLUs-PLA)

Multiplication is an important function of logic operation, and all-optical high-speed multiplication logic operation will lay the foundation for future high-speed optical computing and optical logic processing chip. In this article, by introducing the structure of canonical logic units-based programmable logic array (CLUs-PLA), we propose a scheme to realize all-optical 2 × 2-bit multiplier. In our scheme, different types of CLUs are generated using bidirectional multichannel four-wave mixing (FWM), then the results of multiplier at the operation of 40 Gb/s can be obtained by simple power coupling of corresponding CLUs. Eye diagrams of logic results are widely open, and the extinction ratios are more than 9.4 dB. Comparing with multiplier based on traditional hierarchical computing, multiplier based on parallel computing in our scheme can reduce the number of AND gate by 4, and avoid further deterioration of signal quality due to three-order cascade of AND gate. Moreover, the scheme has the potential to realize m × n-bit (m + n ≤ 9, m and n are positive integers) multiplier at higher operation rate in the integrated platform, paving the way towards multi-bit high-speed compact complex logic devices for future high-performance optical computing and optical logic processing chip.

Universal Magnetic Hall Circuit Based on Paired Spin Heterostructures

The merit of advanced hybrid memory and logic devices not only lies in their high performance and superior functionalities but also their capability to establish a complete computational system, including full memory and logic functionalities. In this paper, a novel, ultrahigh‐performance device concept for hybrid memory and logic applications is presented, which relies on spin‐based magnetic Hall measurements. Employing a pair of spintronic heterostructures, the new system shows flexible functionality as both a robust memory element and a complex logic device. The building blocks of this universal magneto‐Hall circuit are experimentally demonstrated, based on the paired heterostructures. Combined with a new type of circuit, this design paves the way for robust room‐temperature spintronics.

All-Photonic Multifunctional Molecular Logic Device

Photochromes are photoswitchable, bistable chromophores which, like transistors, can implement binary logic operations. When several photochromes are combined in one molecule, interactions between them such as energy and electron transfer allow design of simple Boolean logic gates and more complex logic devices with all-photonic inputs and outputs. Selective isomerization of individual photochromes can be achieved using light of different wavelengths, and logic outputs can employ absorption and emission properties at different wavelengths, thus allowing a single molecular species to perform several different functions, even simultaneously. Here, we report a molecule consisting of three linked photochromes that can be configured as AND, XOR, INH, half-adder, half-subtractor, multiplexer, demultiplexer, encoder, decoder, keypad lock, and logically reversible transfer gate logic devices, all with a common initial state. The system demonstrates the advantages of light-responsive molecules as multifunctional, reconfigurable nanoscale logic devices that represent an approach to true molecular information processing units.

Radio frequency operation of clocked quantum-dot cellular automata latch

The radio frequency operation of a single-electron latch based on Al–AlOx–Al tunnel junctions is presented. By capacitively coupling the latch to a radio frequency single electron transistor, charge switching on the microsecond timescale is demonstrated. The fast switching and high repeatability of the latch response indicates that high speed operation of pipelines, signal fan-outs, and more complex logic devices are possible with this technology. The experimental technique developed is also promising for enabling the investigation of the intrinsic switching speed in electronic quantum-dot cellular automata-based circuits.

Towards Development and Characterization of Ionic Junction via Microcontact Printing

AbstractThe paper presents an evaluation of the feasibility of developing ionic surfactant coated single walled carbon nanotube (SWCNTs) (P-N) junction clusters via microcontact printing using intrinsic semi conducting SWCNTs. These SWCNTs are doped with anionic and cationic surfactant molecules respectively, thereby altering the Fermi energy levels of and its electrical properties. Two types of surfactants were used for doping the SWCNTs to develop extrinsically doped P and N type SWCNTs. Sodium dodecyl sulfate (SDS) having Na+ positive ionic charge (anions) and Cetyl trimethylammonium bromide (CTAB), having Br- negative ionic charge (cations) on its hydrophilic ends have been used to generate anionic SWCNTs (P type) and cationic SWCNTs( N- type respectively. Using, dual level patterning process, these extrinsically doped anionic and cationic semiconducting SWCNTs clusters are alternatively symmetrically patterned in a parallel array to form crossbar P-N junctions onto a standard microfabricated platform using flexible polymeric poly-dimethylsiloxane (PDMS) stamps. Ink-based transfer of the nanomaterial from the relief structures achieves parallel alignment of SWCNTs clusters. The electrical device characterization is achieved by measuring I-V characteristics from the base micro fabricated platform. Functionality of the nanodevice is demonstrated by studying the rectifying current – voltage (I-V) characteristics that shows promise towards the formation of a junction diode array, which can be used for integrating complex logic devices for high-end applications such as memory module and addressable logic. Lastly, we believe that the chemical modulation method and microcontact printing techniques will have a wide scope for development of nanomaterial-based devices.

Chemical-mechanical planarization of Cu and Ta

As device dimensions continue to shrink, multilevel (>8) interconnects are required to efficiently implement complex logic device designs in a single silicon chip. When the number of metal interconnect levels increases, the available depth-of-focus budget of lithographic tools imposes stringent planarity requirements that can only be met currently by chemical-mechanical planarization (CMP). Improved speed and performance are extracted from such devices by switching to copper from Al/Cu as the interconnect metal and to lower dielectric constant inner layers. Use of copper also requires the simultaneous introduction of diffusion-barrier/adhesion-promotion layers of tantalum or TaN. This paper reviews some of the recent advances in the fundamental understanding of the interplay between the mechanical and chemical components of the material-removal process during CMP of copper and tantalum films. The emphasis will be on the role of different process variables in slurries containing silica or alumina abrasives in hydrogen peroxide/glycine solutions.