All-Optical 2 $ \times $ 2-Bit Multiplier at 40 Gb/s Based on Canonical Logic Units-based Programmable Logic Array (CLUs-PLA)

Abstract

Multiplication is an important function of logic operation, and all-optical high-speed multiplication logic operation will lay the foundation for future high-speed optical computing and optical logic processing chip. In this article, by introducing the structure of canonical logic units-based programmable logic array (CLUs-PLA), we propose a scheme to realize all-optical 2 × 2-bit multiplier. In our scheme, different types of CLUs are generated using bidirectional multichannel four-wave mixing (FWM), then the results of multiplier at the operation of 40 Gb/s can be obtained by simple power coupling of corresponding CLUs. Eye diagrams of logic results are widely open, and the extinction ratios are more than 9.4 dB. Comparing with multiplier based on traditional hierarchical computing, multiplier based on parallel computing in our scheme can reduce the number of AND gate by 4, and avoid further deterioration of signal quality due to three-order cascade of AND gate. Moreover, the scheme has the potential to realize m × n-bit (m + n ≤ 9, m and n are positive integers) multiplier at higher operation rate in the integrated platform, paving the way towards multi-bit high-speed compact complex logic devices for future high-performance optical computing and optical logic processing chip.