Complex Instruction Set Computer Research Articles

Implementation of a Multiclocked Pipelined Processor Based on RISc-V using RV321

This study's primary objective is to create a 32-bit pipelined processor based on the open-source RV32I Version 2.0 RISC-V ISA that operates across several clock domains. A processor known as a RISC (Reduced Instruction Set Computer) employs less hardware than a CISC (Complex Instruction Set Computer) in order to reduce the complexity of the instruction set and accelerate the execution time per instruction. In addition, we built this processor with five pipelining layers, which allows for concurrent processing of instructions. All of the procedures are thoroughly explained, supported with the required block diagrams. To guarantee that variable delays, such as clock skew and meta-stability, are avoided inside the stage pipeline registers, multiple clock domains using two clock sources are employed.

An Instruction Inflation Analyzing Framework for Dynamic Binary Translators

Dynamic binary translators (DBTs) are widely used to migrate applications between different instruction set architectures (ISAs). Despite extensive research to improve DBT performance, noticeable overhead remains, preventing near-native performance, especially when translating from complex instruction set computer (CISC) to reduced instruction set computer (RISC). For computational workloads, the main overhead stems from translated code quality. Experimental data show that state-of-the-art DBT products have dynamic code inflation of at least 1.46. This indicates that on average, more than 1.46 host instructions are needed to emulate one guest instruction. Worse, inflation closely correlates with translated code quality. However, the detailed sources of instruction inflation remain unclear. To understand the sources of inflation, we present Deflater , an instruction inflation analysis framework comprising a mathematical model, a collection of black-box unit tests called BenchMIAOes , and a trace-based simulator called InflatSim . The mathematical model calculates overall inflation based on the inflation of individual instructions and translation block optimizations. BenchMIAOes extract model parameters from DBTs without accessing DBT source code. InflatSim implements the model and uses the extracted parameters from BenchMIAOes to simulate a given DBT’s behavior. Deflater is a valuable tool to guide DBT analysis and improvement. Using Deflater, we simulated inflation for three state-of-the-art CISC-to-RISC DBTs: ExaGear, Rosetta2, and LATX, with inflation errors of 5.63%, 5.15%, and 3.44%, respectively for SPEC CPU 2017, gaining insights into these commercial DBTs. Deflater also efficiently models inflation for the open source DBT QEMU and suggests optimizations that can substantially reduce inflation. Implementing the suggested optimizations confirms Deflater’s effective guidance, with 4.65% inflation error, and gains 5.47x performance improvement.

Design of RISCV processor using verilog

The main goal of this paper is to develop a 32-bit pipelined processor with several clock domains based on the RISCV (open source RV32I Version 2.0) ISA. To minimize the complexity of the instruction set and speed up the execution time per instruction, a RISC (Reduced Instruction Set Computer) processor that uses less hardware than a CISC (Complex Instruction Set Computer) is used. Furthermore, this paper constructed this processor with five levels of pipelining with the aid of necessary block diagrams, and all of the processes are well described. In this paper, a RISCV processor is designed and simulated using Verilog. The design of the RISCV processor provides an alternative for software and hardware design to the computer designers as it provides free and open instruction set architecture (ISA). Besides, the designed RISCV processor will be using 5-stage pipeline techniques to improve the overall performance of the processor. This system is started by implementing several main modules, such as alu, aludec, maindec, imem, dmem, regfile, pc_mux, result_mux, pipeline register (IF/ID, ID/IEx, IEx/IMem, and IMem/IW), forwardMuxA, and forwardMuxB. Besides, a hazard unit is implemented into the design to mitigate hazard conditions. The functionality of these modules was simulated and verified by using Xilinx Vivado software.

Comparative Study of RISC AND CISC Architectures

Comparative Study of RISC AND CISC Architectures

Evaluation of CFD Computing Performance on Multi-Core Processors for Flow Simulations

Previous parallel computing implementations for Computational Fluid Dynamics (CFD) focused extensively on Complex Instruction Set Computer (CISC). Parallel programming was incorporated into the previous generation of the Raspberry Pi Reduced Instruction Set Computer (RISC). However, it yielded poor computing performance due to the processing power limits of the time. This research focuses on utilising two Raspberry Pi 3 B+ with increased processing capability compared to its previous generation to tackle fluid flow problems using numerical analysis and CFD. Parallel computing elements such as Secure Shell (SSH) and the Message Passing Interface (MPI) protocol were implemented for Advanced RISC Machine (ARM) processors. The parallel network was then validated by a processor call attempt and core execution test. Parallelisation of the processors enables the study of fluid flow and computational fluid dynamics (CFD) problems, such as validation of the NACA 0012 airfoil and an additional case of the Laplace equation for computing the temperature distribution via the parallel system. The experimental NACA 0012 data was validated using the parallel system, which can simulate the airfoil's physics. Each core was enabled and tested to determine the system's performance in parallelising the execution of various programming algorithms such as pi calculation. A comparison of the execution time for the NACA 0012 validation case yielded a parallelisation efficiency above 50%. The case studies confirmed the Raspberry Pi 3 B+'s successful parallelisation independent of external software and machines, making it a self-sustaining compact demonstration cluster of parallel computers for CFD.

The Renesas Automotive Story in the History of the Microprocessor

Renesas Electronics has a long history of providing high-quality and reliable microcontrollers to the automotive industry for many years. Renesas is the consolidation of the semiconductor units of Hitachi, Mitsubishi, and NEC Electronics. Hitachi and Mitsubishi's semiconductor businesses were divested from each company and merged into Renesas Technology in 2003. NEC Electronics’ semiconductor business was divested in 2010 and merged into a combined Renesas Electronics in 2010. Each company had developed various 8-bit and 16-bit complex instruction set computer (CISC) architecture devices and 32-bit RISC architecture devices. Elements of all these previous architectures' devices are found in the newest Renesas devices available today, with the 32-bit RH850 being the highest selling automotive microcontroller for several years since its introduction.

A Strategical Approach for Implementing Digital Games on FPGA

Field Programmable Gate Arrays (FPGAs) are providing potential solutions to the most of the technological advancements. Starting from the basic modeling of RISC and CISC processors to the complicated designs of processors for data analytics, the FPGAs are being used. Parallelism and Pipelining are the features that are enabling for its application is almost all the domains of Electronics and Communications Industry. In view of such applications, getting expertise in implementation of Digital System Designs on FPGA will become inevitable for Electronics and Communication Engineering Graduate. Learning from Gaming has proved to be successful from the very past. Inspired from the Project based learning pedagogy [15], we have come up with a novel idea of making a student learn FPGA in the process of designing and implementing a single player and two player games. The entire problem formulation of designing these games is divided into tasks and student will be learning these tasks initially. Later, integrating such tasks will evolve into games. As a part of these five games, namely Snake game, Spaceman game, Pacman game, Tic-Tac-Toe and Battle tanker games were successfully implemented on the NEXYS4 DDR FPGA Board. This implementation is done using Xilinx Vivado Software.

A Multi-One Instruction Set Computer for Microcontroller Applications

This work presents a simple integer-only instruction set architecture and microarchitecture derived from One Instruction Set Computers (OISCs) and embedding multiple execution modes ( ${m}$ OISC), capable of running at a reasonable performance level to enable basic usability in microcontroller applications. The purpose of ${m}$ OISC is to enable simple data transfer tasks and run small programs while maintaining ultimate simplicity. We present the internal organization for a computer architecture including an 8bit I/O register, and 64kB central Random Access Memory (RAM), organized in two-bytes words. The processor can run code generated assuming an OISC or a Complex Instruction Set Computer (CISC) scheme (op-code based), depending on the programmer’s demands and based on the initial setting of a register during start-up. To enable practical applications and demonstrate successful exploitation of ${m}$ OISC in view of integration in a compiler back-end, we designed a custom Proof-of-Concept (PoC) software design toolchain based on LLVM and clang . Although not targeting all the features of commercial ISA, the toolchain is capable of compiling C code from LLVM intermediate representation or generating ${m}$ OISC code translated from ARM, x86, RISC-V, and MIPS assembly. The toolchain also enables practical Value Change Dump (VCD) simulations output with graphical plots of the CPU state and associated symbols. A PoC microcontroller system has been synthesized in a low power Field Programmable Gate Array (FPGA) and verified in a basic wireless telemetry application including a Synchronous Peripheral Interface (SPI) RFM9x Long RAnge (LoRA) transceiver and a MAX30205 Inter Integrated Circuit (I2C) temperature sensor, using its 8bit I/O port, with software bus interface implementation. ${m}$ OISC occupies ~6% of resources on a Cyclone 10LP FPGA, for 1397 Adaptive Look-Up Tables (ALUTs) and 461 dedicated logic registers. The measured dynamic current consumption of the complete FPGA board with synthesized ${m}$ OISC is 12mA at 100MHz clock.

Streaming Performance Analysis of Virtual Objects in Augmented Reality Cloud Based on X86 and ARM Processor Types

Augmented Reality is a technology that makes it possible to create 3D objects in the real world with the help of a camera on a gadget. In its development, Augmented Reality technology began to be developed and combined with cloud computing technology. With the existence of Cloud computing technology Augmented reality can work more efficiently because all 3D objects can be stored on the Cloud. With the development of this technology, the author feels the need to conduct an analysis to determine the right processor in making the Augmented Reality Cloud application, because there is no research that is used as a reference in developing hardware and software used for Augmented Reality Cloud. Result of this experiment can be concluded CISC architecture processors have faster time in detecting markers compared to RISC architecture processors, because CISC processor speeds are faster than RISC processors.

A new efficient assembly language teaching aid for intel processors

ABSTRACTAssembly 8086 language is an essential course that is taught in many universities offering computer engineering or science degree. However, the available software simulators that are used to write and run assembly programs do not fulfill the students' expectations due to being difficult to deal with and lacking a lot of necessary GUI features. In this article, we introduce a new Assembly Language Teaching Aid (ALTA32 or ALTA8086) which is basically a simulator that helps much in delivering concepts related to assembly language programming course for Intel microprocessors (µps). Among current and relevant simulators, ALTA32 not only is the simplest and easiest to use, but also has the most fascinating user‐friendly interface that exhibits constructive and informative features. Additionally, it offers multiple run modes with the option of writing programs directly or through loading existing files. It works efficiently in both 16‐bit and 32‐bit extensions considering real mode memory addressing. It supports all data and stack memory addressing modes along with all available directives to be used in both model and full‐segment program approaches. Furthermore, to understand and recognize changes after execution, all affected fields are emphasized and shown using visual effects such as dynamic labels, blinking texts, as well as colored codes. On the other hand, it is widely known that the Complex Instruction Set Computing (CISC) architecture, which is also a register‐memory architecture, is characterized by affording many instructions with various operands, affected flags, complex operations, and sources of syntax errors. Although it is really challenging to build up a simulator that completely supports that wide range of Intel assembly instructions taking into account the variety in their lengths and formats, we succeeded eventually to eliminate the code redundancy and make our code readable, maintainable, and scalable through programming all instructions based on the methodology of combining or grouping all instructions that almost act similarly to follow a certain efficient algorithm. As a programming environment, VB.Net has been used to develop the ALTA32 simulator. Throughout our experience in teaching assembly 8086 language programming course for CISC processors, we found many difficulties in getting the students familiar with well‐known simulators such as Microsoft Macro Assembler (MASM8086 or MASM32) or 8086 µp Emulator (EMU8086). Nevertheless, the feedback from our students about ALTA32 simulator was so impressive and the complaints were totally disappeared. © 2014 Wiley Periodicals, Inc. Comput Appl Eng Educ 23:217–238, 2015; View this article online at wileyonlinelibrary.com/journal/cae; DOI 10.1002/cae.21591

A methodology for testing CPU emulators

A CPU emulator is a software system that simulates a hardware CPU. Emulators are widely used by computer scientists for various kind of activities (e.g., debugging, profiling, and malware analysis). Although no theoretical limitation prevents developing an emulator that faithfully emulates a physical CPU, writing a fully featured emulator is a very challenging and error prone task. Modern CISC architectures have a very rich instruction set, some instructions lack proper specifications, and others may have undefined effects in corner cases. This article presents a testing methodology specific for CPU emulators, based on fuzzing. The emulator is “stressed” with specially crafted test cases, to verify whether the CPU is properly emulated or not. Improper behaviors of the emulator are detected by running the same test case concurrently on the emulated and on the physical CPUs and by comparing the state of the two after the execution. Differences in the final state testify defects in the code of the emulator. We implemented this methodology in a prototype (named as EmuFuzzer), analyzed five state-of-the-art IA-32 emulators (QEMU, Valgrind, Pin, BOCHS, and JPC), and found several defects in each of them, some of which can prevent proper execution of programs.

Design and Implementation of a Fast Dynamic Packet Filter

This paper presents Swift, a packet filter for high-performance packet capture on commercial off-the-shelf hardware. The key features of the Swift include: 1) extremely lowfilter update latency for dynamic packet filtering, and 2) gigabits-per-second high-speed packet processing. Based on complex instruction set computer (CISC) instruction set architecture (ISA), Swift achieves the former with an instruction set design that avoids the need for compilation and security checking, and the latter by mainly utilizing single instruction, multiple data (SIMD). We implement Swift in the Linux 2.6 kernel for both i386 and ×86-64 architectures and extensively evaluate its dynamic and static filtering performance on multiple machines with different hardware setups. We compare Swift to BPF (the BSD packet filter)--the de facto standard for packet filtering in modern operating systems--and hand-coded optimized C filters that are used for demonstrating possible performance gains. For dynamic filtering tasks, Swift is at least three orders of magnitude faster than BPF in terms of filter update latency. For static filtering tasks, Swift outperforms BPF up to three times in terms of packet processing speed and achieves much closer performance to the optimized C filters. We also show that Swift can harness the processing power of hardware SIMD instructions by virtue of its SIMD-capable instruction set.

Design and microarchitecture of the IBM System z10 microprocessor

The IBM System z10™ microprocessor is currently the fastest running 64-bit CISC (complex instruction set computer) microprocessor. This microprocessor operates at 4.4 GHz and provides up to two times performance improvement compared with its predecessor, the System z9® microprocessor. In addition to its ultrahigh-frequency pipeline, the z10™ microprocessor offers such performance enhancements as a sophisticated branch-prediction structure, a large second-level private cache, a data-prefetch engine, and a hardwired decimal floating-point arithmetic unit. The z10 microprocessor also implements new architectural features that allow better software optimization across compiled applications. These features include new instructions that help shorten the code path lengths and new facilities for software-directed cache management and the use of 1-MB virtual pages. The innovative microarchitecture of the z10 microprocessor and notable differences from its predecessors and the IBM POWER6™ microprocessor are discussed.

Automated Worst-Case Execution Time Analysis Based on Program Modes

A program mode is a regular trajectory of the execution of a program that is determined by the values of its input variables. By exploiting program modes, we may make worst-case execution time (WCET) analysis more precise. This paper presents a novel method to automatically find program modes and calculate the WCET estimates of programs. First, the modes of a program will be identified automatically by mode-relevant program slicing, and the precondition will be calculated for each mode using a path-wise test data generation method. Then, for each feasible mode, we show how to calculate its WCET estimate for modern reduced instruction set computer (RISC) processors with caches and pipelines and for traditional complex instruction set computer (CISC) processors. We also present a method to obtain the symbolic expression for each mode for CISC processors. The experimental results show the effectiveness of the method.

A retargetable framework for instruction-set architecture simulation

Instruction-set architecture (ISA) simulators are an integral part of today's processor and software design process. While increasing complexity of the architectures demands high-performance simulation, the increasing variety of available architectures makes retargetability a critical feature of an instruction-set simulator. Retargetability requires generic models while high-performance demands target specific customizations. To address these contradictory requirements, we have developed a generic instruction model and a generic decode algorithm that facilitates easy and efficient retargetability of the ISA-simulator for a wide range of processor architectures, such as RISC, CISC, VLIW, and variable length instruction-set processors. The instruction model is used to generate compact and easy to debug instruction descriptions that are very similar to that of architecture manual. These descriptions are used to generate high-performance simulators. Our retargetable framework combines the flexibility of interpretive simulation with the speed of compiled simulation. The generation of the simulator is completely separate from the simulation engine. Hence, we can incorporate any fast simulation technique in our retargetable framework without introducing any performance penalty. To demonstrate this, we have incorporated fast IS-CS simulation engine in our retargetable framework which has generated 70% performance improvement over the best known simulators in this category. We illustrate the retargetability of our approach using two popular, yet different, realistic architectures: the SPARC and the ARM.

Rematch for CISC

The complex instruction set computer (CISC) seemed consigned to the dustbin of history. But it's coming back to deal with a growing need for custom instructions to get more performance out of processors beyond multimedia applications. The first thing needed in order to produce one of these customisable processors is a way of altering the hardware at runtime. Configurable processors are used widely in digital audio players, storage units and network equipment. FPGAs are commonly used in low-volume hardware as alternatives to custom chips. The latest processor makes it possible to build long instruction words out of the processor operations that are available to the basic processor.

High prevalence of BRCA1 mutations in breast + ovarian cancer patients at the region of Gdansk, Poland

In this paper we will introduce a high performance implementation of our C-processor architecture. The C-processor is a memory based CISC processor intended for the efficient execution of high level block structured languages. The resulting pipelined implementation is quite different from the pipelines normally found in current RISC microprocessors. The main differences are the number of stages and the interlock problems caused by the memory oriented design.

Effectiveness of cross-platform optimizations for a java just-in-time compiler

This paper describes the system overview of our Java Just-In-Time (JIT) compiler, which is the basis for the latest production version of IBM Java JIT compiler that supports a diversity of processor architectures including both 32-bit and 64-bit modes, CISC, RISC, and VLIW architectures. In particular, we focus on the design and evaluation of the cross-platform optimizations that are common across different architectures. We studied the effectiveness of each optimization by selectively disabling it in our JIT compiler on three different platforms: IA-32, IA-64, and PowerPC. Our detailed measurements allowed us to rank the optimizations in terms of the greatest performance improvements with the smallest compilation times. The identified set includes method inlining only for tiny methods, exception check eliminations using forward dataflow analysis and partial redundancy elimination, scalar replacement for instance and class fields using dataflow analysis, optimizations for type inclusion checks, and the elimination of merge points in the control flow graphs. These optimizations can achieve 90% of the peak performance for two industry-standard benchmark programs on these platforms with only 34% of the compilation time compared to the case for using all of the optimizations.

An Object-Oriented Educational Tool to Simulate Multilevel Computer Architectures

We describe a simulator that is a useful supporting tool in all activities involving computer architecture teaching. The system, developed using an object-oriented approach, integrates in a single tool different architecture models, such as CISC and RISC architecture types, and different computer levels, such as microprogramming and instruction set levels. The system allows the user to define the computer architecture at the instruction set level and then to switch automatically to the lower level of the corresponding micro-architecture. The simulation process consists of a loop, in which two strictly correlated phases are executed: the definition phase, in which the user defines the architecture through a choice of hardware components, and a test phase, in which the user tests the designed architecture in order to verify the result of the design activity of the previous phase. Once the processor design has been completed through this simulation process, the tool allows the user to save and use a stand-alone simulator of the target computer architecture. The definition and simulation activities of the computer architecture are supported by a graphical user interface for an effective, easy-to-use teaching environment.

A framework for high‐performance matrix multiplication based on hierarchical abstractions, algorithms and optimized low‐level kernels

AbstractDespite extensive research, optimal performance has not easily been available previously for matrix multiplication (especially for large matrices) on most architectures because of the lack of a structured approach and the limitations imposed by matrix storage formats. A simple but effective framework is presented here that lays the foundation for building high‐performance matrix‐multiplication codes in a structured, portable and efficient manner. The resulting codes are validated on three different representative RISC and CISC architectures on which they significantly outperform highly optimized libraries such as ATLAS and other competing methodologies reported in the literature. The main component of the proposed approach is a hierarchical storage format that efficiently generalizes the applicability of the memory hierarchy friendly Morton ordering to arbitrary‐sized matrices. The storage format supports polyalgorithms, which are shown here to be essential for obtaining the best possible performance for a range of problem sizes. Several algorithmic advances are made in this paper, including an oscillating iterative algorithm for matrix multiplication and a variable recursion cutoff criterion for Strassen's algorithm. The authors expose the need to standardize linear algebra kernel interfaces, distinct from the BLAS, for writing portable high‐performance code. These kernel routines operate on small blocks that fit in the L1 cache. The performance advantages of the proposed framework can be effectively delivered to new and existing applications through the use of object‐oriented or compiler‐based approaches. Copyright © 2002 John Wiley & Sons, Ltd.