Complex Fast Fourier Transform Research Articles

A novel fast time jamming analysis transmission selection technique for radar systems

The jamming analysis transmission selection (JATS) sub-system is used in radar systems to detect and avoid the jammed frequencies in the available operating bandwidth during signal transmission and reception. The available time to measure the desired frequency spectrum and select the non-jammed frequency for transmission is very limited. A novel fast time (FAT) technique that measures the channel spectrum, detects the jamming sub-band and selects the non-jammed frequency for radar system transmission in real time is proposed. A JATS sub-system has been designed, simulated, fabricated and implemented based on FAT technique to verify the idea. The novel FAT technique utilizes time-domain analysis instead of the well-known fast Fourier transform (FFT) used in conventional JATS sub-systems. Therefore, the proposed fast time jamming analysis transmission selection (FAT-JATS) sub-system outperforms other reported JATS sub-systems as it uses less FPGA resources, avoids time-delay occurred due to complex FFT calculations and enhances the real time operation. This makes the proposed technique an excellent candidate for JATS sub-systems.

An efficient channelization architecture and its implementation for radio astronomy

Channelization is one of the most important parts in a Digital Back-End(DBE) for radio astronomy. A DBE with wider bandwidth and higher resolution consumes larger amount of computing and memory resources, which results in much higher hardware cost. This paper presents an efficient channelization architecture, which consists of Bit-Inverted, Parallel Complex Fast Fourier Transform(BIPC-FFT) and In-place Forward-Backward Decomposition(IPFBD). The efficient architecture can assist with saving a lot of resources, so a wide-band and high-resolution DBE can be implemented on an resource restricted platform. Based on the efficient channelization architecture, we designed a Dual-Input, 64K-Channelized prototype DBE with 1.2 GHz bandwidth on a Xilinx Virtex-6 LX240T Field Programmable Gate Array(FPGA) chip. The test results in the lab and observation results at Yunnan Observatory demonstrate the DBE can be used for radio astronomy.

Low Complexity FFT Factorization for CS Reconstruction

In this paper is presented a novel area efficient Fast Fourier transform (FFT) for real-time compressive sensing (CS) reconstruction. Among various methodologies used for CS reconstruction algorithms, Greedy-based orthogonal matching pursuit (OMP) approach provides better solution in terms of accurate implementation with complex computations overhead. Several computationally intensive arithmetic operations like complex matrix multiplication are required to formulate correlative vectors making this algorithm highly complex and power consuming hardware implementation. Computational complexity becomes very important especially in complex FFT models to meet different operational standards and system requirements. In general, for real time applications, FFT transforms are required for high speed computations as well as with least possible complexity overhead in order to support wide range of applications. This paper presents an hardware efficient FFT computation technique with twiddle factor normalization for correlation optimization in orthogonal matching pursuit (OMP). Experimental results are provided to validate the performance metrics of the proposed normalization techniques against complexity and energy related issues. The proposed method is verified by FPGA synthesizer, and validated with appropriate currently available comparative analyzes.

A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs

Soft errors are an important issue for SRAM-based Field Programmable Gate Arrays (FPGAs), since they result in permanent alterations of the mapped circuit when they affect their configuration memory. Concurrent Error Detection (CED) techniques, such as Dual Modular Redundancy (DMR), are usually employed to detect errors that affect the performance of the circuit. When trying to detect errors produced on the complex Fast Fourier Transform (FFT), the Parseval Sum of Squares (SoS) is a widely used technique. In this paper, we present a scheme to implement CED techniques for the complex FFT implemented in SRAM-based FPGAs. These techniques perform checks based on the relationships existing between one or more of the inputs and the outputs of the algorithm. Three examples of these techniques are provided to further clarify how to construct them. These techniques, along with DMR and SoS, have been tested through fault injection. An analysis on their error detection capabilities shows that they achieve high detection rates with much less resource usage than DMR and SoS. In addition, the number of false error detections for these techniques is lower than that of SoS, which leads to less unnecessary reconfigurations of the device.

Life-cycle cost analysis of roofing technologies in tropical areas

Various technologies have been applied on roofs to reduce the air-conditioning load in buildings during summer or in tropical areas, including cool paint, roof ventilation, mass and reflective insulation. These technologies help to reduce roof temperatures or heat transmission effectively in summer at different economic costs. It is desirable to evaluate the cost effectiveness of different roofing technologies, especially in the tropical climate.This work analyzes the heat gains of concrete-based roofs combined with different roofing technologies, as well as the cost effectiveness of these technologies in the tropical climate of Singapore. The transient roof temperatures and heat transmissions are predicted using Complex Fast Fourier Transform (CFFT) method, and the impacts of roof ventilation on heat gain are predicted using correlations proposed for convective resistance prediction via computational fluid dynamics (CFD) simulation. The daily heat gains of different roof components are hence predicted, and Life-cycle Cost Analysis (LCCA) is performed to evaluate the payback periods of different roofing technologies, including cool paint, expanded polystyrene foam (EPS), radiant barrier (RB), and roof (natural and forced) ventilation. It is concluded that the application of cool paint on unventilated roof shows the shortest payback period, and the combined use of RB and natural ventilation yields the largest energy savings in the long run. Compared with forced ventilated roofs, those passive roof technologies (cool paint, RB, air gap and EPS foam) without electricity requirement are more recommended, due to their cost effectiveness.

Life Cycle Analysis of Cool Roof in Tropical Areas

In this work, the Complex Fast Fourier Transform (CFFT) method is introduced to predict the roof temperature and heat gain in the tropical country of Singapore. The cost-effectiveness of cool paint and roof ventilation are evaluated through life-cycle analysis. Cool paint and roof ventilation can provide annual cooling energy savings of 33-57 USD/m2 for the top-floor residential units. The payback period of cool paint is shorter than 2 months in unventilated roof and shorter than 6 months in ventilated roof. Both cool paint and roof ventilation are very energy-efficient and cost-effective in tropical climate.

Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT

In this paper we analyze the power consumption and energy efficiency of general matrix-matrix multiplication (GEMM) and Fast Fourier Transform (FFT) implemented as streaming applications for an FPGA-based coprocessor card. The power consumption is measured with internal voltage sensors and the power draw is broken down onto the systems components in order to classify the energy consumed by the processor cores, the memory, the I/O links and the FPGA card. We present an abstract model that allows for estimating the power consumption of FPGA accelerators on the system level and validate the model using the measured kernels. The performance and energy consumption is compared against optimized multi-threaded software running on the POWER7 host CPUs. Our experimental results show that the accelerator can improve the energy efficiency by an order of magnitude when the computations can be undertaken in a fixed point format. Using floating point data, the gain in energy-efficiency was measured as up to 30 % for the double precision GEMM accelerator and up to 5 × for a 1k complex FFT.

Parameter estimation of manoeuvring targets based on segment integration and Lv's transform

In this paper, the received signal in a range cell is modelled as a multi-component linear frequency-modulated (LFM) signal after range compression and motion compensation, and a new method based on segment integration and Lv's transform (LVT) is introduced for parameter estimation of LFM signals over long observation interval. In this method, the LFM signals are firstly divided into segments and fast Fourier transform (FFT) is then applied within each signal segment. After that, the same frequency resolution bins of each segment are selected to construct new series and inter-segment LVT is implemented to obtain the parameter estimates. The criteria to choose the number of segments, output signal-to-noise ratio, computational complexity and memory cost are analysed in detail for this new approach. This method is fast and able to obtain the accurate parameter estimates by using the complex multiplications and FFT. Comparisons with other popular methods, LVT, maximum-likelihood estimation and fractional Fourier transform are performed. Experimental results demonstrate the proposed method is capable of obtaining the accurate parameter estimates with low computational burden and storage memory, making it suitable to be applied in memory-limited and real-time processing systems.

Development and realization of a novel type of high-speed windowed complex FFT processor

Fast Fourier transform (FFT) is a key algorithm for the real-time tracking and processing of the space-borne ocean radar altimeter. In order to put the complex data into three operations in sequence as multiplying the window, performing FFT, and computing module-square, and also meeting the requirements of high-speed digital signal processing, a novel scheme for implementing FFT with digital signal processing (DSP) C6701 is proposed in this paper. Firstly, Radix-4 algorithm of decimation in time (DIT) is adopted. Then, the improved bit-reverse algorithm is utilized for decreasing the calculation quantum. Pipeline and paralleled pattern are also considered conjointly. Based on these improvements, real-time and precision are all ensured, and the balance of calculation, communication and storage is also well weighted. Finally, a novel approach of flash programming by gel file and second boot loader is adopted, and by using this method, the format conversion of COFF file to hex file is not needed. Compared with MATLAB 6.5, the simulation and system application results all demonstrate the feasibility and effectiveness of this proposed scheme. Furthermore, the design can not only helps following real-time tracking on echo signal of Chinese national HY-2 satellite altimeter, but also provides beneficial engineering experience for FFT implementation in the other embedded systems of DSP.

A yield improvement technique in severe process, voltage, and temperature variations and extreme voltage scaling

Drastic yield reduction at sub/nearthreshold voltage domains, caused by the severe process, voltage, and temperature (PVT) variations in this region, is challenging characteristic of recent nanometre sensory chips. Using a variation sensitive and ultra-low-power design, this paper proposes a novel technique capable of sensing and responding to PVT variations by providing an appropriate forward body bias (FBB) so that the delay variations and timing yield of whole system as well as energy-delay product (EDP) are improved. Theoretical analysis for the error probability, confirmed by post-layout HSPICE simulations for an 8-bit Kogge–Stone adder and also two large Fast Fourier Transform (FFT) processors, shows considerable improvements in severe PVT variations and extreme voltage scaling. For this adder, for example, the proposed technique can reduce error rate from 50% to 1% at 0.4V. In another implementation, in average ∼7× delay variation and ∼4× EDP improvement is gained after this technique is applied to an iterative 1024pt, radix 4, complex FFT while working in sub/nearthreshold voltage region of 0.3V–0.6V. Also, pipelined version of the FFT consumed only 412pJ/FFT at 0.4V while processing 125K FFT/sec.

Thermal performance of concrete-based roofs in tropical climate

Abstract In this work, an analytical Complex Fast Fourier Transform (CFFT) method is used and modified to predict the transient roof temperature and transmitted heat flux through the multilayer roofs of naturally ventilated rooms. A field experiment is carried out on two full-scale roofs to validate the CFFT model. The mean bias error (MBE) and cumulative variation of root mean square error (CVRMBE) in the ceiling temperature prediction using CFFT model are found less than 4% during both sunny and rainy days. After validation, a parameter study is conducted to investigate the impacts of rooftop surface solar reflectivity (from 0.1 to 0.9) and thermal resistance (from 0.1 to 2.5 m 2 K/W) on the thermal performance of two types of concrete-based roofs, namely the unventilated and ventilated roofs. Compared to the roofs with solar reflectivity of 0.1, increasing the solar reflectivity by 0.1 reduces the daily heat gain by 11% in both the unventilated and ventilated roofs during a typical weather day in Singapore. Compared with the unventilated roofs, the individual uses of roof ventilation and 2.5-cm expanded polystyrene (EPS) foam insulation reduce the daily roof heat gain by 42% and 68% respectively, and the daily roof heat gain reductions increase to 73% and 84% in the ventilated roofs incorporated with 2.5-cm EPS foam and radiant barrier respectively.

Parallel Implementation of 1-D Complex FFT Using Multithreading and Multi-Core Systems

 Abstract—Now-a-days most desktop PCs have multiprocessing technology such as Hyper-Threading (HT), Dual-Core, and Quad-Core processors. Technological developments in microprocessor design have enabled hardware vendors to put multiple cores on a single socket. The main idea is to build software applications that can fully exploit the capabilities of a multi-core system using multithreading approach for faster performance. The aim of this paper is to show the performance enhancement in terms of execution time using multiple threads. This involves executing sequential software application followed by multithreaded software application on Intel based multi-core systems. 1-D complex Fast Fourier Transform (FFT) function has been taken from an open source library, called FFTw, as an example to prove the concept. Finally results show the decrease in execution time with increase in FFT sizes for a multithreaded software application on a multi-core system.

A Pipelined FFT Architecture for Real-Valued Signals

This paper presents a new pipelined hardware architecture for the computation of the real-valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the reduced number of operations of the RFFT with respect to the complex fast Fourier transform (CFFT), and requires less area while achieving higher throughput and lower latency. The architecture is based on a novel algorithm for the computation of the RFFT, which, contrary to previous approaches, presents a regular geometry suitable for the implementation of hardware structures. Moreover, the algorithm can be used for both the decimation in time (DIT) and decimation in frequency (DIF) decompositions of the RFFT and requires the lowest number of operations reported for radix 2. Finally, as in previous works, when calculating the RFFT the output samples are obtained in a scrambled order. The problem of reordering these samples is solved in this paper and a pipelined circuit that performs this reordering is proposed.

Design of 16-point Radix-4 Fast Fourier Transform in 0.18µm CMOS Technology

This paper introduces detail design of semi-custom CMOS Fast Fourier Transform (FFT) architecture for computing 16-point radix-4 FFT. FFT is one of the most widely used algorithms in digital signal processing. It is used in many signal processing and communication application as an important block for various multi-carrier systems such as for WLAN (Wireless local area network). This paper describes the design of an ASIC (Application Specific Integrated Circuit) CMOS FFT processor for 16-point radix-4 complex FFT computation, realized utilizing 0.18µm standard CMOS technology. Fixed point data format is preferred in comparison of floating point data format for a shorter dynamic range and reduced hardware utilization; thus, catering to the needs of portability. Furthermore, computations results at particular stage are rounded to avoid overflow issue and to be stored in register. The computation speed of the design is observed to be 50MHz after the synthesis process. Compared to traditional radix-4 algorithm the architecture proposed for 16-point FFT results in 1.73% of power saving and 5.5% of area reduction.

Efficient 2D FFT implementation on mediaprocessors

We have developed an efficient implementation to compute the 2D fast Fourier transform (FFT) on a new very long instruction word programmable mediaprocessor. Using instruction-level parallelism and a multimedia instruction set, our radix-4 Cooley–Tukey algorithm optimally maps the FFT computation to the processing resources of the Hitachi/Equator’s MAP mediaprocessor. We have also achieved more efficient data I/O and lower data transfer time compared to traditional implementations by processing several columns in parallel during the column-wise stage of row–column decomposition. We used a programmable direct memory access engine and a double-buffering scheme in the data cache to perform the computation and the data transfer in parallel. Our implementation resulted in 22.4 ms total execution time for a 512 × 512-point 2D complex FFT, which is faster than previous single-chip programmable or dedicated solutions. The implementations on two other mediaprocessors, the TriMedia TM1100 and the BOPS ManArray, illustrate the importance of the instruction set architecture for achieving high performance and the trend of data I/O becoming the limitation on the 2D FFT performance in newer mediaprocessors.

COBRA: a 100-MOPS single-chip programmable and expandable FFT

This paper presents an optimized column fast Fourier transform (FFT) architecture, which utilizes bit-serial arithmetic and dynamic reconfiguration to achieve a complete overlap between computation and communication. As a result, for a clock rate of 40 MHz, the system can compute a 24-b precision 1K point complex FFT transform in 9.2 /spl mu/s, far surpassing the performance of any existing FFT systems.

A low-power, high-performance, 1024-point FFT processor

This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 /spl mu/m (L/sub poly/=0.6 /spl mu/m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 /spl mu/s while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.

A CORDIC processor for FFT computation and its implementation using gallium arsenide technology

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 /spl mu/m gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 /spl mu/s, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations, Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor, The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors.

An extensible complex fast Fourier transform processor chip for real-time spectrum analysis and measurement

This paper describes in detail the design of a CMOS custom fast Fourier transform (FFT) processor for computing a 256-point complex FFT. The FFT is well-suited for real-time spectrum analysis in instrumentation and measurement applications. The FFT butterfly processor reported here consists of one parallel-parallel multiplier and two adders. It is capable of computing one butterfly computation every 100 ns thus it can compute a 256-point complex FFT in 102.4 /spl mu/s excluding data input and output processes.

A 64-point Fourier transform chip for video motion compensation using phase correlation

Details of a new low power fast Fourier transform (FFT) processor for use in digital television applications are presented. This has been fabricated using a 0.6-/spl mu/m CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8/spl times/8 mm/sup 2/ and dissipates 1 W. The chip design is based on a novel VLSI architecture which has been derived from a first principles factorization of the discrete Fourier transform (DFT) matrix and tailored to a direct silicon implementation.