Design of 16-point Radix-4 Fast Fourier Transform in 0.18Âµm CMOS Technology

Siva Kumar Palaniappa,Tun Zainal Azni Zulki

doi:10.3844/ajassp.2007.570.575

Abstract

This paper introduces detail design of semi-custom CMOS Fast Fourier Transform (FFT) architecture for computing 16-point radix-4 FFT. FFT is one of the most widely used algorithms in digital signal processing. It is used in many signal processing and communication application as an important block for various multi-carrier systems such as for WLAN (Wireless local area network). This paper describes the design of an ASIC (Application Specific Integrated Circuit) CMOS FFT processor for 16-point radix-4 complex FFT computation, realized utilizing 0.18µm standard CMOS technology. Fixed point data format is preferred in comparison of floating point data format for a shorter dynamic range and reduced hardware utilization; thus, catering to the needs of portability. Furthermore, computations results at particular stage are rounded to avoid overflow issue and to be stored in register. The computation speed of the design is observed to be 50MHz after the synthesis process. Compared to traditional radix-4 algorithm the architecture proposed for 16-point FFT results in 1.73% of power saving and 5.5% of area reduction.

Highlights

W n N = exp−2π N jn which reduce the computationalThe Discrete Fourier Transform (DFT) plays a significantly important role in many applications of digital signal processing
It has been applied in a wide range of fields such as linear filtering, spectrum analysis, digital video broadcasting and orthogonal frequency demodulation multiplexing (OFDM)
Controller: The Fast Fourier Transform (FFT) processor event is determined by the control circuit depending on the feedback it receives from the surrounding unit

Summary

INTRODUCTION

The Discrete Fourier Transform (DFT) plays a significantly important role in many applications of digital signal processing. The rapidly increasing demand of OFDMbased applications, including modern wireless telecommunication such as LAN, needs real-time high speed computation in Fast Fourier Transform algorithm This has made the design of FFT processor a critical requirement for the up coming wireless technology[1]. Several architectures have been proposed based on CooleyTurkey algorithm to further reduce the computation complexity, including radix-4, radix-2, and split-radix This Fast Fourier Transform algorithm use Divide-and-Conquer approach to divide the computation recursively and extract as many common twiddle factors as possible. The total number of complex addition/subtraction is reduced to Nlog2N, which is identical to the radix-2 algorithm This approach saves 33% of adders/subtract required. To reduce the addition/subtraction of the radix-4 design, matrix of the linear transformation is used as follows: Circuit Implementation: The radix-4 16-point FFT was designed using verilog code and simulated in NcVerilog Cadence in order to verify its functionality.

Controller

Butterfly Architecture

Design

CONCLUSION