Chip Complexity Research Articles

One-Step Generation and Purification of Cell-Encapsulated Hydrogel Microsphere With an Easily Assembled Microfluidic Device.

Cell-laden hydrogel microspheres with uniform size show great potential for tissue repair and drug screening applications. Droplet microfluidic systems have been widely used for the generation of cell-laden hydrogel microspheres. However, existing droplet microfluidic systems are mostly based on complex chips and are not compatible with well culture plates. Moreover, microspheres produced by droplet microfluidics need demulsification and purification from oil, which requires time and effort and may compromise cell viability. Herein, we present a simple one-step approach for producing and purifying hydrogel microspheres with an easily assembled microfluidic device. Droplets were generated and solidified in the device tubing. The obtained hydrogel microspheres were then transferred to a tissue culture plate filled with cell culture media and demulsified through evaporation of the oil at 37°C. The removal of oil caused the gelled microspheres to be released into the cell culture media. The encapsulated cells demonstrated good viability and grew into tumor spheroids in 12–14 days. Single cell-laden hydrogel microspheres were also obtained and grown into spheroid in 14 days. This one-step microsphere generation method shows good potential for applications in automated spheroid and organoid cultures as well as drug screening, and could potentially offer benefits for translation of cell/microgel technologies.

Performance Monitoring Counter Based Intelligent Malware Detection and Design Alternatives

Hardware solutions for malware detection are becoming increasingly important as software-based solutions can be easily compromised by intelligent malware. However, the cost of hardware solutions including design complexity and dynamic power consumption cannot be ignored. Many of the existing hardware solutions are based on statistical learning blocks with abnormal features of system calls, network traffics, or processor behaviors. Among those solutions, the performance of the learning techniques relies primarily on the quality of the training data. However, for the processor behavior-based solutions, only a few behavioral events can be monitored simultaneously due to the limited number of PMCs (Performance Monitoring Counters) in a processor. As a result, the quality and quantity of the data obtained from architectural features have become a critical issue for PMC-based malware detection. In this paper, to emphasize the importance of selecting architectural features for malware detection, the statistical differences between malware workloads and benign workloads were characterized based on the information from performance counters. Most malware can easily be detected with basic characteristics, but some malware types are statistically very similar to benign workloads which need to be handled more in-depth. Hence, we focus on multiple steps to investigate critical issues of PMC-based malware detection: (i) statistical characterization of malware; (ii) distribution-based feature selection; (iii) trade-off analysis of detection time and accuracy; and (iv) providing architectural design alternatives for hardware-based malware detection. Our results show that the existing number of performance counters is not enough to achieve the desired accuracy. For more accurate malware detection in real-time, we propose both accuracy improvement schemes (with additional PMCs, etc.) and hardware acceleration schemes. Both schemes provide accuracy improvement (5~10%) and detection speedup (up to 10%) with the additional hardware cost (less than 1% of the chip complexity).

Rapid antimicrobial susceptibility profiling using impedance spectroscopy

The present antibiotic susceptibility testing (AST) techniques based on bacterial culture, gene amplification and mass spectrometry are highly time consuming, labour intensive or expensive. Impedance spectroscopy is an emerging tool for rapid bacterial analysis as it is label-free, real-time, affordable and high-throughput. The over-reliance of this technique on complex chip designs and cell enrichment strategies has, however, slowed its foray into clinical AST. We demonstrate a label-free approach in which a low conductivity zwitterionic buffer is used for boosting impedance sensitivity in simple interdigitated electrodes (IDEs) allowing rapid AST in just 20 min without any liquid flow, biofunctionalization or cell enrichment steps. The detection principle relies on measuring changes in solution resistance due to antibiotic-induced bacterial cell death or growth. While the death-based approach is faster (20 min), it's restricted to surface-acting bactericidal antibiotics. The cell growth approach is longer (60–80 min) but more versatile as it applies to all drug types. Results for antibiotic sensitivity analysis and minimum inhibitory concentration (MIC) determination are illustrated for Escherichia coli, Klebsiella pneumoniae and Staphylococcus aureus against a wide class of antibiotics (penicillins, cephalosporins, polymyxins, carbapenems etc.).

Microfluidic droplet detection via region-based and single-pass convolutional neural networks with comparison to conventional image analysis methodologies

As the complexity of microfluidic experiments and the associated image data volumes scale, traditional feature extraction approaches begin to struggle at both detection and analysis pipeline throughput. Deep-neural networks trained to detect certain objects are rapidly emerging as data gathering tools that can either match or outperform the analysis capabilities of the conventional methods used in microfluidic emulsion science. We demonstrate that two types of neural-networks, You Only Look Once (YOLOv3, YOLOv5) and Faster R-CNN, can be trained on a dataset which comprises of droplets generated across several microfluidic experiments and systems. The latitude of droplets used for training and validation, produce model weights which are easily transitive to emulsion systems at large, while completely circumventing any necessity of manual feature extraction. In flow cell experiments which comprised of greater than either 10,000 mono- or polydisperse droplets, the models show excellent or superior statistical symmetry to classical implementations of the Hough transform or widely utilized ImageJ plugins. In more complex chip architectures which simulate porous media, the produced image data typically requires heavy pre-processing to extrapolate valid data, where the models were able to handle raw input and produce size distributions with accuracy of ± 2μm for intermediate magnifications. This data harvesting fidelity is extended to foreign datasets not included in the training such as micrograph observation of various emulsified systems. Implementing these neural networks as the sole feature extraction tools in these microfluidic systems not only makes the data pipelining more efficient but opens the door for live detection and development of autonomous microfluidic experimental platforms due to inference times of greater than 100 frames per second.

Configurable 3D Printed Microfluidic Multiport Valves with Axial Compression.

In the last decade, the fabrication of microfluidic chips was revolutionized by 3D printing. It is not only used for rapid prototyping of molds, but also for manufacturing of complex chips and even integrated active parts like pumps and valves, which are essential for many microfluidic applications. The manufacturing of multiport injection valves is of special interest for analytical microfluidic systems, as they can reduce the injection to detection dead volume and thus enhance the resolution and decrease the detection limit. Designs reported so far use radial compression of rotor and stator. However, commercially available nonprinted valves usually feature axial compression, as this allows for adjustable compression and the possibility to integrate additional sealing elements. In this paper, we transfer the axial approach to 3D-printed valves and compare two different printing techniques, as well as six different sealing configurations. The tightness of the system is evaluated with optical examination, weighing, and flow measurements. The developed system shows similar performance to commercial or other 3D-printed valves with no measurable leakage for the static case and leakages below 0.5% in the dynamic case, can be turned automatically with a stepper motor, is easy to scale up, and is transferable to other printing methods and materials without design changes.

Detector-Free Photothermal Bar-Chart Microfluidic Chips (PT-Chips) for Visual Quantitative Detection of Biomarkers.

The volumetric bar-chart microfluidic chips (V-Chips) driven by chemical reaction-generated gas provide a promising platform for point-of-care (POC) visual biomarker quantitation. However, multiple limitations are encountered in conventional V-Chips, such as costly and complex chip fabrication, complicated chip assembly, and imprecise controllability of gas production. Herein, we introduced nanomaterial-mediated photothermal effects to V-Chips, and for the first time developed a new type of V-Chip, photothermal bar-chart microfluidic chip (PT-Chip), for visual quantitative detection of biochemicals without any bulky and costly analytical instruments. Immunosensing signals were converted to visual readout signals via photothermal effects, the on-chip bar-chart movements, enabling quantitative biomarker detection on a low-cost polymer hybrid PT-Chip with on-chip scale rulers. Four different human serum samples containing a prostate-specific antigen (PSA) as a model analyte were detected simultaneously using the PT-Chip, with a limit of detection of 2.1 ng/mL, meeting clinical diagnostic requirements. Although no conventional signal detectors were used, it achieved comparable detection sensitivity to absorbance measurements with a microplate reader. The PT-Chip was further validated by testing human whole blood without the color interference problem, demonstrating the good analytical performance of our method even in complex matrices and thus the potential to fill the gap in current clinical diagnostics that is incapable of testing whole blood. This new PT-Chip driven by nanomaterial-mediated photothermal effects opens a new horizon of microfluidic platforms for instrument-free diagnostics at the point-of-care.

A machine learning method for hardware Trojan detection on real chips

Due to the global supply chain of integrated circuits (IC) from design to application, Hardware Trojan (HT) may be stealthily inserted into ICs. The effect of HT detection methods are related to the signal-to-noise ratio (SNR) and the Trojan-to-circuit ratio (TCR). Various HT detection methods are designed to target at simulated circuits; however, the effect on real chips is not involved. In the light of detection of HT on real chips with low SNR and low TCR, a machine learning method is proposed and experimented in this paper. It is difficult to directly distinguish the insignificant effect of HT on a modern complex chip. The proposed method extracts statistic features to explore the much rich expression of HT signals and adjusts the distance of different features to separate Trojan circuits from the security ones far apart. The proposed methods are tested on real chips with 10−5 TCR and demonstrated the effect compared to other state-of-the-art methods.

Analysis of Scanning Acoustic Microscopy Problems for Plastic Encapsulated Microcircuits with Complex Structure

In order to keep up with the development trend of plastic encapsulated technology and effectively improve the Scanning Acoustic Microscopy (SAM) capability of Plastic Encapsulated Microcircuits (PEMs) with complex structure, the structural characteristics of complex packaging devices, the limitations of ultrasonic technology and the applicability of testing standards are systematically studied. The influence of complex package structure and chip coated structure on SAM detection is analysed. The influence of the limitation of ultrasonic technology on the thickness and number of layers of PEMs is studied. Finally, the applicability of SAM test standards is discussed. Through the research, many problems in the SAM detection of PEMs with complex structures are pointed out, and some test requirements and suggestions on test standards are given.

Survey on Microprocessor Agile Design Methodology and Technology

<p indent=0mm>The era of Dennard scaling and Moore’s law is coming to an end. As a result, it is more and more important to improve the performance of microprocessors through novel domain specific architectures. The growing complexity of domain specific architectures leads to a design productivity crisis, which stimulates the development of new tools and methodologies to enable the completion of complex chip designs on schedule and within budget for specific domain requirements. The global research practices gradually show that the microprocessor agile design methodology is an effective solution to the design productivity crisis. This survey first briefly discusses the essence of agile design methodology and the possibility of applying it to microprocessor design by comparing the characters between software and hardware designs. Then the paper reviews the main research work in recent years and shows the research status and development trends. Finally, we give some suggestions on the potential research directions for the near future.

Parametric modeling of uncut chip geometry for predicting crater wear in gear skiving

In gear skiving, tool wear is one of the primary issues owing to the large thermomechanical cutting load. However, the effective rake angle and depth-of-cut can vary continuously throughout a single cut, leading to a complex uncut chip geometry that significantly hinders the understanding of the cutting characteristics and adds further difficulty to the prediction of tool wear. This study proposes a parametric modeling method for calculating the uncut chip geometry for each cutting pass. Developments in the rake angle and depth-of-cut (as subjected to an uncut chip) were comprehensively investigated with an aim to advance the understanding of the cutting characteristics during a single cut. Based on the uncut chip geometry, the crater wear was successfully predicted using the derived stress and temperature data, followed by a single-tooth skiving wear test verification. By comparing numerical and experimental results for crater wear, an error of less than 5 % was obtained in both depth and area. The proposed method provides a non-CAD/CAM-engine-software/environment-based alternative for calculating the process of an uncut chip geometry, clearly advancing the flexibility in further potential applications such as cutting parameter optimization and cutter design.

Nanolithography toolbox—Simplifying the design complexity of microfluidic chips

Microfluidic devices typically require complex shapes such as funnels, spirals, splitters, channels with different widths, or customized objects of arbitrary complexity with a smooth transition between these elements. Device layouts are generally designed by software developed for the design of integrated circuits or by general computer-aided design drawing tools. Both methods have their limitations, making these tasks time consuming. Here, a script-based, time-effective method to generate the layout of various microfluidic chips with complex geometries is presented. The present work uses the nanolithography toolbox (NT), a platform-independent software package, which employs parameterized fundamental blocks (cells) to create microscale and nanoscale structures. In order to demonstrate the functionality and efficiency of the NT, a few classical microfluidic devices were designed using the NT and then fabricated in glass/silicon using standard microfabrication techniques and in poly(dimethylsiloxane) using soft lithography as well as more complex techniques used for flow-through calorimetry. In addition, the functionality of a few of the fabricated devices was tested. The powerful method proposed allows the creation of microfluidic devices with complex layouts in an easy way, simplifying the design process and improving design efficiency. Thus, it holds great potential for broad applications in microfluidic device design.

Microfluidic Chip for Trapping Magnetic Nanoparticles and Heating in Terms of Biological Analysis

In this study, we reported the results of the design and the fabrication a planar coil in copper (square, a = 10 mm, 15mm high, 90 turns), these planar coils were integrated in a microfluidic chip for trapping magnetic nanoparticles and local heating applications. A small thermocouple (type K, 1 mm tip size) was put directly on top of the micro-channel in poly(dimethyl-siloxane) in order to measure the temperature inside the channel during applying current. The design of planar coils was based on optimizing the results of the magnetic calculation. The most suitable value of the magnetic field generated by the coil was calculated by ANSYS® software corresponded to the different distances from the coil surface to the micro-channel bottom (magnetic field strength Hmax = 825 A/m). The magnetic filed and heating relationship was balanced in order to manipulating the trapping magnetic nanoparticles and heating process. This design of the microfluidic chip can be used to develop a complex microfluidic chip using magnetic nanoparticles.

Influence of the Rake Angle on Nanocutting of Fe Single Crystals: A Molecular-Dynamics Study

Using molecular dynamics simulation, we study the cutting of an Fe single crystal using tools with various rake angles α . We focus on the (110)[001] cut system, since here, the crystal plasticity is governed by a simple mechanism for not too strongly negative rake angles. In this case, the evolution of the chip is driven by the generation of edge dislocations with the Burgers vector b = 1 2 [ 111 ] , such that a fixed shear angle of ϕ = 54.7 ∘ is established. It is independent of the rake angle of the tool. The chip form is rectangular, and the chip thickness agrees with the theoretical result calculated for this shear angle from the law of mass conservation. We find that the force angle χ between the direction of the force and the cutting direction is independent of the rake angle; however, it does not obey the predictions of macroscopic cutting theories, nor the correlations observed in experiments of (polycrystalline) cutting of mild steel. Only for (strongly) negative rake angles, the mechanism of plasticity changes, leading to a complex chip shape or even suppressing the formation of a chip. In these cases, the force angle strongly increases while the friction angle tends to zero.

Low-deformation precision thermal bonding of nanostructured microfluidic chips

Polymer bonding is widely employed in thermal welding, ultrasonic welding, laser welding, and surface-activated bonding. To adapt bonding properties to the smaller microstructure and complexity of a microfluidic chip, the bonding process should produce low polymer structure deformation and strong bonding strength. To fabricate a microfluidic chip without an adhesive layer, a new precision polymer bonding process that employs a nanostructure and two different layers of the same polymer material with different glass transition temperatures (Tg) is devised. Low-temperature bonding (less than 20 °C) was achieved. A deformation ratio of 1.1% was obtained, which is 10 times smaller than that for the typical thermal-bonding process. Thus, a precision bonding technique for a low-deformation microstructured chip was successfully developed.

HPPT-NoC: A Dark-Silicon Inspired Hierarchical TDM NoC with Efficient Power-Performance Trading

Networks-on-chip (NoCs) acquired substantial advancements as the typical solution for a modular, flexible and high performance communication infrastructure coping with the scalable Multi-/Manycores technology. However, the increasing chip complexity heading towards thousand cores, together with the approaching dark-silicon era, puts energy efficiency as an integral design key for future NoC-based multicores, where NoCs are significantly contributing to the total chip power. In this paper, we propose HPPT-NoC, a dark-silicon inspired energy-efficient hierarchical TDM NoC with online distributed setup-scheme. The proposed network makes use of the dim silicon parts of the chip to hierarchically connect quad-routers units. Normal routers operate at full-chip-frequency at high supply level, and hierarchical routers operate at half-chip-frequency and lower supply voltage with adequate synchronization. Routers follow a proposed TDM architecture that separates the datapath from the control-setup planes. This allows separate clocking and operating supplies between data and control and to keep the control-setup as a single-slot-cycle design independent of the datapath slot size. The proposed NoC architecture is evaluated versus a base NoC from the state-of-the-art in terms of performance and hardware results using Synopsys VCS and Synopsys Design Compiler for SAED90nm and SAED32nm technologies. The obtained results highlight the power-frequency-trading feature supported by the proposed hierarchical NoC through the configurable data-control clock relation and maintained over the different technology nodes. With the same power budget of the base NoC, the proposed architecture provides up to 74% setup latency enhancement, 32% increased NoC saturation load, and 21% higher success rates, offering up to 78% improved power delay product. On the other hand, with 38% power savings, the proposed NoC provides up to 37% enhanced latency and 15% higher success rates, with 72% enhanced power delay product. The proposed design consumes almost double the area of the base NoC, however with an average of 56% under-clocked (dim) silicon area operating at half to quarter the maximum chip frequency. This results in reduced power density as a main concern in the dark-silicon era down to 24% of the base NoC.

Glycoprotein fluorescent speed sensing by newly-synthesized boronic complex probe and chip supramolecular electrophoresis

In this work, we proposed the concept of fluorescent speed sensing (FSS) of glycoprotein in chip supramolecular electrophoresis (CSE). To achieve a stable FSS run, we firstly synthesized a novel boronic acid-based diben-zoxanthene receptor (Rp3) by a simple one-pot reaction and the complex probe of F1@Rp3 containing Rp3 and fluorescein (F1), and performed a series of experiments to assess the complex probe's ability for recognition of saccharides and glycoproteins. Secondly, we revealed the mechanism of 'balance electromigration of supramolecular complex probe' in FSS and developed the relevant theory of FSS via a series of theoretical derivation. The FSS theory showed that the moving speed of F1 was a function of glycoprotein content, indicating a novel model of glycoprotein sensing. To demonstrate the validity and utility of developed model and theory, IgG and ovalbumin were selected as model glycoproteins for the relevant experiments. The results verified the validity of FSS concept to glycoprotein assay with good accuracy (less than 6.33 % difference from standard HPLC method), stability (less than 6.04 % RSD) and linearity (higher than R2 = 0.99) as well as fair sensitivity (8.48 ng). Finally, the FSS was successfully used for the analysis of HbA1c (a key biomarker in diabetes blood). The developed FSS concept and complex probe have great potential for glycoprotein sensing, particularly for the diagnosis of diabetes.

Test yield and quality analysis models of chips

ABSTRACTIn this work, we utilized a digital integrated-circuit (IC) testing model (DITM), based on a statistical simulation method, to evaluate the test yield and test quality of semiconductor products. A circuit or chip has multiple parameters and the relationships among these parameters at different levels are complicated. To simply express numerous and complex interrelated IC or chip manufacturing and testing parameters, we assumed a normal distribution of manufacturability and then standardized and related all other parameters. On applying the Digital integrated circuit testing model (DITM) to data on Accuracy Requirements in At-Speed Functional Test and International technology roadmap for semiconductors (ITRS Roadmap), the simulated results clearly indicated that when the threshold value of a quality control test is determined, the DITM can accurately and effectively predict future Yt (Test Yield).

Design and Chip Implementation of a SMI/MVDR Dual-Mode Beamformer for Wireless MIMO Communication Systems

This paper presents a low complexity chip design supporting dual-mode beamforming, i.e. sampling matrix inversion (SMI) and the minimum variance distortionless response (MVDR), for wireless Multiple-Input Multiple-Output (MIMO) communication systems. The auto-correlation matrix inversion is the critical computing kernel shared by the two beamforming schemes. To alleviate the computing complexity, the auto-correlation matrix is approximated by a Toeplitz counterpart, which can be decomposed efficiently by applying the Cholesky decomposition and the Schur algorithm. This leads to an O (N 3 ) to O (N 2 ) complexity reduction, where N is the matrix size, while preserving computing parallelism for the hardware design. In addition, a diagonal loading technique is employed to mitigate the stability problem when the matrix is ill-conditioned. Simulation results indicate that no performance loss is observed due to the algorithm simplification measures. A systolic array based mapping procedure converts the two beamforming algorithms to a unified hardware accelerator design with 80% shared circuitry. Complex-valued divisions are achieved by adopting a hardware efficient coordinate rotation digital computer (CORDIC) scheme. In chip implementation, a TSMC 90nm UTM process technology is used and the design specs largely follow the requirements of IEEE 802.11ac standard. The core size of the chip design is 0.68mm2. The measurement results show that the chip can operate up to 200MHz with a power consumption of 49.03mW. It can complete the computation of a new beamforming vector (of size 8) every 0.64us and exhibits the highest throughput among the 6 compared designs.

A Survey on the Best Choice for Modulus of Residue Code

Nowadays, the development of technology and the growing need for dense and complex chips have led chip industries to increase their attention on the circuit testability. Also, using the electronic chips in certain industries, such as the space industry, makes the design of fault tolerant circuits a challenging issue. Coding is one of the most suitable methods for error detection and correction. The residue code, as one of the best choices for error detection aims, is wildly used in large arithmetic circuits such as multiplier and also finds a wide range of applications in processors and digital filters. The modulus value in this technique directly effect on the area overhead parameter. A large area overhead is one of the most important disadvantages especially for testing the small circuits. The purpose of this paper is to study and investigate the best choice for residue code check base that is used for simple and small circuits such as a simple ripple carry adder. The performances are evaluated by applying stuck-at-faults and transition-faults by simulators. The efficiency is defined based on fault coverage and normalized area overhead. The results show that the modulus 3 with 95% efficiency provided the best result. Residue code with this modulus for checking a ripple carry adder, in comparison with duplex circuit, 30% improves the efficiency.

A Survey on the Best Choice for Modulus of Residue Code

Nowadays, the development of technology and the growing need for dense and complex chips have led chip industries to increase their attention on the circuit testability. Also, using the electronic chips in certain industries, such as the space industry, makes the design of fault tolerant circuits a challenging issue. Coding is one of the most suitable methods for error detection and correction. The residue code, as one of the best choices for error detection aims, is wildly used in large arithmetic circuits such as multiplier and also finds a wide range of applications in processors and digital filters. The modulus value in this technique directly effect on the area overhead parameter. A large area overhead is one of the most important disadvantages especially for testing the small circuits. The purpose of this paper is to study and investigate the best choice for residue code check base that is used for simple and small circuits such as a simple ripple carry adder. The performances are evaluated by applying stuck-at-faults and transition-faults by simulators. The efficiency is defined based on fault coverage and normalized area overhead. The results show that the modulus 3 with 95% efficiency provided the best result. Residue code with this modulus for checking a ripple carry adder, in comparison with duplex circuit, 30% improves the efficiency.