Abstract
This paper presents a low complexity chip design supporting dual-mode beamforming, i.e. sampling matrix inversion (SMI) and the minimum variance distortionless response (MVDR), for wireless Multiple-Input Multiple-Output (MIMO) communication systems. The auto-correlation matrix inversion is the critical computing kernel shared by the two beamforming schemes. To alleviate the computing complexity, the auto-correlation matrix is approximated by a Toeplitz counterpart, which can be decomposed efficiently by applying the Cholesky decomposition and the Schur algorithm. This leads to an O (N 3 ) to O (N 2 ) complexity reduction, where N is the matrix size, while preserving computing parallelism for the hardware design. In addition, a diagonal loading technique is employed to mitigate the stability problem when the matrix is ill-conditioned. Simulation results indicate that no performance loss is observed due to the algorithm simplification measures. A systolic array based mapping procedure converts the two beamforming algorithms to a unified hardware accelerator design with 80% shared circuitry. Complex-valued divisions are achieved by adopting a hardware efficient coordinate rotation digital computer (CORDIC) scheme. In chip implementation, a TSMC 90nm UTM process technology is used and the design specs largely follow the requirements of IEEE 802.11ac standard. The core size of the chip design is 0.68mm2. The measurement results show that the chip can operate up to 200MHz with a power consumption of 49.03mW. It can complete the computation of a new beamforming vector (of size 8) every 0.64us and exhibits the highest throughput among the 6 compared designs.
Highlights
Beamforming, known as spatial filtering, is an essential technique of array signal processing and was traditionally applied to radar systems to achieve the directional transmission/receiving of signals
DESIGN COMPARISONS In the proposed dual-mode beamformer design, the sampling matrix inversion (SMI) algorithm and the minimum variance distortionless response (MVDR) algorithm share most of the computing modules, i.e., the Autocorrelation matrix, the Schur decomposition, M matrix, g vector, diagonal loading and the SMI weight calculation
The design was carefully developed starting from the algorithm development, architecture mapping, circuit optimization to the final chip implementation
Summary
Beamforming, known as spatial filtering, is an essential technique of array signal processing and was traditionally applied to radar systems to achieve the directional transmission/receiving of signals. Beamforming controls the phase and relative amplitude of the signal at each transmitter (or receiver) for directional signal transmission (or reception). The implementation of beamforming can be achieved in the RF section or in the baseband (digital) section The former one employs a phase shifter for each antenna and requires an additional signal combiner at the receiving end [2]–[4]. It can support the combination of beamforming and digital precoding to combat the channel impairments efficiently. Signals received from each antenna are down converted to baseband, digitally sampled, and multiplied respectively with a beamforming weight, before being combined for demodulation. A beamforming module is in charge of the calculations of beamforming weights
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