Complementary Transistors Research Articles

Doping‐Free Nanoscale Complementary Carbon‐Nanotube Field‐Effect Transistors with DNA‐Templated Molecular Lithography

A comprehensive methodology that enables cost-effective and reproducible fabrication for doping-free complementary carbon-nanotube field-effect transistors with molecular-scale nanogaps is presented (see image). Incorporating top-down/bottom-up dualities, numerous SWNTs are localized at a predefined active region and interconnected via a DNA-templated nanogap.

Effects of Strained Silicon Layer on Nickel (Germano)silicide for Nanoscale Complementary Metal Oxide Semiconductor Field-Effect Transistor Device

The effects of a strained silicon layer on the thermal stability of nickel (germano)silicide for nanoscale complementary metal oxide semiconductor field-effect transistor (CMOSFET) devices are discussed in this study. Three different thicknesses, 5, 13, and 40 nm, of silicon layers on silicon germanium (SiGe) were prepared for this experiment. The effects of the silicidation rapid thermal annealing (RTA) temperature and postsilicidation annealing temperature for the different silicon layer thicknesses were studied. For comparison, a bulk silicon substrate and a SiGe substrate were also used. Silicides with the thin strained silicon layers (5 and 13 nm) on SiGe showed good thermal stability in this study. However, the other silicides using bulk silicon, 40-nm-thick silicon on SiGe, and the SiGe substrate underwent degradation due to silicide agglomeration during annealing. A SiO2 layer was found on the silicide using the SiGe substrate. In this study, several analysis methods such as four-point probe measurement, field-emission scanning electron microscopy (FE-SEM), atomic force microscopy (AFM), and Auger electron spectroscopy (AES) were used for detailed study.

Implementation and application of cellular neural networks based on single electron device

This paper realizes cellular neural networks using the characteristic of negative differential resistance of hybrid single electron transistor and complementary metallic oxide semiconductor field effect transistor structure. The main building blocks consisting of cell core circuit, A and B template circuits are designed. Then a cellular neural network (CNN) is built and its application in image processing is studied. The computer simulation shows that the designed circuits are suitable for CNN implementation owing to its simple structure, low power dissipation and fast response. It could be used to form CNN of various scales so as to further increase the density of integrated circuits.

Low power amplitude modulation detector

An AM demodulator using totem pole complementary metal oxide semiconductor transistors having a feedback to provide a common gate voltage of approximately half that across the transistors in the totem pole. The AM demodulator used in a hearing assistance device and in a programmer of a hearing assistance device.

360- W/1 mW Complementary Cross-Coupled Differential Colpitts LC-VCO/QVCO in 0.25- m CMOS

A complementary cross-coupled differential Colpitts voltage controlled oscillator (VCO) is reported. The combination of gm-boosting and the complementary transistors allows record low power integrated VCO implementation. The proposed VCO and the corresponding parallel quadrature VCO (P-QVCO) are implemented using 0.25-μm CMOS technology for 1.8 GHz operation. Measurements for the VCO and P-QVCO show phase noise of -116.8 and -117.7 dBc/Hz at 1 MHz offset, while dissipating only 0.4 and 1.1 mA from a 0.9-V supply, respectively.

Design of a Robust Analog-to-Digital Converter Based on Complementary SET/CMOS Hybrid Amplifier

As a solution to the high speed, ultralow power, and extremely compact ADC circuit block, a complementary single-electron transistor (SET)/CMOS hybrid amplifier-based analog-to-digital converter (ADC) is proposed. It is implemented with a physics-based SPICE model including nonideal effects in real Si-based SETs such as the tunnel barrier lowering effect, parasitic MOSFETs operation, and the phase shift of Coulomb oscillation by the bias of a gate other than a main control gate. Its core scheme is the combination of both the amplification of SET current by MOSFETs and the suppression of a Coulomb blockade oscillation valley current by the differential amplification. In addition, the transient operation of SET/CMOS hybrid circuit-based ADCs fully accounting for nonideal effects of real SETs is successfully demonstrated for the first time. Compared with the previous SET-based ADCs, our ADC makes features of the immunity to nonideal effects, large voltage swing of the output signal, and high load drivability.

Pentacene and ZnO hybrid channels for complementary thin-film transistor inverters operating at 2V

We report on the fabrication of complementary thin-film transistor (TFT) inverter with organic-inorganic hybrid channels. By adopting organic-pentacene p channel and inorganic-ZnO n channel, we have fabricated a model device of hybrid complementary TFT inverters at a low channel deposition temperature below 100°C. Although those p and n channels were deposited on high-temperature-processed thin gate oxide/p-Si here, our complementary device demonstrated good potentials toward air-stable logic applications, operating with an excellent voltage gain of ∼26 at 2V as well as with a dynamic response of ∼10ms.

Bias Temperature Instabilities for Low-Temperature Polycrystalline Silicon Complementary Thin-Film Transistors

The degradation mechanisms of both negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) were studied for low-temperature polycrystalline silicon complementary thin-film transistors. Measurements show that both NBTI and PBTI are highly bias dependent; however, the effect of the temperature is only functional on the NBTI stress. Furthermore, instead of interfacial trap-state generation during the NBTI stress, the PBTI stress passivates the interface trap states. We conclude that the diffusion-controlled electrochemical reactions dominate the NBTI degradation while charge trapping in the gate dielectric controls the PBTI degradation.

Low voltage complementary thin-film transistor inverters with pentacene-ZnO hybrid channels on AlOx dielectric

The authors report on the fabrication of complementary thin-film transistor (CTFT) inverters with pentacene (p type) and ZnO (n type) hybrid channels on rf-deposited AlOx dielectrics. All deposition processes were carried out on glass substrates at low temperatures (<100°C). Since our p-channel TFT showed somewhat equivalent field mobility of 0.11cm2∕Vs compared to that of the n-channel device (0.75cm2∕Vs), the hybrid CTFT inverters were designed with identical dimensions for both channels. The CTFT device demonstrated an excellent voltage gain of ∼21 with a low static power dissipation of ∼1.5nW at a low supply voltage of 7V.

Extra Bonus on Transistor Optimization with Stress Enhanced Notched-Gate Technology for Sub-90 nm Complementary Metal Oxide Semiconductor Field Effect Transistor

A simple and efficient strain engineering technique for integrating the tensile-stress contact etch stop layer (CESL) process to a notch gate has been reported in detail. The strain engineering technique utilizes slight process modifications to modulate the channel stress and implantation profile for the enhancement of performance without adding any extra process steps. Compared with the conventional vertical-gate complementary metal oxide semiconductor field effect transistor (CMOSFET) with an offset spacer, a device with a notch gate as a self-aligned offset spacer achieves an extra 7% NMOS ION enhancement. The enhancement comes from the larger channel stress induced by the tensile-stress CESL on the notch gate, and is confirmed by technology computer aided design (TCAD) simulation. Moreover, fewer interface defects (Dit) and parasitic capacitances were obtained for the notch-gate samples.

Reduction in operation voltage of complementary organic thin-film transistor inverter circuits using double-gate structures

The authors have fabricated organic inverters comprising p-type pentacene and n-type fluoroalkyl naphthalenetetracarboxylic di-imide thin-film transistors (TFTs). The TFTs have double-gate structures that independently control the threshold voltage of the p- and n-type TFTs. The mobilities of the p- and n-type transistors are 0.18 and 0.09cm2∕Vs, respectively. Both the as-manufactured p- and n-type TFTs exhibit depletion-type behavior, which can be changed to enhancement-type behavior by applying a voltage bias to the top-gate electrodes. By controlling the top-gate biases, the operation voltage of the organic inverter circuits can be systematically reduced to 5V.

CURRENT CONTROLLED PRECISION RECTIFIER CIRCUITS

A novel full-wave precision rectifier employing a single current controlled conveyor (CCCII) with three outputs, two complementary MOS transistors, and a resistor is proposed. The circuit enjoys high input impedance, current controlled output, good zero-crossing performance, and linearity. Another current controlled precision rectifier with no external resistor is also derived from the proposed circuit. RSPICE simulations using real device parameters are included to verify the proposed circuits.

Interface chemical characterization of novel W∕HfO2∕GeON∕Ge stacks

The downscaling of complementary metal-oxide semiconductor transistors requires new materials such as Ge substrates for high carrier mobility and high-k dielectrics to decrease the equivalent oxide thickness while reducing the leakage current from the channel to the gate. Photoemission and Auger electron spectroscopies are used to investigate the interfaces of the W∕HfO2∕GeON∕Ge stack. Hard x-ray photoemission spectroscopy is also used to achieve bulk sensitivity. The GeON thin interfacial layer is obtained by nitridation of the germanium native oxide. Nitridation at 480°C and 120mbars yields the highest nitrogen incorporation (nearly 20at.%). X-ray photoemission spectroscopy analysis shows the presence of Ge–Hf bonding states, indicating direct interaction between the germanium and the hafnium oxide despite the GeON passivating layer. High energy photoemission is used to probe the buried W∕HfO2 interface. No interfacial layer such as WOx is observed between W and HfO2.

Intriguing conducting properties of HfOxNy thin films prepared from the Hf[N(C2H5)2

Hafnium nitride films were prepared on the Si(100) substrates by the metal-organic chemical vapor deposition method using Hf[N(C2H5)2]4. The prepared samples were then oxidized in air, followed by rapid-thermal annealing to produce HfOxNy thin films, meanwhile the associated physical properties were investigated. The x-ray photoelectron spectroscope analysis unveiled that the composition of the films is HfOxNy. In addition, the films after the rapid-thermal annealing treatments at various temperatures revealed salient features in their physical properties, such as capacitance and conductivity. On this basis, the feasibility of using the HfOxNy layers as high-k dielectrics in complementary metal oxide semiconductor transistors was also discussed.

Influence of electron-beam and ultraviolet treatments on low-k porous dielectrics

The down scaling of complementary metal oxide semiconductor transistors requires materials such as porous low-k dielectrics for advanced interconnects to reduce resistance-capacitance delay. After the deposition of the matrix and a sacrificial organic phase (porogen), postcuring treatments may be used to create porosity by evaporation of the porogen. In this paper, Auger electron spectroscopy is performed to simultaneously modify the material (e-beam cure) and measure the corresponding changes in structure and chemical composition. X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy measurements in attenuated total reflection mode confirm the Auger results. The porogen removal and matrix cross-linking result in the formation of a Si–O–Si network under e-beam or ultra violet cure. The possible degradation of these materials, even after cure, is mainly due the presence of Si–C bonds.

Characterizing the Channel Backscattering Behavior in Nanoscale Strained Complementary Metal Oxide Semiconductor Field-Effect Transistors

This work investigates the impact of different uniaxial strain polarities on channel backscattering in nanoscale complementary metal oxide semiconductor field-effect transistor (CMOSFET). Two carrier statistics, nondegenerate and degenerate-limited, are employed to extract the channel backscattering ratio, ballistic efficiency, and related backscattering factors. While the channel length scales down and the channel stress level increases further, the modulation of channel backscattering ratio, i.e., improved (degraded) by uniaxial tensile (compressive) strain, becomes more prominent. This observation holds true under both carrier statistics, which implies that the nondegenerate case with simple mathematics can be fairly used for evaluation. In addition, the correlation between strain-enhanced mobility gain and drain current improvement is found to be predicted well by the ballistic efficiency deduced with the nondegenerate carrier statistics.

Complementary organic field effect transistors by ultraviolet dielectric interface modification

The realization of p- and n-type pentacene organic field effect transistors and an organic inverter stage is reported based on selective ultraviolet (UV) modification of the polymer dielectric in air. Apart from the UV radiation treatment, the device structures are identical. The achieved field effect carrier mobilities for both transistor types are ≈0.1cm2∕Vs. Similar performance data for both transistor types as well as an observed low current hysteresis qualify the UV treatment for organic complementary metal oxide semiconductor (O-CMOS) technology. The realized O-CMOS inverter exhibits stable operation below its supply voltage, as well as a gain of 17.

Electronic properties of ultrathin HfO2, Al2O3, and Hf–Al–O dielectric films on Si(100) studied by quantitative analysis of reflection electron energy loss spectra

Quantitative analysis of reflection electron energy loss spectra for ultrathin HfO2, Al2O3, and Hf–Al–O dielectric thin films on Si(100) were carried out by using Tougaard-Yubero [Surf. Interface Anal. 36, 824 (2004)] QUEELS-ε(k,ω)-REELS software. Experimental cross sections obtained from reflection electron energy loss spectroscopy were compared with theoretical inelastic scattering cross section Ksc deduced from the simulated energy loss function (ELF). The ELF is expressed as a sum of Drude oscillators. For HfO2, the ELF shows peaks in the vicinity of 10, 17, 22, 27, 37, and 47eV. For Al2O3, a broad peak at 22eV with a very weak shoulder at 14eV and a shoulder at 32eV were observed, while for the Al2O3 doped HfO2, the peak position is similar to that of HfO2. This indicates that when Hf–Al–O film is used as a gate dielectric in a complementary metal-oxide semiconductor transistor, its electronic structure is mainly determined by the d state of Hf. In addition, the inelastic mean free path (IMFP) was also calculated from the theoretical inelastic scattering cross section. The IMFPs at 300eV were about 7.05, 9.62, and 8.48Å and those at 500eV were 11.42, 15.40, and 13.64Å for HfO2, Al2O3, and Hf–Al–O, respectively. The method of determining the IMFP from the ELF is a convenient tool for ultrathin dielectric materials.

Single cell recordings with pairs of complementary transistors

Floating gate field-effect transistors (FETs) for the detection of extracellular signals from electrogenic cells were fabricated in a complementary metal oxide semiconductor process. Additional passivation layers protected the transistor gates from the electrolyte solution. To compare the signals from n- and p-FETs, two electronically separated, but locally adjacent transistors were combined to one measuring unit. The paired sensing area of this unit had the dimension of a single cell. Simultaneous recordings with n- and p-channel floating gate FETs from a single cell exhibited comparable amplitudes and identical time courses. The experiments indicate that both types of FETs express similar sensitivities.

Level Converting Flip-Flops for High-Speed and Low-Power Applications

This letter presents two high-performance level-convert-ing flip-flops (LCFF) for multi-VDD systems, indirect precharging flip-flop (IPFF) and multi-supply complementary pass-transistor flip-flop (MCPFF). Employing a simple precharging scheme, IPFF provides high operating speed. MCPFF, on the other hand, provides low power operations by implementing the edge-triggering function with complementary pass transistors. Performance comparison indicates that IPFF operates at the highest speed and MCPFF consumes the lowest power among the seven LCFFs under evaluation.