Complementary Transistors Research Articles

Highly Thermal Immune Nitrogen-Doped Ni–Germanosilicide with Co/TiN Double Layer for Nano-Scale Complementary Metal Oxide Semiconductor Applications

In this study, a highly thermal immune Ni–germanosilicide utilizing a 1%-nitrogen-doped nickel and a Co/TiN double capping layer is proposed for nano-scale complementary metal oxide semiconductor field effect transistors (CMOSFETs). It is shown that thermal stability of Ni–germanosilicide is improved a lot by the nitrogen incorporation in Ni–germanosilicide film using the 1%-nitrogen-doped nickel target and Co/TiN double capping layer. Even after the post-silicidation annealing at 600 °C for 30 min, low resistivity Ni–germanosilicide can be achieved. It is believed that the nitrogen atoms in 1%-nitrogen-doped nickel are incorporated in the Ni–germanosilicide during silicidation and formed a nitride compound at the grain boundaries of Ni–germanosilicide and the Ni–germanosilicide/SiGe interface.

Complementary carbon nanotube-gated carbon nanotube thin-film transistor

We introduce, a complementary carbon nanotube (CNT)-gated CNT thin-film field effect transistor (FET). By using two perpendicularly crossed single-wall CNT (SWNT) bundles as the gate and the channel interchangeably, a sub-50nm complementary CNT-FET is demonstrated. It is found that the new CNT-FET shows acceptable FET characteristics by interchanging the roles of the gate and the channel. The unique dual functionality of the device will open up a new possibility and flexibility in the design of future complementary CNT electronic circuits.

An investigation of low-frequency noise in complementary SiGe HBTs

We present a comprehensive investigation of low-frequency noise behavior in complementary (n-p-n + p-n-p) SiGe heterojunction bipolar transistors (HBTs). The low-frequency noise of p-n-p devices is higher than that of n-p-n devices. Noise data from different geometry devices show that n-p-n transistors have an increased size dependence when compared with p-n-p transistors. The 1/f noise of p-n-p SiGe HBTs was found to have an exponential dependence on the (intentionally introduced) interfacial oxide (IFO) thickness at the polysilicon-to-monosilicon interface. Temperature measurements as well as ionizing radiation were used to probe the physics of 1/f noise in n-p-n and p-n-p SiGe HBTs. A weak temperature dependence (nearly a 1/T dependence) of 1/f noise is found in both n-p-n and p-n-p devices with cooling. In most cases, the magnitude of 1/f noise is proportional to I/sub B//sup 2/. The only exception in our study is for noise in the post-radiation n-p-n transistor biased at a low base current, which exhibits a near-linear dependence on I/sub B/. In addition, in proton radiation experiments, the 1/f noise of p-n-p devices was found to have higher radiation tolerance than that of n-p-n devices. A two-step tunneling model and a carrier random-walk model are both used to explain the observed behavior. The first model suggests that 1/f noise may be caused by a trapping-detrapping process occurring at traps located inside IFO, while the second one indicates that noise may be originating from the emitting-recapturing process occurring in states located at the monosilicon-IFO interface.

Improved Gate-Edge Profile of Metal/High-k Gate Stack Using an NH[sub 3] Ashing Process in Gate-First CMOSFETs

This study analyzed an alternative ashing technology for removing photoresist in the production of gate-first complementary metal oxide semiconductor field effect transistors (CMOSFETs) with a high-k metal gate stack. NH 3 ashing is proposed as an alternative to O 2 ashing to improve the gate-edge profile. It was found that NH 3 ashing suppresses bottom oxide growth below the thin HfO 2 layer, reducing Si recesses in the source/drain active area, and eliminating bottom oxide encroachment into the gate edge. The NH 3 ashing process also makes the HfO 2 film more resistant to the wet chemistry, which reduces the high-k undercut beneath the metal gate during the high-k removal process.

Reducing AC Power Consumption by Three-Dimensional Integration of Ge-On-Insulator CMOS on 1-Poly-6-Metal 0.18 μm Si MOSFETs

We have used three-dimensional (3D) integration to reduce the ac power consumption in interconnects, which is the most severe issue beyond the dc power arising from the gate dielectric leakage current. From a direct calculation of the ac power consumption using an electromagnetic method, we show that both the ac power consumption and maximum operation frequency can be improved by integrating an additional integrated circuit layer. The 3D integration was realized by Ge-on-insulator (GOI) complementary metal oxide semiconductor field effect transistors (CMOSFETs) on 1-poly-6-metal (1P6M) Si devices, where little performance degradation was measured in the lower layer Si MOSFETs, due to the inherent low thermal budget (500°C rapid thermal anneal) of the GOI processing. The drive current of the 3D GOI n- and p-MOSFETs was more than double that of the control Si devices, providing another advantage of the approach.

New Device Structure Using Array Transistors and Flexible U-Grooves Suitable for 18-V, High-Performance SOI Complementary Bipolar LSIs

We have developed a new device structure suitable for high-performance and high-power mixed signal large scale integrations (LSIs) using 0.35-/spl mu/m SOI complementary bipolar transistors. The new structure is composed of array transistors for various operating currents and flexible U-groove (trench) layout for high-power transistors. Thermal simulation results showed that the thermal resistance could be reduced by 40% by using the flexible U-groove layout. Test structure measurements showed that the maximum operating currents of a double polysilicon self-aligned NPN transistor were improved by 2 and 3.5 times by using ballasting resistors and ballasting resistors with flexible U-groove layout, respectively. The effects of the transistor structure on the thermal resistance and the maximum operating current were discussed.

Silicon-Atom Induced Fermi-Level Pinning of Fully Silicided Platinum Gates on HfO2 Dielectrics

Fully silicided platinum gates have been proposed as metal gate electrodes for scaled complementary metal oxide semiconductor field-effect transistors (CMOSFETs). The Pt monosilicide (PtSi) phase was formed on gate dielectrics by a full silicidation reaction at 400°C. PtSi gate electrodes on SiO2 possess a high effective work function of 4.9 eV, which could be used as a possible metal gate electrode for p-MOSFETs, while at the PtSi/HfO2 interface, Fermi-level pinning is observed independent of the PtSi fabrication process. The Fermi-level pinning at the PtSi/HfO2 interface is comparable to that at the poly-Si/HfO2 interface, and Fermi-level pinning does not occur at the Pt/HfO2 interface. These results show that Fermi-level pinning is induced by the presence of silicon atoms at the HfO2 upper interface.

Carbon-Nanotube-Based Voltage-Mode Multiple-Valued Logic Design

Multivalued logic has always attracted the attention of digital system and logic designers. However, the high-performance and low-power CMOS process, which has been developed over the last two decades, has traditionally assisted successful circuit implementation of binary logic. Consequently, in spite of its large potential multivalued logic design is seldom a circuit designer's choice. This paper presents a novel method of multiple-valued logic design using carbon-nanotube field-effect transistors (CNFETs). The geometry-dependent threshold voltage of CNFETs has been effectively used to design a ternary logic family. We have developed a SPICE-compatible model of ballistic CNFETs that can account for varying geometries and operating conditions. SPICE simulations have been performed on the proposed logic gates, and the transfer characteristics as well as transient behavior have been extensively studied. Finally, a comparison in terms of power and performance of the ternary logic family vis-a/spl grave/-vis traditional complementary field-effect transistor binary logic family has been presented.

Semiconductor lasers with an inversely biased active region for generation of millimeter wave modulated signals

A semiconductor laser structure is proposed to introduce field effects in its active region. It has five layers of p-n-i-p-n with four electrical contacts to the doped layers, where the current injection into an inversely biased active region is based on the operation of two complementary bipolar transistors with their base-collector junction common. The inverse bias is useful to incorporate carrier transfer phenomena like Gunn effect in semiconductor lasers. Our analysis on the proposed lasers shows that its lasing operation is possible while applying a high electric field more than 106 V/m in the carrier transfer domain.

A Novel Approach to Compact Model Parameter Extraction for Excimer Laser Annealed Complementary Thin Film Transistors

A unified physical-based model parameter extraction technique for excimer laser annealed lower temperature polycrystalline silicon (LTPS) complementary thin film transistors (TFTs) is for the first time proposed. For two well-known compact models of LTPS TFT, Rensselaer Polytechnic Institute (RPI) V1 and V2 models, our approach sequentially optimizes the model parameters in the regions of linear, subthreshold, saturation, and leakage. Compared with the measured results, the extracted I D −V G , I D −V D , transconductance, and output conductance are within 3% of accuracy. The agreement with the experimental data is excellent for the n- and p-type LTPS TFTs with different length and width. This extraction technique bridges the fabrication of LTPS TFTs and the design of complementary system on panel circuits.

Surface chemistry and electrical properties of germanium nanowires.

Germanium nanowires (GeNWs) with p- and n-dopants were synthesized by chemical vapor deposition (CVD) and were used to construct complementary field-effect transistors (FETs). Electrical transport and X-ray photoelectron spectroscopy (XPS) data are correlated to glean the effects of Ge surface chemistry to the electrical characteristics of GeNWs. Large hysteresis due to water molecules strongly bound to GeO(2) on GeNWs is revealed. Different oxidation behavior and hysteresis characteristics and opposite band bending due to Fermi level pinning by interface states between Ge and surface oxides are observed for p- and n-type GeNWs. Vacuum annealing above 400 degrees C is used to remove surface oxides and eliminate hysteresis in GeNW FETs. High-kappa dielectric HfO(2) films grown on clean GeNW surfaces by atomic layer deposition (ALD) using an alkylamide precursor is effective in serving as the first layer of surface passivation. Lastly, the depletion length along the radial direction of nanowires is evaluated. The result suggests that surface effects could be dominant over the "bulk" properties of small diameter wires.

Influences of nonuniformity in metal concentration in gate dielectric silicate on CMIS inverters' propagation delay time

It is shown that propagation delay time in CMIS (complementary metal insulator semiconductor field effect transistor) inverters is strongly affected by dielectric constant nonuniformity in gate dielectrics caused by the phase separation in silicate films. Influences of such nonuniformity on load capacitance are studied by analytical calculations based on a physical model which takes polarization into account. It is newly found that load capacitances are affected by the phase separation in qualitatively different ways, depending on the average metal concentration of their dielectric films. An experimental result is compared with those calculations. Influences of such nonuniformity on current drivability are studied by 3-dimensional device simulations. It is also newly found that such nonuniformity affects load capacitance and current drivability in different ways, resulting in an increase in propagation delay time of CMIS inverters for all metal concentrations studied. An explanation of this phenomenon is given with physical considerations.

Complementary tunneling transistor for low power application

The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.

Growth and transport properties of complementary germanium nanowire field-effect transistors

n- and p-type Ge nanowires were synthesized by a multistep process in which axial elongation, via vapor–liquid–solid (VLS) growth, and doping were accomplished in separate chemical vapor deposition steps. Intrinsic, single-crystal, Ge nanowires prepared by Au nanocluster-mediated VLS growth were surface-doped in situ using diborane or phosphine, and then radial growth of an epitaxial Ge shell was used to cap the dopant layer. Field-effect transistors prepared from these Ge nanowires exhibited on currents and transconductances up to 850 μA/μm and 4.9 μA/V, respectively, with device yields of >85%.

Gamma-ray response of SOI bipolar junction transistors for fast, radiation tolerant front-end electronics

This paper is devoted to studying the effects of γ radiation on the electrical parameters of complementary bipolar junction transistors, part of an SOI (silicon on insulator) BiCMOS process, in view of the design of fast, rad-hard analog blocks. A survey of the total ionizing dose response has been carried out paying particular attention to its dependence on the layout and process choices. The final integrated doses are compatible with operation in the space environment and in high-energy physics experiments involving moderately high-radiation levels. The issue of enhanced low-dose rate sensitivity (ELDRS) has been addressed by a preliminary characterization of transistors exposed to 60Co sources with different activities.

Physical and Electrical Properties of W / WN x / Poly ­ Si1 − xGex ( x = 0 , 0.2 , 0.6 ) Gates Stack with Post-thermal Process

We investigated the physical and electrical properties of a gates stack with a post-thermal process for use in the high performance complementary metal oxide semiconductor field effect transistor. Under the same annealing conditions, the crystallinity of the W films degraded, and the sheet resistance of the films increased with increasing Ge content of the films. These results are attributed to the increase in surface roughness of the films, which suppressed grain growth in the W films as the Ge content of poly increased. After high temperature annealing, the grain size of the W films increased, and the crystallinity of the W films was enhanced due to a reduction of the uniform strain. The elimination of uniform strain in W films and the increase in grain size led to a decrease in the sheet resistance of the structure. In addition, no evidence of the formation of was observed even after annealing at 900°C for 30 min due to the barrier between the W film and the film. However, the N content of the films decreased by about 61% of the initial amount and accumulated below the layer, suggesting an interfacial reaction between the film and the film. As the annealing temperature increased, the amount of dopant in the poly films of the system also decreased due to boron accumulation and the formation of a boron compound (BN). © 2003 The Electrochemical Society. All rights reserved.

Physical and Electrical Properties of Polycrystalline Si1 − xGex Deposited Using Single-Wafer-Type Low Pressure CVD

Polycrystalline (poly) films have been suggested as a promising alternative to the currently employed poly silicon gate electrode for complementary metal oxide semiconductor field effect transistor technology due to lower resistivity, less boron penetration, and less gate depletion effect than that of poly Si gates. We investigated the deposition characteristics and physical properties of poly films using and as deposition source gases in single-wafer-type low pressure chemical vapor deposition (LPCVD) system and the electrical properties of MOS capacitors with the poly gate stack. Deposition rate as well as Ge content of poly films shows the large increase with the addition of a small fraction of while, above critical flux, it is slightly changed. In addition, the Ge content in poly films decreased with an increase in deposition temperature. The flatband voltage of the poly gate stack decreased by 0.3 V and gate depletion effect of poly gate stack was reduced by 18% as compared to that of the poly Si gate stack. In addition, the charge to breakdown of the poly gate stack was higher than that of poly Si gate stack. © 2003 The Electrochemical Society. All rights reserved.

A 200-v high-voltage amplifier using a parasitic field-oxide transistor for voltage feedback

A 200-V high-voltage amplifier with a 50-kHz bandwidth is built in a 10-V trench-isolated CMOS process with complementary high-voltage transistors. The high-voltage amplifier uses parasitic field-oxide transistors to dc stabilize the input-output voltage transfer characteristic. Use of parasitic field-oxide transistors for output voltage sensing provides only a small capacitive output load and eliminates the need for high-voltage resistor feedback networks. By removing resistor feedback networks, compact and low-power high-voltage amplifiers may be realized for a certain class of applications.

N-Type Dopant Activation Behaviors in Poly Si1 − xGex Films with Ge Contents and Activation Temperatures

We investigated the electrical properties and microstructures of n-type doped poly films with Ge contents using hall measurement, four-point probe, transmission electron microscopy, and energy dispersive X-ray spectrometry to apply to gate electrode of complementary metal oxide semiconductor field effect transistor. The sheet resistance of poly films implanted with arsenic decreased with the decrease of Ge content and the increase of activation temperature due to the increase of carrier mobility and activated carrier concentration. In addition, we found that the segregation of dopant increased at the grain edge and the activated carrier concentration decreased with the increase of Ge content due to higher diffusivity and lower solid solubility limit of As in poly films. © 2003 The Electrochemical Society. All rights reserved.

Properties of Polycrystalline Si1 − xGex Films Grown by Ultrahigh Vacuum CVD Using Si2 H 6 and GeH4

Polycrystalline films have been suggested as a promising alternative to the currently employed polycrystalline silicon (poly-Si) gate electrode for complementary metal oxide semiconductor field effect transistor technology due to lower resistivity, less boron penetration, and less gate depletion effect than that of poly-Si gates. We investigated the formation of poly- films by using ultrahigh vacuum chemical vapor deposition CVD with and gases, and studied their physical properties as well as electrical characteristics. The deposition rate and Ge content of poly- films increased linearly with the flux of up to a critical flux, while, above this critical flux, it is slightly changed. The resistivity of poly- films decreased as the Ge content increased, and was about one-half of that of poly-Si films at a Ge content of 45%. The capacitance-voltage measurements of metal oxide semiconductor capacitor structures with gates demonstrated that the flatband voltage of the films was lower than that of poly Si films by 0.2 V. In addition, the changes of flatband voltage with the dosage of boron and the sudden decrease of accumulation capacitance in the gate structure were investigated. Leakage current levels increased slightly due to the difference in with the increase of Ge content in poly films. © 2003 The Electrochemical Society. All rights reserved.