Complementary To Absolute Temperature Research Articles

A Highly Accurate, Polynomial-Based Digital Temperature Compensation for Piezoresistive Pressure Sensor in 180 nm CMOS Technology.

Recently, piezoresistive-type (PRT) pressure sensors have been gaining attention in variety of applications due to their simplicity, low cost, miniature size and ruggedness. The electrical behavior of a pressure sensor is highly dependent on the temperature gradient which seriously degrades its reliability and reduces measurement accuracy. In this paper, polynomial-based adaptive digital temperature compensation is presented for automotive piezoresistive pressure sensor applications. The non-linear temperature dependency of a pressure sensor is accurately compensated for by incorporating opposite characteristics of the pressure sensor as a function of temperature. The compensation polynomial is fully implemented in a digital system and a scaling technique is introduced to enhance its accuracy. The resource sharing technique is adopted for minimizing controller area and power consumption. The negative temperature coefficient (NTC) instead of proportional to absolute temperature (PTAT) or complementary to absolute temperature (CTAT) is used as the temperature-sensing element since it offers the best temperature characteristics for grade 0 ambient temperature operating range according to the automotive electronics council (AEC) test qualification ACE-Q100. The shared structure approach uses an existing analog signal conditioning path, composed of a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC). For improving the accuracy over wide range of temperature, a high-resolution sigma-delta ADC is integrated. The measured temperature compensation accuracy is within ±0.068% with full scale when temperature varies from −40 °C to 150 °C according to ACE-Q100. It takes 37 µs to compute the temperature compensation with a clock frequency of 10 MHz. The proposed technique is integrated in an automotive pressure sensor signal conditioning chip using a 180 nm complementary metal–oxide–semiconductor (CMOS) process.

A 0.5-V Supply, 36 nW Bandgap Reference With 42 ppm/°C Average Temperature Coefficient Within −40 °C to 120 °C

This paper presents a switched capacitor network (SCN)-based bandgap voltage reference (BGR) circuit designed and implemented in a 65nm standard CMOS process with a wide temperature range, high precision, low supply voltage and low power consumption for IoT device application. The proposed BGR employs a 2x charge pump with ripple optimization design to supply the ${V} _{\mathbf {EB}}$ generator, which can relax ${V} _{\mathbf {DD}}$ from 0.9V to 0.5V.A proportional to absolute temperature (PTAT) current source is proposed to bias the PNP BJT in order to reduce the nonlinearity of ${V} _{\mathbf {EB}}$ . Moreover, a voltage divider SCN with low leakage consideration to form the complementary to absolute temperature (CTAT) voltage is designed to reduce the nonlinearity of its coefficient, while a series-parallel SCN with adjusted clock swing to form the PTAT voltage is designed to improve the line regulation of the BGR. The measurement result shows that the proposed BGR has a temperature coefficient (TC) of 42 ppm/°C at 0.5V supply within −40 °C to 120 °C. The line regulation is 3.2mV/V or 0.64%/V from 0.5V to 1V. Based on 6-chip test result, it shows a $3\sigma / \mu $ variation of 3.08% before trimming, while 0.36% after trimming.

A Sub-200nW All-in-One Bandgap Voltage and Current Reference Without Amplifiers

This brief presents a low-power and high-precision bandgap voltage and current reference (BGVCR) in one simple circuit for battery-powered applications. All the amplifiers have been eliminated in the proposed circuit. The voltage reference is derived from the bandgap topology, and the current reference is obtained by summing a proportional-to-absolute-temperature (PTAT) current and a complementary-to-absolute-temperature (CTAT) current. Therefore, the temperature coefficient of the current reference can be optimized. Besides, a pseudo-cascode structure and a simple line sensitivity enhancement circuit are adopted to improve the current mirror accuracy and line sensitivity. The proposed circuit is fabricated in a 0.18-μm deep N-well CMOS process with an active area of 0.063 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured VREF and IREF are 1.2 V and 51 nA, respectively. The VREF and IREF show measured average temperature coefficients of 32.7 ppm/°C and 89 ppm/°C at a temperature of -45 to 125°C and standard deviations of 0.17 % and 1.15 %, respectively. In the supply voltage range of 2 to 5 V, the line sensitivities of voltage and current are 0.058%/V and 1.76%/V, respectively. The minimum supply voltage is 2 V with a total power consumption of 192 nW at room temperature.

A 1036-F2/Bit High Reliability Temperature Compensated Cross-Coupled Comparator-Based PUF

In this article, a compact physical unclonable function (PUF) based on cross-coupled comparator is presented. Featuring a positive feedback response generation mechanism, the mismatch in analog signals between the cross-coupled transistor pair is quickly amplified to prevent its polarity from flipping by the temporal noise. The rapid enlargement of noise margin by the sense amplifier also contributes to stabilizing the response against supply voltage variations. To improve its temperature stability, the counteracting effect of complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) drives are considered in sizing the bit cell transistors. The proposed design is fabricated in a standard 65-nm CMOS process. The bit cell occupies an area of only $4.38~\mu \text {m}^{2}$ (i.e., $1036~F^{2}$ ), and the overall PUF chip consumes 2.98 pJ/bit at the throughput of 8 Mb/s, of which only 1.61 pJ/bit is due to the PUF’s core. With the uniqueness measured to be 49.53%, the unpredictability of the fabricated PUF chips is validated by autocorrelation function and NIST randomness tests. Compared with the state-of-the-art implementations, the proposed PUF has the lowest native response instability of 1.46% with 500 repeated PUF readouts at 27 °C and 1.2 V. By varying the operating temperature from −50 °C to 150 °C in a step size of 10 °C and the supply voltage from 1.0 to 1.4 V in a step size of 0.1 V simultaneously, the average reliability of the proposed PUF obtained from the 2-D plot of all operating conditions is found to be 96.87% without correction and 99.31% with spatial majority voting (SMV).

Methods of Compensation for the Temperature Dependence of the Reference Voltage Sources of Integrated Circuits

The basic principles of reference voltage source construction are considered in the article. Possible sources of error of the output reference voltage, advantages and disadvantages of the existing architectural solutions of the reference voltage sources are analyzed. An architectural solution for the construction of a reference voltage source with higher order nonlinearities compensation is proposed, which has a temperature independent output voltage and is capable of operating at a supply voltage equal to or below 1 V. This solution has the possibility of implementing in the standard CMOS technology. Recommendations for compensation for the error caused by the offset voltage of the operational amplifier are given.In the modern world, integrated circuits (ICs) are the nucleus of virtually all electronic systems. When designing many ICs, one of the most important tasks is to generate accurate voltages for the entire circuit. The ICs that create these voltages are often referred to as the reference voltage sources. The reference voltage is a major component of both fully analog and digital circuits and even memory elements. There is a particular demand for low voltage power supplies as it is required for modern gadgets, mobile phones, laptops, cameras, etc. They should have low sensitivity to changes in power supply, possible deviations in the parameters of the manufacturing process and temperature.The reference voltage sources in standard CMOS technology have high precision output voltage, but temperature dependence is a problem. Another problem of such circuits is the inability to operate with a supply voltage below 1 V. The reasons for this are two: the principle of their operation is based on a bandgap of silicon equal to 1.25 V, which already exceeds 1 V of power; the second reason is that low voltage sources of reference voltage contain an operational amplifier, which should also operate at low power. In this case, low voltage power supply generators have poorer accuracy rates than classical implementation. Therefore, improving the characteristics of reference voltage sources while being able to operate at a supply voltage close to or below 1 V is a problem and requires a compromise solution.In the article was analyzed generators that provides proportional to absolute temperature (PTAT) voltage at their outputs, generators that provides complementary to absolute temperature (CTAT) voltage at their outputs. The source of the high-order nonlinearity was analyzed.The schematic of implementing reference voltage generators was proposed. The formulas for output voltage was derivated. The basic principles of operation of proposed schematic was described. The voltage reference, which utilizes the temperature-dependent currents generated from the parasitic n-p-n and p-n-p bipolar junction transistor devices in the CMOS process, is presented.

An 8-nW Resistor-Less Bandgap Reference Based on a Single-Branch Floating PTAT Voltage

This letter presents an ultra low-power resistor-less bandgap reference circuit, which is based on the topology of a single-branch floating proportional-to-absolute-temperature (PTAT) voltage. By using a cascode high impedance current bias technique, the single-branch PTAT voltage can be directly floating on the complementary-to-absolute-temperature (CTAT) voltage generated by the $V_{EB}$ of the bipolar transistor. Ultra low power consumption is realized by the simple topology in the proposed method, which only needs a few current branches. Fabricated in 0.13- $\mu \text{m}$ CMOS process, this letter generates a 1.252-V bandgap reference voltage. The total power consumption is 8.26 nW with a 1.4-V supply voltage. Without a resistor, this letter can achieve a small active area of 0.017 mm2. The average value of the temperature coefficient is 68 ppm/°C from −20 °C to 110 °C, and the line regulation is 0.019 %/V.

Adjustable Output CMOS Voltage Reference Design

In this brief, a CMOS voltage reference based on mutual temperature compensation using NMOS transistors of the same threshold type is advanced. The technique consists in subtracting two voltages that present similar complementary-to-absolute-temperature (CTAT) behavior, which are appropriately generated from the same threshold-type NMOS transistors operating as diodes in different inversion levels. The proposed topology provides an adjustable voltage and avoids the use of start-up drivers. The circuit design was carried out in a 180 nm CMOS process. Experimental results verified the effectiveness of the presented technique, and produced a reference voltage of 500 mV. The circuit operates with a supply voltage ranging from 1.2 V to 1.8 V, consumes $4.7~\mu \text{A}$ at 27 °C, has a temperature coefficient (TC) of 22 ppm/°C from 0 °C to 100 °C, and presents a power supply rejection ratio (PSRR) of −42 dB.

A 0.7-V 28-nW CMOS Subthreshold Voltage and Current Reference in One Simple Circuit

This paper presents a low-power and high-precision voltage and current reference (VCR) in one simple circuit. The voltage reference is derived from the threshold voltage difference between an I/O (i.e., 3.3-V NMOS) and standard (i.e., 1.8-V NMOS) transistors with temperature-independent bias current, and the current reference is the voltage reference divided by a temperature-insensitive resistor. The resistor is made up by series connection of a proportional-to-absolute-temperature (PTAT) NWELL resistor and a complementary-to-absolute-temperature (CTAT) high-resistance poly resistor in series. Implemented in a standard 0.18- $\mu \text{m}$ CMOS process, the proposed VCR circuit takes an active area of only 0.055 mm2. The measured voltage and current references ( $\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$ ) at room temperature are 368 mV and 9.77 nA, respectively. The measured average temperature coefficient (TC) of $\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$ are 43.1 ppm/°C and 149.8 ppm/°C over a temperature range of −40~125°C with one-time trimming and the variation coefficients are 0.35% and 1.6%, respectively. The measured voltage and current line sensitivities are 0.027%/V and 0.6%/V, respectively. The minimum supply voltage is 0.7 V with a total power consumption of 28 nW. The measured power supply ripple rejection (PSRR) of $\text{V}_{\mathrm {ref}}$ is −65 dB @DC and −39.4 dB at frequencies higher than 1 Hz.

A 0.55 V Bandgap Reference with a 59 ppm/°C Temperature Coefficient

This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with the existing BJT-based reference circuits by using a MOS transistor operating in sub-threshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65[Formula: see text]nm CMOS technology. Post-layout simulation results show that the proposed circuit works with a supply voltage of 0.55[Formula: see text]V, and generates a 286[Formula: see text]mV reference voltage with a temperature coefficient of 59[Formula: see text]ppm/∘C. The circuit takes 413[Formula: see text]nA current from 0.55[Formula: see text]V supply and occupies 0.00986[Formula: see text]mm2 of active area.

A CMOS temperature sensor based on duty-cycle modulation with calibration

In this paper, a digital CMOS temperature sensor based on duty-cycle modulation with digital calibration is presented. The temperature sensor generates a duty-cycle-modulated signal by applying a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current derived from substrate bipolar junction transistors (BJT) to an integrator followed by a window comparator. The duty-cycle-modulated signal is then converted to a digital representation of temperature with two counters. Calibration is performed in the digital domain with three calibration parameters. Dynamic element matching (DEM) and chopping techniques are also used to minimize the errors caused by the component mismatch. The prototype chip is fabricated in a $$0.5\,\upmu \hbox {m}$$ CMOS process. The chip area occupies $$2.3\,\hbox {mm}^2$$. Measurement results from 11 test chips show that an inaccuracy of $$-1.1{-}0.5\,^{\circ }\hbox {C}$$ is achieved over the temperature range from $$-35$$ to $$85\,^{\circ }\hbox {C}$$ after calibration. The 2.5 V supply voltage is utilized and the total power consumption is 0.83 mW at a conversion rate of 0.5 kSa/s with a resolution of $$0.0625\,^{\circ }\hbox {C/LSB}$$, leading to $$6.48-\hbox {nJ}^{\circ }\hbox {C}^2$$ resolution figure of merit (FoM) and $$2951.1-\hbox {nJ}\%^2$$ accuracy FoM.

A Temperature Compensation Voltage Controlled Oscillator Using a Complementary to Absolute Temperature Voltage Reference

This paper presents a temperature compensation voltage controlled oscillator (VCO) based on Cross-Coupled pair and Colpitts structures which is suitable for military fields. Also, two inductors have been used for increasing the negative conductance. By using this method, start-up condition has been improved. Two varactors and a simple capacitor bank are applied for covering a wide tunning range. The VCO has been designed and simulated in TSMC 0.18 µm CMOS technology.To compensate the frequency drift over a temperature range, MOS varactors are used and biased with a complementary to absolute temperature (CTAT) voltage reference. This CTAT voltage reference has been applied to two varactors and decreased the frequncy drift over temperature range. By using this technique, the proposed VCO can achieve a very stable frequency of 11.5 PPM/°C at 24.35 GHz over a temperature range of -40~120 °C. Simulation results also show the VCO covers the frequency range of 23.75~24.8 GHz. The simulated phase noise of center frequency is -102.6 dBc/Hz at 1 MHz offset frequency. The VCO consumes 10.4 mW DC power under 1.8 V supply voltage. The figure of merit of the VCO is -179.8 after compensating.

A 470‐990 MHz digital‐controlled VCO with temperature compensation

AbstractA 470‐990 MHz ring oscillator with 10‐bit digital control is implemented using 0.18 μm CMOS technology. A complementary to absolute temperature (CTAT) current bias is employed to achieve temperature compensation. Operating from a 1.8 V supply, the oscillator consumes the currents of 5.41 mA and 15.15 mA at 470 MHz and 990 MHz, respectively. Measurement results show that the frequency drift of the oscillator is within 1% from−10 to 80°C.

A 0.9-V 33.7-ppm/°C 85-nW Sub-Bandgap Voltage Reference Consisting of Subthreshold MOSFETs and Single BJT

A low temperature coefficient (TC) and high power supply ripple rejection (PSRR) CMOS sub-bandgap voltage reference (sub-BGR) circuit using subthreshold MOS transistors and a single BJT is presented in this brief. The proposed sub-BGR consists of a novel complementary-to-absolute-temperature (CTAT) voltage generator based on a scaled emitter-base voltage of a BJT, and an improved proportional-to-absolute-temperature (PTAT) voltage generator based on stacking of $\Delta V_{\mathbf {GS}}$ of sub- $V_{\mathbf {TH}}$ MOSFETs. As the CTAT circuit achieves a reduced absolute value of the negative TC, the PTAT circuit achieves reduced power consumption without consuming a large chip area. The proposed sub-BGR circuit is implemented in a standard 0.18- $\mu \text{m}$ CMOS process. Measured results show that the sub-BGR circuit can run with a supply voltage down to 0.9 V while the power consumption is only 85 nW. An average TC of 33.7 ppm/°C and a PSRR of better than −40 dB over the full frequency range are achieved.

A 0.4-V 0.93-nW/kHz Relaxation Oscillator Exploiting Comparator Temperature-Dependent Delay to Achieve 94-ppm/°C Stability

This paper presents the analysis and design of a relaxation oscillator that counteracts the complementary-to-absolute-temperature (CTAT) property of the comparator delay with the proportional-to-absolute-temperature (PTAT) property of the RC core to realize temperature-stabilized operation. By using a feedback bias network to linearize the comparator CTAT delay, thus improving the overall temperature stability by 20 $\times $ , this technique enables a comparator with ~20 $\times $ less bandwidth and an overall oscillator with ~5 $\times $ lower power than conventional approaches. In a 0.18- $\mu \text{m}$ silicon on insulator CMOS process, this design consumes 1.14 nW from a 0.4-V supply operating at 1.22 kHz, with a temperature coefficient (TC) as low as 40 ppm/°C ( $\mu = 94$ ppm/°C for $n = 5$ ) achieving state-of-the-art efficiency (0.93 nW/kHz) for kilohertz-range relaxation oscillators.

A High-Speed Temperature Sensor with Low Supply Sensitivity for SoC Thermal Monitoring

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180[Formula: see text]nm CMOS process and occupies a small area of 0.048[Formula: see text]mm2 excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of [Formula: see text][Formula: see text]1.5[Formula: see text]C from [Formula: see text]45[Formula: see text]C to 85[Formula: see text]C under a supply voltage of 1.4–2.4[Formula: see text]V showing a worst-case supply sensitivity of 0.5[Formula: see text]C/V. The sensor maintains a high conversion rate of 45[Formula: see text]KS/s with a fine resolution of 0.25[Formula: see text]C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8[Formula: see text]V, the maximum energy consumption per conversion is only 7.8[Formula: see text]nJ at [Formula: see text]45[Formula: see text]C.

A Sub-1V Full CMOS Bandgap Voltage Reference with a Body Bias

In this paper, a low-power sub-1V bandgap voltage reference(sub-BGR) without any resistors and BJTs is presented. To reduce process variations without bipolar junction transistors(BJTs), a weighted Vgs structure is modified with a body bias for the generation of both complementary-to-absolutetemperature(CTAT) voltage and proportional-toabsolute-temperature(PTAT) voltage. Moreover, the proposed sub-BGR is operated in subthreshold region to minimize the power consumption. The proposed sub-BGR is implemented with a 0.18 μm deep N-well (DNW) CMOS technology. The measured results show that the temperature variation of 55ppm/°C is obtained with a temperature range from -40°C to 80°C. The power supply rejection ratio(PSRR) of -44 dB at 100 Hz is achieved while consuming total power of 38 nW at the supply voltage of 0.8 V. Measured output reference voltage is 435 mV and the active area is 150 μm by 49 μm.

A sub-1V, 120 nW, PVT-variation Tolerant, Tunable and Scalable Voltage Reference with 60 d

This paper presents a novel low-power process, voltage and temperature (PVT)-variation tolerant voltage reference generator that can be easily redesigned across various CMOS technologies. The proposed circuit architecture can be used in standalone analog integrated circuits that may not require nano-scale technologies as well as system-on-a-chip applications that need analog circuits in a much lower technology node due to their dominant digital counterparts. The reference generator implements weighted averaging of a PTAT (proportional to absolute temperature) and a CTAT (complementary to absolute temperature) voltage at zero temperature coefficient (ZTC) point. PVT-variation tolerant behavior is achieved by using an on-chip shift register based switching circuit that adjusts the bias current of a key transistor in the circuit. The proposed reference generator is fabricated in 180 nm mixed-mode CMOS technology and also designed in 65 and 28 nm technologies using foundry provided models. For a temperature range from ${\mathbf 0}$ to 75 °C at 1.8 V supply, the measured tuned output voltage varies by only ${\pm 0.33}$ % across ${\mathbf 17}$ chips, which is significantly lower than all previously reported works.

Wide-range CTAT and PTAT sensors with second-order calibration for on-chip thermal monitoring

This paper presents wide-range complementary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) sensors with second-order calibration for on-chip thermal monitoring. Particularly, a current mirror and an n-well resistor are used in these sensors to eliminate the second-order term of the temperature coefficient to linearize the transfer function between the output voltage and the temperature. The proposed CTAT and PTAT sensors are implemented on silicon using a typical 0.18μm CMOS process. The core area of the CTAT and PTAT sensors is 0.0125mm2 and 0.0074mm2, respectively. In the range from −55°C to 155°C, the worst deviation of the CTAT and PTAT temperature sensors is measured to be −3.75°Cto+3.34°C and −3.73°Cto+3.85°C, respectively. The maximum non-linearity reduction of the CTAT and PTAT sensors is 59.84% and 87.48%, respectively, by the proposed second-order calibration. Notably, the overhead area of the CTAT and PTAT sensors is only 0.64% and 1.08%, respectively.

A 1.58 nW power consumption and 34.45 ppm/°C temperature coefficient bandgap reference (BGR) for subblocks of RFID tag

In this paper a bandgap reference (BGR) circuit irrespective of the temperature and the supply voltage variation with very low power consumption is proposed. The proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) generators of the proposed BGR, which has four cores cascaded with each other, are used in order to increase not only the output voltage, but also the output control ability for the temperature and the voltage insensitivity. To combine produced voltage from PTAT and CTAT generator, a weight combination circuit, which uses internal capacitors of transistors, is applied. Due to the fact that all of the transistors in such a topology are worked in sub-threshold region, the power consumption is significantly diminished to 1.58nW. Also the variation of the temperature from −25°C to 150°C, leads to the temperature coefficient about 34.45ppm/°C. The design simulation is done at 960MHz frequency in TSMC 0.18µm CMOS technology with the help of Cadence software. Also the post layout simulation result and the layout of the proposed circuit are presented. The output and the chip area of this BGR are 141.5mV and 1387µm2 respectively.

A New No Op Amp Full CMOS Voltage Reference Circuit

A no op amp structure full CMOS reference voltage circuit is designed. The two currents which are proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) are added together to get the reference output voltage which is obtained through a resistance. The characteristics of the new circuit are simulated using 0.5 μm BSIM3V3 spice models in HSPICE. The simulation results show that the output voltage of the circuit is 997mV, the power consumption is 1.12mW, the temperature coefficient is 15.2 ppm/°C in the range from-30°C to 100°C at the supply voltage of 2V.