Complementary To Absolute Temperature Research Articles

A Highly Linear Ultra-Low-Area-and-Power CMOS Voltage-Controlled Oscillator for Autonomous Microsystems.

Voltage-controlled oscillators (VCOs) can be an excellent means of converting a magnitude into a readable value. However, their design becomes a real challenge for power-and-area-constrained applications, especially when a linear response is required. This paper presents a VCO for smart dust systems fabricated by 65 nm technology. It is designed to minimize leakage, limit high peak currents and provide an output whose frequency variation is linear with the input voltage, while allowing rail-to-rail input range swing. The oscillator occupies 592 μm2, operates in a frequency range from 43 to 53 Hz and consumes a maximum average power of 210 pW at a supply voltage of 1 V and 4 pW at 0.3 V. In addition, the proposed VCO exhibits a quasi-linear response of frequency vs. supply voltage and temperature, allowing easy temperature compensation with complementary to absolute temperature (CTAT) voltage.

An Energy‐Efficient Fully On‐Chip CMOS Temperature Sensor for Portable Applications With an RFoM of 2.79 pJ.K2

ABSTRACTThis article describes an energy‐efficient, low‐power CMOS temperature sensor suitable for portable applications. The sensor's front‐end circuitry is designed with a reference voltage (V), complementary to absolute temperature (CTAT) voltage (V), and ramp voltage generators. The ramp voltage (V) is produced by utilizing a current reference circuit. The ramp voltage is compared with independent and temperature‐dependent voltages to perform the voltage‐to‐frequency conversion. Conversion from frequency to digital output is achieved through an asynchronous counter with an on‐chip oscillator. The proposed design is realized in a 0.18‐m CMOS technology and attains a power usage of 604.4 nW at 27°C with an operating voltage of 0.5 V. Furthermore, it obtains an inaccuracy of +0.71/−0.73°C over −40°C to 125°C temperature range with an active area of 0.025 mm2. Moreover, the designed sensor circuit offers a resolution of 0.17°C with an energy conversion of 96.7 pJ.

A 1 V supply 10.3 ppm/°C 59 nW subthreshold CMOS voltage reference

—A low temperature coefficient (TC), low power subthreshold CMOS voltage reference (CVR) over a wide temperature range is presented in this paper. The proposed circuit employs the voltage difference between the two inputs of the operational amplifier as the proportional to absolute temperature (PTAT) voltage and the complementary to absolute temperature (CTAT) voltage, which is obtained by the ΔVGS of different-threshold transistors biased in the subthreshold region. The proposed CVR was designed in the 0.18-μm CMOS process with a total area of 0.0049 mm2. It achieves an average temperature coefficient (TC) of 10.3 ppm/°C over a temperature range of −40 °C–120 °C, with a TC of 4.9 ppm/°C at the TT corner. The measured power supply rejection ratio (PSRR) is −65 dB at 10 Hz and −30 dB at 1 MHz, while the power consumption is 59 nW at a supply voltage of 1 V. The average line sensitivity (LS) is 0.16 %/V, and the LS is 0.09 %/V at the TT corner.

A 8.83 ppm/°C temperature coefficient, 75 dB PSRR subthreshold CMOS voltage reference with piecewise curvature compensation

A subthreshold CMOS voltage reference (CVR) with low temperature coefficient (TC) over a wide temperature range and low power is proposed in this paper. The proposed CVR utilizes the ΔVGS of different-threshold and same-threshold nMOS pairs to generate complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages, respectively. To compensate for the low-temperature and high-temperature segments of the temperature characteristic curve, the nonlinear compensation currents generated by the exponential-like relationship between the drain current and the gate-source voltage of two MOSFETs work in the subthreshold region is used. Based on a 0.18-μm CMOS process, post-layout simulation results show that the proposed CVR achieves an average output voltage of 263 mV. The power supply ripple rejection (PSRR) is −75 dB at 10 Hz and the line sensitivity (LS) is 0.0069 %/V when the supply voltage varies from 0.8 V to 2.5 V. The average TC is 8.83 ppm/°C for a wide temperature range of −40 °C–120 °C, and the minimum TC is only 3.65 ppm/°C.

A 1.58 nJ/conversion temperature-to-digital converter with low power variations

A 1.58 nJ/conversion temperature-to-digital converter at the supply voltage of 0.7 V was designed and fabricated on the die area of 0.147 mm2 using the 90 nm CMOS technology. The sub-nA constant reference current (I ref) and the sub-nA complementary-to-absolute temperature (CTAT) current (I CTAT) are generated by employing the gate leakage currents of PMOSFETs. The current-to-frequency oscillators using those currents followed by the frequency-to-digital converter are used to produce the digital codes inversely proportional to temperatures. With this approach, the power consumption at high temperatures can be alleviated significantly. Thus, the variation of power consumption is only 70% from −10 °C to 90 °C. The conversion time is 107 ms at the RT and the noise non-limited resolution is 0.052 °C.

Low-power Relaxation Oscillator with Temperature-compensated Thyristor Decision Elements

This paper presents a low-power 140 kHz relaxation oscillator (ROSC) for low-frequency clock generators and timers. In voltage-mode ROSCs, unavoidable shunt current consumption results from voltage slewing at the integration capacitor. The proposed circuit employs CMOS thyristor-based decision elements which effectively reduce shunt currents by exploiting internal positive feedback. A complementary-to-absolute temperature (CTAT) current reference compensates for the frequency’s temperature sensitivity. In order to achieve high negative temperature coefficient with small area and power overhead, the circuit reuses parts of the positive-to-absolute temperature (PTAT) bias generation block. Moreover, a modified start-up circuit with 3 times faster oscillator power-on is presented. The 0.09 mm{}^2 oscillator consumes 6.5 nW/kHz at 1.5 V to 2.5 V supply if only the CTAT source is considered, resulting in a power consumption of 907.4 nW at 140 kHz. The measured temperature coefficient of -514.7 ppm/K in the range of −40 °C to 85 °C shows an improvement of 5.5 times compared to the uncompensated case. A supply sensitivity of 2.62 %/V, a frequency resolution of 2.67 kHz/step, and an average clock jitter of 6.02 ns are achieved. The oscillator is embedded in an ultra-low power system-on-chip for autonomous environmental sensing.

A 6.435-nW, 26.2-ppm/°C hybrid bandgap reference with stacked ΔVGS compensation in sub-threshold region

This paper illustrates a methodology to design an ultra-low power hybrid bandgap reference (HBR) with high accuracy to counteract the effect of temperature using single BJT and MOSFETs working in subthreshold region. Based on compensated VBE and ΔVth, the study provides a new insight into compensation of complementary-to-absolute-temperature (CTAT) voltage with a nano-watt proportional-to-absolute-temperature (PTAT) voltage generator with reduced threshold voltage-induced process variation. Designed in a 180 nm CMOS process, the circuit has a measured temperature coefficient of 26.2 ppm/°C with a wide temperature range of −40 °C∼125 °C and an overall variation coefficient of 0.234% among 9 chips with an active area of 0.0264 mm2. The experimental result shows that the proposed HBR circuit can operate with a supply voltage down to 1.1 V and a full frequency PSRR of better than −35 dB while the power consumption is only 6.435 nW.

A 1.1 V 25 ppm/°C Relaxation Oscillator with 0.045%/V Line Sensitivity for Low Power Applications

A fully-integrated CMOS relaxation oscillator, realized in 40 nm CMOS technology, is presented. The oscillator includes a stable two-transistor based voltage reference without an operational amplifier, a simple current reference employing the temperature-compensated composite resistor, and the approximated complementary to absolute temperature (CTAT) delay-based comparators compensate for the approximated proportional to absolute temperature (PTAT) delay arising from the leakage currents in the switches. This relaxation oscillator is designed to output a square wave with a frequency of 64 kHz in a duty cycle of 50% at a 1.1 V supply. The simulation results demonstrated that the circuit can generate a square wave, with stable frequency, against temperature and supply variation, while exhibiting low current consumption. For the temperature range from −20 °C to 80 °C at a 1.1 V supply, the oscillator’ output frequency achieved a temperature coefficient (T.C.) of 12.4 ppm/°C in a typical corner in one sample simulation. For a 200-sample Monte Carlo simulation, the obtained T.C. is 25 ppm/°C. Under typical corners and room temperatures, the simulated line sensitivity is 0.045%/V with the supply from 1.1 V to 1.6 V, and the dynamic current consumption is 552 nA. A better figure-of-merit (FoM), which equals 0.129%, is displayed when compared to the representative prior-art works.

Ultra Low Power Temperature Compensated Complementary Metal Oxide Semiconductor Ring Oscillator in Subthreshold

Low power consumption, low chip area and fabrication in the standard complementary metal oxide semiconductor (CMOS) process are vital requirements for oscillators used in low-cost bio-implantable and wearable devices. Conventional ring oscillators (ROs) are good candidates for using in biomedical applications. However, their oscillation frequency strongly depends on the temperature. In this study, a temperature compensated ring oscillator with low power consumption is proposed. The transistors of the proposed ring oscillator operate in the subthreshold region to achieve a low power and low voltage performance. Since, in the subthreshold region, the oscillation frequency of a conventional ring oscillator increases with increase in the temperature, two current sources are used to power the proposed subthreshold ring oscillator: a temperature independent current source and a complementary to absolute temperature (CTAT) current source. In the proposed circuit, the CTAT current forms a small part of the total supplied current and its duty is to compensate for the oscillation frequency deviation. Two prototypes of the subthreshold ring oscillator were designed and simulated for a target frequency of 1MHz using commercially available 0.18µm RF-CMOS technology. The thermal coefficient (TC) of the uncompensated ring oscillator was 2400 ppm/ºC from -40ºC to 85ºC, though applying the proposed technique reduces the TC of the ring oscillator to 80.4 ppm/ºC with total power consumption as low as 14.5µW.

A 9.5nW, 0.55V Supply, CMOS Current Reference for Low Power Biomedical Applications

This brief proposes an ultra-low-power current reference in TSMC 180nm technology. Temperature compensation is achieved by taking the ratio of compensated voltage and an on-chip resistance. This design uses the concept of the back-gate effect of critical MOSFET to generate complementary to absolute temperature (CTAT) voltage. The circuit works from a supply voltage of 0.55V and is designed for a reference current of 5.6nA. Furthermore, a pseudo-differential amplifier (PD-AMP) helps realize low line regulation of 0.022%/V in the supply range of 0.55 to 1.9V. An average temperature coefficient (TC) of 256.07ppm/°C is achieved for mismatch and process variations in Monte-Carlo simulations for 1000 samples over a temperature range of −30°C to 70°C. The circuit consumes only 9.5nW of power (at room temperature and minimum supply voltage), making it suitable for ultra-low-power biomedical applications.

High-performance sub-1 V CMOS voltage reference with low supply voltage

A CMOS voltage reference with low line sensitivity, high PSRR, and low supply voltage is presented. Usually, CMOS voltage references use proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) behaviours to generate temperature-compensated reference voltages. Since the PTAT-behaviour-generator circuit requires more transistors with complex circuitry than the CTAT-behaviour-generator circuit, these voltage references require a large number of transistors. Therefore, this technique does not offer much improvement in the circuit's complexity, power consumption, and area. To overcome these drawbacks, some of the researchers have presented voltage references based on the subtraction of two CTAT behaviours but they have used two different circuits for CTAT voltages/currents. In contrast, only one standard beta-multiplier circuit is used in the proposed design to generate CTAT voltages which further decreases circuit complexity and area. Also, operational amplifiers have been employed in the negative feedback loop to achieve low line sensitivity and high PSRR. The proposed circuit offers an output reference voltage of 350 mV with a temperature coefficient of 31.5 ppm/°C for the temperature varying from −55 °C to 125 °C. The line sensitivity and PSRR are observed as 0.015 %/V (for supply voltage ranging from 0.65 V to 3.5 V) and −85.4 dB (for the frequency of 100 Hz), respectively.

A temperature‐compensated linear GaAs HBT power amplifier for small‐cell applications in −25 to 125∘C$^\circ \rm C$ lunar environment

A two-stage 920–960 MHz power amplifier (PA) in GaAs heterojunction bipolar transistor (HBT) process is demonstrated for small-cell communications in the lunar environment. To cope with the temperature fluctuations during lunar days, a novel complementary to absolute temperature (CTAT) biasing scheme is proposed for the PA to achieve an ultra-wide-range temperature compensation. Moreover, to meet the linearity requirements of the small-cell applications while producing high output power, a band-stop filter is employed in the biasing circuit of the second stage to reduce the AM– AM distortions. Over the temperature range of −25 to 125°C, the PA is capable of operating for the small-cell applications over a gain ranging from 30.2 to 32.8 dB. The proposed PA achieves 24.5 dBm linear power with −47 dBc adjacent channel leakage ratio (ACLR) and a PAE of 15%.

A Low-temperature-coefficient Bandgap Voltage Reference for Sar Adc

Abstract The paper verifies a curvature-compensated bandgap reference circuit, which generates 1.2V bandgap voltage. Bandgap voltage comprises two parts: proportional to absolute temperature (PTAT) voltage from the bandgap core and complementary to absolute temperature (CTAT) voltage from the p-n junction. Simulation results across corners show that the temperature coefficient of this architecture can be less than 3ppm/°C by using the current compensation. Test results prove that the temperature coefficient achieves 5ppm/°C. The proposed bandgap consumes a power of 2mW and occupies an area of 0.15mm2 in the 0.18μm CMOS process.

A Sub-1-V CMOS Voltage Reference with High PSRR and High Accuracy

This paper presents a novel sub-1-V CMOS voltage reference with high power supply rejection ratio (PSRR), low line sensitivity, and low supply voltage. CMOS voltage references available in the literature use a self-biased cascode branch consisting of two MOS transistors operating in the subthreshold region to generate the proportional-to-absolute-temperature (PTAT) voltage only, whereas extra circuitry is required to generate the complementary-to-absolute-temperature (CTAT) voltage for temperature compensation. But in the proposed sub-1-V CMOS voltage reference, both the PTAT and CTAT voltages are generated using a single self-biased cascode branch. Two operational amplifiers in negative feedback topology are used to convert the PTAT and CTAT voltages into PTAT and CTAT currents, respectively, which help to enhance the stability and PSRR of the proposed voltage reference. The proposed voltage reference has been designed and simulated in 180-nm standard CMOS technology using Cadence Virtuoso Analog Design Environment. The proposed voltage reference achieves an output reference voltage of 424.85[Formula: see text]mV with a temperature coefficient of 29.5[Formula: see text]ppm/∘C for the temperatures ranging from [Formula: see text]C to 125∘C at a supply voltage of 0.8[Formula: see text]V. A line sensitivity of 0.0035%/V is achieved for the supply voltage varying from 0.8[Formula: see text]V to 5[Formula: see text]V at nominal temperature (27∘C). A PSRR of [Formula: see text]91.69[Formula: see text]dB is observed for the frequencies ranging from 1[Formula: see text]Hz to 10[Formula: see text]kHz at nominal conditions without using any capacitive filter. Also, the output noises of the proposed design at nominal conditions for the frequencies of 1[Formula: see text]Hz and 10[Formula: see text]kHz are obtained as 2.37[Formula: see text][Formula: see text]V/[Formula: see text]Hz and 45.26[Formula: see text]nV/[Formula: see text]Hz, respectively.

A nano-power sub-bandgap voltage and current reference topology with no amplifier

A sub-bandgap current and voltage reference operating at ultra-low quiescent current is proposed for energy harvesting and battery-operated systems. Using a single bipolar junction transistor (BJT) and no operational amplifier (opamp), the current reference is generated from proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) voltages combined in a simple three-branch self-biased structure, while the voltage reference is derived by driving the current reference to a temperature-insensitive resistor. The line sensitivity (LS) is enhanced by incorporating cascode devices into the original configuration. Designed in a 0.18-µm standard CMOS process, the proposed architecture occupies an active area of 609 µm × 755 µm with around 47 nA current consumption regardless of temperature. The generated current and voltage references are 6.7 nA and 180 mV, and their temperature coefficients (TC) are 32.76 ppm/°C and 34.80 ppm/°C across the temperature range from −40 to 120 °C, respectively. The minimum supply voltage is 1.1 V, and the line sensitivity of the voltage and current reference are 0.031%/V and 0.03%/V, respectively, over the supply voltage range of 1.1–1.8 V.

A Fully MOSFET Voltage Reference with Low Power Consumption and High Power Supply Rejection Ratio for IoT Microsystems

In this work, a fully MOSFET voltage reference (FMVR) circuit with a current consumption of 7.6 nA and a supply voltage of 1 V is proposed. To generate the complementary to absolute temperature (CTAT) voltage, the voltage of a PN junction generated by a PMOS transistor - which is part of the bias circuit - is used. Generation of proportional to absolute temperature (PTAT) voltage is carried-out by utilizing three stages of self-cascode transistors biased in the sub-threshold region. A fraction of the CTAT voltage is added to the PTAT voltage without using an additional circuit to enable acquiring an output reference voltage of about 0.648 V with minimal temperature dependence. The proposed voltage reference is simulated in 0.18 μm of CMOS process and its area occupation is 0.0023 mm2. The obtained post-layout simulation results demonstrate that the proposed FMVR has a temperature coefficient equivalent to 12.9 ppm/°C under the temperature variation from -25 °C to 120 °C. Moreover, the line regulation under supply voltage variation from 0.9 V to 2 V is found to be equal to 0.02 %/V, and a power supply rejection ratio of 44 dB is acquired. Comparing the main parameters of the proposed FMVR - to the state-of-the-art circuits - shows that it has higher efficiency with smaller area and lower power consumption.

3.48-nW 58.4ppm/°C Sub-threshold CMOS Voltage Reference with Four Transistors and Two Resistors

In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1[Formula: see text]V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-[Formula: see text]m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494[Formula: see text]mV with temperature coefficient (TC) of 58.4[Formula: see text]ppm/∘C across [Formula: see text]C to 85∘C; while the consuming power is lowered to 3.48[Formula: see text]nW at the minimum supply of 0.8[Formula: see text]V. The line sensitivity is 0.7%/V for the supply voltages from 0.8[Formula: see text]V to 1.8[Formula: see text]V, whereas the power supply ripple rejection (PSRR) is [Formula: see text]49.06[Formula: see text]dB at 1[Formula: see text]Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2[Formula: see text]mV with [Formula: see text]/[Formula: see text] of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.

A CMOS PSR Enhancer with 87.3 mV PVT-Insensitive Dropout Voltage for Sensor Circuits.

A new power supply rejection (PSR) based enhancer with small and stable dropout voltage is presented in this work. It is implemented using TSMC-40 nm process technology and powered by 1.2 V supply voltage. A number of circuit techniques are proposed in this work. These include the temperature compensation for Level-Shifted Flipped Voltage Follower (LSFVF) and the Complementary-To-Absolute Temperature (CTAT) current reference. The typical output voltage and dropout voltage of the enhancer is 1.1127 V and 87.3 mV, respectively. The Monte-Carlo simulation of this output voltage yields a mean T.C. of 29.4 ppm/°C from −20 °C and 80 °C. Besides, the dropout voltage has been verified with good immunity against Process, Temperature and Process (PVT) variation through the worst-case simulation. Consuming only 4.75 μA, the circuit can drive load up to 500 μA to yield additional PSR improvement of 36 dB and 20 dB of PSR at 1 Hz and 1 MHz, respectively for the sensor circuit of interest. This is demonstrated through the application of an enhancer on the instrumentation Differential Difference Amplifier (DDA) for sensing floating bridge sensor signal. The comparative Monte-Carlo simulation results on a respective DDA circuit have revealed that the process sensitivity of output voltage of this work has achieved 14 times reduction in transient metrics with respect to that of the conventional counterpart over the operation temperature range in typical operation condition. Due to simplicity without voltage reference and operational amplifier(s), low power and small consumption of supply voltage headroom, the proposed work is very useful for supply noise sensitive analog or sensor circuit applications.

A Low Supply Voltage, Low Line Sensitivity and High PSRR Subthreshold CMOS Voltage Reference

The paper presents a low supply voltage CMOS voltage reference with low line sensitivity and high PSRR. Generally, the reference voltage is obtained using both complementary-to-absolute-temperature (CTAT) current and proportional-to-absolute-temperature (PTAT) current. This technique increases the complexity and area of the reference circuit. To overcome these drawbacks, the temperature compensated reference voltage has been proposed using only CTAT currents. Mostly, the CTAT current generators are simple, power-efficient, and area-efficient as compared to the PTAT current generators. The negative feedback loop has been formed in the proposed design to obtain a supply independent CTAT current and to avoid the use of startup drivers. The proposed circuit has been designed using Cadence virtuoso analog design environment in BSIM3V3 180[Formula: see text]nm CMOS technology. The simulation results of the proposed circuit show a reference voltage of 312[Formula: see text]mV with a temperature coefficient (TC) of 38.85[Formula: see text]ppm/∘C over a wide temperature range of [Formula: see text]C to 125∘C with a supply voltage of 0.8[Formula: see text]V. The line sensitivity is 0.027% [Formula: see text] with a supply voltage ranging from 0.8[Formula: see text]V to 3[Formula: see text]V. The power supply rejection ratio (PSRR) without using any capacitive filter is observed as [Formula: see text] and [Formula: see text][Formula: see text]dB at 100[Formula: see text]Hz and 100[Formula: see text]kHz frequency, respectively. The circuit is simple and occupies a chip area of 0.0027[Formula: see text]mm2.

A 1.16-V 5.8-to-13.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers

This article introduces an accurate current-mode bandgap reference circuit design with a novel shared offset compensation scheme for its internal amplifiers. This bandgap circuit has been designed to operate over a very wide temperature range from −40 °C to 150 °C. Its output voltage is 1.16 V with a 3.3-V supply voltage. A multi-section curvature compensation method alleviates the error from the bipolar junction transistor’s base–emitter nonlinear voltage dependence on temperature. The bandgap reference circuit contains two operational amplifiers that are utilized to generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) current sources. With the implementation of the described shared offset-cancellation methodology, the simulated output inaccuracy introduced by the amplifier is kept to a 5 $\sigma $ offset within ±4.6 $\mu \text{V}$ while allowing to conserve die size and power consumption by preventing that each amplifier is accompanied by its own active auxiliary offset-cancellation circuit. Designed and fabricated in a 130-nm CMOS process technology, the bandgap reference has a measured output voltage shift of less than 1 mV over a −40 °C to 150 °C temperature range and an overall variation of ±8.2 mV across seven measured samples without trimming.