Complementary SiGe Research Articles

A unified aging compact model for hot carrier degradation under mixed-mode and reverse E-B stress in complementary SiGe HBTs

This paper presents an accurate, comprehensive and physics-based aging compact model for stress-induced degradation due to hot-carrier generation and oxide trapping in advanced complementary NPN and PNP SiGe HBTs. The analytical model equations are derived from the solution of reaction–diffusion theory and Fick’s law of diffusion combined with oxide trapping mechanism under accelerated stress conditions. The model accuracy has been validated against results from long-term aging tests performed close to the safe-operating-areas of an advanced complementary 0.25 µm BiCMOS technology. Degradation asymmetry observed between NPN and PNP devices is accurately captured by this unified aging compact model. This study highlights the challenges of predicting degradation of complementary circuits and thereby improving its functionalities by designing better-matched NPN and PNP HBTs.

Tradeoffs Between RF Performance and SET Robustness in Low-Noise Amplifiers in a Complementary SiGe BiCMOS Platform

Low-noise amplifiers (LNAs) are necessary components for any communications system. Single-event transients (SETs) induced by energetic particles in space can corrupt the data in an RF receiver. Using p-n-p silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs), instead of their more common n-p-n counterparts, has been shown to be an effective mitigation technique in digital, analog, and RF circuits. Since p-n-p SiGe HBTs tend to have lower performance than n-p-n SiGe HBTs, in this article, the tradeoffs between performance and SET robustness have been evaluated through the use of simulations. Two LNAs were designed using an algorithmic design technique: one using only n-p-n SiGe HBTs, and the other using only p-n-p devices. The n-p-n LNA had higher peak gain and lower noise figure at the center frequency of 5 GHz when compared to the p-n-p LNA, by 3.2 and 0.4 dB, respectively. However, the n-p-n LNA also produced transients with amplitudes larger than the p-n-p LNA across all simulated linear energy transfers. Although the p-n-p LNA has lower overall performance, it is also more robust to SETs. Thus, the choice between using n-p-n and p-n-p SiGe HBTs for an RF design will depend on application requirements.

P-n-p-Based RF Switches for the Mitigation of Single-Event Transients in a Complementary SiGe BiCMOS Platform

The benefits of using p-n-p silicon–germanium (SiGe) heterojuction bipolar transistors (HBTs) in radio frequency (RF) circuits for the mitigation of single-event transients (SETs) have been investigated. As a representative circuit example, p-n-p SiGe-HBT RF single-pole single-throw (SPST) switches have been designed in a complementary SiGe BiCMOS platform. The fabricated p-n-p-based RF switches provide comparable RF performance to n-p-n-based switches. In terms of SET transient peaks and duration, the p-n-p SiGe HBT RF switches exhibit a significant reduction in SET sensitivity compared with their n-p-n counterparts. In the frequency domain, the p-n-p switches show fewer low-frequency spurs than that of the n-p-n switches. In addition, inverse-mode p-n-p SiGe HBT switches provide the best overall SET response among all RF SPST switches investigated.

An Investigation of High-Temperature (to 300 °C) Safe-Operating-Area in a High-Voltage Complementary SiGe on SOI Technology

Safe-operating-area (SOA) in a high-voltage complementary silicon–germanium (SiGe) (= n-p-n + p-n-p) on silicon-on-insulator (SOI) technology is investigated from 24 °C to 300 °C. Three key reliability degradation regions are identified, including: 1) high-current; 2) mixed-mode; and 3) high-power. The degradation mechanisms, which are operative, including Auger damage, mixed-mode damage, and electrothermal runaway as well as their temperature dependences are identified. Mixed-mode damage exhibits a strong negative temperature coefficient for both n-p-n and p-n-p SiGe heterojunction bipolar transistors (HBTs) up to 300 °C, which leads to an increase in the SOA from a high-voltage perspective. Electrothermal boundaries are also explored by finding ${J}_{C,{\textsf {crit}}}$ and ${V}_{{\textsf {CB}},{\textsf {crit}}}$ across the ${J}_{C}$ – ${V}_{\textsf {CB}}$ plane up to 300 °C. Both n-p-n and p-n-p SiGe HBTs show an increase in the SOA for the electrothermal boundary as temperature increases. High-current-induced damage, on the other hand, exhibits a positive temperature coefficient, which implies that high current drive should carefully be considered when using SiGe HBT circuits operated in a high-temperature environment. However, at very high temperatures (>200°C), the high current damage processes show annealing properties, which implies that at sufficiently high temperatures, annealing can dominate over Auger damage and potentially extend the SOA of the technology.

Physical Differences in Hot Carrier Degradation of Oxide Interfaces in Complementary (n-p-n+p-n-p) SiGe HBTs

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability.

Total Ionizing Dose Effects on a High-Voltage (>30V) Complementary SiGe on SOI Technology

Total ionizing dose (TID) effects are evaluated for a high-voltage (>30 V) complementary SiGe on SOI technology. Devices are irradiated with 10-keV X-rays at doses up to 5 Mrad(SiO2). The results depend strongly on collector-to-emitter bias, in both forward- and inverse-mode. An anomalous reduction in current gain at high injection in forward-mode operation is observed at doses >500 krad(SiO2). Calibrated 2-D TCAD simulations suggest that this high injection phenomenon is primarily due to interface traps near the STI/Si interface, which is exhibited as a collector resistance increase in the forward Gummel characteristics. Additionally, a strong collector doping dependence is observed, which indicates that this is primarily driven by the thick and lightly doped collector used in this technology. These results illustrate, that high concentrations of interface traps at the STI can have a strong impact on the forward-mode TID response of SiGe HBTs.

(Invited) The Application of Advanced Sige Complementary Bipolar Technologies to High Speed and High-Precision Applications

SiGe has rapidly grown to a mature process technology addressing a broad array of applications. Most of the literature discussing these applications focuses on RF circuits and very high-speed data links; both take advantage of the high switching speed, low noise, and current handling capabilities afforded by SiGe transistors. The addition of germanium into a silicon bipolar junction transistor (BJT) technology allows the component engineer to optimize different parameters. These applications usually force the focus on Ft or Fmax. While these are also important in the design of precision circuits and or high linearity amplifiers, current gain (Hfe) and Early voltage (Va) are often design limitations that force use of more complex circuits. Additionally, usually only NPN transistors are available which can significantly complicate the design of critical analog building blocks. SiGe in fact provides significant performance boost to PNP transistors and in the last couple of decades complementary SiGe BJT processes are offered by several major semiconductor manufacturers. Although generally the focus has been on relatively low voltage devices with Bvceos of significantly less than 5V, SiGe can also be applied to the design of much higher voltage transistors with a significant boost in performance. Many integrated circuits are built in such complementary SiGe Bipolar technologies and offer significant advantages over equivalent devices built in more conventional processes. To address low voltage applications, we will discuss how complementary SiGe can be applied to the design of a high-speed 16bit analog to digital convertor (ADC) and the design of a special buffer amplifier developed to condition the signal fed to such ADCs. Higher voltage (+/-15V supplies) precision amplifiers are still a significant market and have warranted the development of specialized complementary SiGe technologies. We will work through the design of a typical amplifier and show how the improved transistors lead to better end-product performance. Feedback amplifiers are generally easier to stabilize if there are fewer gain stages. Compensation techniques are available to stabilize complex amplifier designs which generally sacrifice performance. The increased gain offered by SiGe BJTs compared to alternatives can reduce the number of gain stages needed to meet a specific specification. The availability of a complementary PNP transistor can also significantly simplify circuit design. The combination of the gain of the SiGe BJT (due to high Va and Hfe) together with the simplicity and symmetry offered by complementary bipolar circuit design enables the design of very high performance operational amplifiers. We will detail an ampliier designed for very high performance portable audio applications. The combination of high Early Voltage and high Beta allows for a simple, single gain stage implementation, which results in low quiescent power, high capacitive load drive and high PSRR. The high beta and Ft of the SiGe transistors make this performance possible at low quiescent power.

Review—Multifunctional Technology with Monolithic Integrated THz-, Photonic- and μ-Fluidic Modules

The purpose of this work is to review requirements and challenges for the monolithic integration of different devices and modules in a baseline CMOS-process with the intention to create a multifunctional technology platform. We consider integrated modules like THz devices, i.e. complementary SiGe heterojunction bipolar transistors, silicon photonics components in particular Ge-PIN photo detectors and the wafer-level integration of micro-fluidic channels for sensor applications. However, the monolithic integration of devices and modules for novel functionalities is still a trade-off. On the one side there are requirements of the integration concept and therefore to the process steps of the dedicated module to achieve a maximum device performance. On the other side there are influences of the process steps for the module integration to the performance of the devices from the underlying baseline technology like bipolar- and CMOS-transistors or passive components. Both aspects have to be considered to enable the co-integration of new modules in order to get a technology platform for high performances and novel functionalities. We review process adaptations of the baseline technologies to enable an efficient co-integration of different modules. Moreover we discuss critical process steps with a certain thermal budget and their influence to device performances. Finally we give recommendations for process sequences to enable a wafer level co-integration of microfluidic channels into a SiGe-BiCMOS technology platform.

(Invited) Multifunctional Technology with Monolithic Integrated THz-, Photonic- and µ-Fluidic Modules

In this paper we present a multifunctional technology platform with different monolithic integrated modules like THz devices, i.e. complementary SiGe heterojunction bipolar transistors, silicon photonics components in particular Ge-PIN photo detectors and finally the wafer-level integration of µ-fluidic channels for sensor applications. Challenges during the monolithic integration of these different modules were reviewed and necessary process adaptations discussed in order to enable a co-integration.

(Invited) Multifunctional Technology with Monolithic Integrated THz-, Photonic- and µ-Fluidic Modules

Beside the use of the continuously scaled silicon-based integrated-circuit technologies there is an increased demand of “More-than-Moore” (MtM) components, modules and technologies to serve the requirements of new applications e.g. in the communication market or in big data processing centers. The MtM approach describes the diversification of functionality on a reasonable scaling level and is according to the ITRS one of the key drivers for future communication products. The strategies to increase the functionality of an integrated circuit or system by the integration of MTM components can be distinguished to monolithic and heterogeneous integration concepts, respectively. The latter one enables in general a high flexibility for the combination of different functionalities as CMOS, MEMS (micro-electro-mechanical systems) or III-V devices. However, a reliable packaging and therefore a sufficient yield can be a major concern for these systems. The monolithic integration of modules and devices with advanced functionality in a baseline CMOS process can overcome this concern. However these integration concepts have to consider issues during the integration of different modules like the interaction of process steps to the performance of the devices. In this paper we present a multifunctional technology platform with different monolithic integrated modules like THz devices, i.e. complementary SiGe heterojunction bipolar transistors, silicon photonics components as waveguides, photo detectors and modulators, and finally the wafer-level integration of µ-fluidic channels. The continuous improvement of SiGe-BiCMOS technologies have proven their demand for instance in the automotive radar market. Mid- and long-range radar systems at 77 GHz can be realized by using HBTs with maximum oscillation frequencies (fmax) of 300 GHz. The power consumption of these systems can be significantly reduced by the use of available SiGe-BiCMOS technologies with fmax of 500 GHz. Addditional new applications as THz circuits for gas spectroscopy and chipsets for sensing and short-range wireless communication have been demonstrated with these technologies. In future novel systems as short-range-radar (SRR) or autonomous cruise control (ACC) at frequencies of 120 and 150GHz can be targeted by the use of next generation SiGe-BiCMOS technologies. According to the ITRS one main challenge of group-IV bipolar technologies is the determination of a reasonable “plateau technology” i.e. the best ratio of fT/fmax of the fast npn-HBTs as well as the realization of complementary devices. In this work we review the continuous progress of high-speed npn-HBTs and the realization of the fastest pnp-HBT with maximum oscillation frequencies of 265GHz in an IHP-BiCMOS process. The demand for opto-electronic technologies in the market of big data processing centers increase continuously because of the necessity to handle the steadily growing data volumes. Recently we introduced the monolithic integration of photonic components as silicon-waveguides, high speed germanium-photo detectors and silicon based mach-zehnder-modulators (MZM) with high speed SiGe-BiCMOS devices in a joint technology. This new electro-photonic-integrated-circuit (EPIC) technology enables new applications as fully integrated linear 40Gbps receiver or SP-QPSK receiver for 28Gbaud operation. These circuits are among best in class and outperform monolithically Si integrated receivers fabricated elsewhere, e.g. with a Photonics-CMOS platform. However, there are several challenges during the monolithic integration of these photonic components in a SiGe-BiCMOS environment as the realization of a mixed substrate (SOI and bulk) or process optimizations to enable high-performance SiGe-HBTs and high speed Ge-photo detectors on the same wafer. The last part of the paper describes the wafer level integration of micro-fluidic channels in a SiGe-BiCMOS technology. The silicon channels were realized by a deep silicon substrate etching from the wafer backside after the SiGe-BiCMOS process on the front side of the wafer is almost finished. The local backside etching (LBE) process requires specific conditions on the front side to enable a save and reliable process on the backside (chemical-mechanical-polishing (CMP), photo-lithography, reactive-ion etching (RIE)). The in- and outlet of the fluidic channels are realized on a separate silicon wafer by different deep RIE processes. Finally both wafers were bonded permanently. With this approach high frequency circuits which were realized in the SiGe-BiCMOS front- and back end can be used for sensor applications to investigate small volumes of fluids in the µ-channels for instance in bio-medical applications. The paper reviews the monolithic integration of different modules and components to realize a multifunctional technology. We show challenges and benefits of this monolithic integration approach for the realization of a complex “More-than-Moore” technology.

A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC

This paper describes a 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T&H to improve the dynamic performance of the individual sub-ADCs and to reduce both the converter error rate and the complexity of the required interleaving background calibration algorithms. It achieves an SFDR of 79 dBc and 66 dBc at low and high frequency inputs, respectively and an error rate of less than 10 -9 , and has a power consumption of 1.15 W for the core ADC.

An Investigation on the Optimization and Scaling of Complementary SiGe HBTs

We use predictive technology computer-aided design to investigate the device design challenges and optimization issues that will be necessarily encountered in scaling of complementary silicon-germanium (C-SiGe) heterojunction bipolar transistors (HBTs). A fully integrated simulation framework was developed to design and optimize device doping and Ge profiles for any given target performance, using important circuit-relevant figures-of-merit. This methodology was successfully utilized to realize device profiles for multiple C-SiGe technology nodes within the context of a C-SiGe scaling roadmap. A method for optimizing the ac performance of SiGe HBTs geared for both high-performance and low-power applications is also presented. The performance metrics of the optimized profiles presented here are then compared with those of existing fabricated devices reported in the literature.

Single-Event Response of the SiGe HBT Operating in Inverse-Mode

The single-event effect sensitivity of inverse-mode biased SiGe HBTs in both bulk and SOI technology platforms are investigated, for the first time, using digital circuits and stand-alone device test structures. Comparisons of heavy-ion broad beam data of shift register circuits constructed with forward-mode and inverse-mode biased SiGe HBTs from a first-generation, complementary SOI SiGe BiCMOS process, reveal an improvement in SEU mitigation for the inverse-mode shift register architecture. Full 3D TCAD simulations highlight the differences in transient current origination between forward and inverse-mode biased devices, illustrating the impact of doping profiles on ion-induced shunt duration. To extend the analysis to a bulk platform, new fourth-generation npn , SiGe HBTs were biased in both the forward and inverse-mode and irradiated at NRL using the two photon absorption measurement system. These measurements support the analysis of transient origination using 3D TCAD simulations. Furthermore, the isolation of the output terminal from the sensitive subcollector-substrate junction is experimentally demonstrated for the inverse-mode bias. Fully coupled mixed-mode simulations predict a significant reduction in sensitive area for inverse-mode shift registers built in a bulk SiGe platform.

An Investigation of DC and RF Safe Operating Area of n-p-n $+$ p-n-p SiGe HBTs on SOI

We have examined the reliability risks of complementary SiGe HBTs on thick-film silicon on insulator (SOI). DC stress techniques, such as reverse emitter-base (EB) stress, mixed-mode stress, and flyback measurements, were used to characterize the safe operating area of n-p-n and p-n-p SiGe HBTs fabricated on SOI substrates. The measurements were analyzed based on fundamental damage mechanisms, such as hot carriers generated at the EB and collector-base junctions during large reverse voltage, and thermal runaway as a result of high current phenomena. RF stress (using a large amplitude continuous-wave signal) was also performed to examine the reliability of complementary bipolar complementary metal-oxide-semiconductor devices and circuits in an RF context. In both cases, p-n-p SiGe HBTs were found to be more reliable than n-p-n SiGe HBTs, a fact that may offer opportunities for circuit design optimization.

Single Event Transient Hardness of a New Complementary (npn <formula formulatype="inline"><tex Notation="TeX">$+$</tex></formula> pnp) SiGe HBT Technology on Thick-Film SOI

We report heavy-ion microbeam and total dose data for a new complementary (npn + pnp) SiGe on thick-film SOI technology. Measured transient waveforms from heavy-ion strikes indicate a significantly shortened single-event-induced transient current, while maintaining the total dose robustness associated with SiGe devices. Heavy-ion broad-beam data confirm a reduced single event upset (SEU) cross-section in a high-speed shift register circuit.

A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR

This paper describes a 16-bit analog-to-digital converter designed in a complementary SiGe BiCMOS SOI process. The high-performance complementary BJTs lead to a switched-current approach to the signal processing. Although it uses a fairly traditional four-stage pipeline architecture, several techniques are incorporated to achieve 16 bits of distortion performance at a sample rate of up to 160 MHz. For improved high input frequency linearity we describe a track and hold with a sampling instant modulation scheme. For stability of the current-mode DAC over signal swing and temperature we describe a scheme to increase the output impedance of the first sub-DAC. At a sample clock frequency of 122 MHz, prototype silicon exhibits a spurious-free dynamic range of 100 dBc through the first two Nyquist zones and a signal-to noise ratio of 77 dB. With a 160 MHz sampling clock, the measured SFDR is better than 90 dBc and the SNR is better than 74.5 dB. The ADC dissipates 1.6 W from 5 V and 3.3 V supplies.

The Effects of X-Ray and Proton Irradiation on a 200 GHz/90 GHz Complementary $(npn + pnp)$ SiGe:C HBT Technology

We investigate the effects of both X-ray and proton irradiation on a novel 200 GHz/90 GHz (npn/pnp) complementary SiGe:C HBT technology. The DC forward mode total dose tolerance of the pnp HBTs is shown to exceed that of the npn HBTs by a significant margin after being subjected to both 63-MeV proton and 10-keV X-ray sources, while the AC characteristics of both devices exhibit no degradation up to X-ray doses as high as 1.8 Mrad(SiO2). Pre- and post-irradiation results from a current feedback operational amplifier implemented in this technology and irradiated up to a dose of 1.8 Mrad(SiO2) are presented, showing no degradation in performance metrics under two low current density bias configurations.

The Effects of Proton and X-Ray Irradiation on the DC and AC Performance of Complementary (npn + pnp) SiGe HBTs on Thick-Film SOI

The impact of 63.3 MeV proton and 10 keV X-ray irradiation on the DC and AC performance of complementary SiGe HBTs on thick-film SOI is investigated. Proton and X-ray induced changes in the forward and inverse Gummel characteristics, the output characteristics, and avalanche multiplication are reported for both npn and pnp SiGe HBTs, at both room temperature (300 K) and at cryogenic temperatures (down to 30 K). Comparison of room temperature and cryogenic data suggests interface trap formation at two distinct physical locations in the transistors. Experimental data and calibrated TCAD simulations are used to compare the radiation response of both thick-film SOI devices and thin-film SOI SiGe HBTs.

Up-conversion mixers in a complementary 0.4 μm SiGe process

In this paper a 0.4 ?m complementary SiGe process is used to fabricate up-conversion mixers for base-station applications. A current feedback mixer, and a mixer with a folded input, were designed in order to test benefits obtainable from the use of equally fast PNP- and NPN-transistors. The target was to improve linearity and to increase output compression point ( $${\it OP}_{-1\,{\rm dB}}$$ ) of the mixers. A +5 dBm output compression point @2 GHz was measured while drawing 43 mA from 5 V voltage supply.

Issues and Opportunities for Complementary SiGe HBT Technology

This paper reviews the prospects of using complementary SiGe HBTs (npn + pnp transistors) to enhance the capabilities of current npn-only SiGe technology platforms. After an introduction, we discuss device design approaches and optimization, point out device and fabrication challenges, introduce technology solutions presently in existence, and project forward to potential applications of complementary SiGe technology.