Silicon Complementary Metal Oxide Research Articles

Low-Energy Symmetric Key Distribution in Wireless Sensor Networks

In this work, a scheme for key distribution and network access in a Wireless Sensor Network (WSN) that utilizes Identity-Based Cryptography (IBC) is presented. The scheme is analyzed on the ARM920T processor and measurements were taken for the runtime and energy of its components. It was found that the Tate pairing component of the scheme consumes significant amounts of energy, and so should be ported to hardware. An accelerator was implemented in 65 nm Complementary Metal Oxide Silicon (CMOS) technology and area, timing, and energy figures have been obtained for the design. Results indicate that a hardware implementation of IBC would meet the strict energy constraint required of a wireless sensor network node.

Complementary metal-oxide semiconductor-compatible silicon carbide pressure sensors based on bulk micromachining

This Letter presents a complementary metal-oxide semiconductor-compatible silicon carbide (SiC) absolute capacitive pressure sensor for harsh environmental applications. The pressure sensor was fabricated by bulk micromachining technology. Low-temperature SiC film was deposited by the plasma-enhanced chemical vapour deposition process and utilised as the moveable membrane of the device. Even though the deposited film has a good mechanical property and high chemical resistance, it takes low electric conductivity, thus tungsten(W) was used as the sensor's electrodes. This pressure sensor exhibits a linear response over a pressure range of 2 bars, with a total change of 507.1 mV (i.e. 0.274 pF). Furthermore, it is confirmed to withstand KOH etching for more than 30 min.

Latency/area analysis and optimization of asynchronous nanowire reconfigurable crossbar system

With continued scaling of complementary metal-oxide-silicon (CMOS) technology, numerous challenges have arisen making it difficult to progress with. These challenges include the increase of integrated circuit complexity, non-recoverable expenses, frequency and power density. Nanotechnologies are expected to take the forefront of continuing the technological revolution. In this work, a novel model-based latency/area analysis and optimization method for the newly proposed Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA) is presented and validated. ANRCA is based on a self-timed logic referred to as the Null Convention Logic (NCL). There is no global clocking and clock distribution network, all failure modes related to timing will be either eliminated or relaxed. The proposed architecture is anticipated to have higher manufacturability and robustness that are critical factors in nanoscale systems due to the nondeterministic nature of nanoassemblies and also suitable computing frameworks for asynchronous nanoscale communication networks. In order to facilitate efficient programming and flexible reconfiguration, a new hierarchical reconfigurable architecture for ANRCA is also proposed. Various configurable logic block structures have been considered and also their programming and reconfiguration issues are discussed. The proposed measurement and optimization method can be used to estimate area and latency measurements for different configurable logic blocks and also applied to find the optimal structure for the given arbitrary logic to map.

Self-Assembled Monopole Antennas With Arbitrary Shapes and Tilt Angles for System-on-Chip and System-in-Package Applications

The design, fabrication and measurement of self-assembled vertical and oblique monopole antennas, are presented. Vertical on-chip antennas offer advantages over conventional on-chip planar antennas, most notably potentially higher efficiency with associated superior coupling between distant and adjacent ports along the direction of the chip plane. The fabrication method enables lithographical specification of the monopole profile and its sloping angle so that the orientation and shape of monopoles can be controlled. The fabrication process uses SU-8 material and is performed under 200°C and is therefore compatible with many commercial microelectronic fabrication processes such as complementary metal-oxide silicon (CMOS) technology. This allows the integration of the antennas with CMOS front ends and other signal processing stages for communications or sensing.

Novel automatic endotracheal position confirmation system: Mannequin model algorithm evaluation

A novel endotracheal intubation accurate positioning confirmation system based on image classification algorithm is introduced and evaluated using a mannequin model. The system comprises a miniature complementary metal oxide silicon sensor (CMOS) attached to the tip of a semi rigid stylet and connected to a digital signal processor (DSP) with an integrated video acquisition component. Video signals acquired and processed by an algorithm implemented on the processor. During mannequin intubations, video signals were continuously recorded. A total of 10 videos were recorded. From each video, 7 images of esophageal intubation and 8 images of endotracheal intubation (in which the carina could be clearly seen) were extracted, yielding a total of 150 images taken from arbitrary positions and angles which were processed by the confirmation algorithm. The performance of the confirmation algorithm was evaluated using a leave-one-out method: in each iteration, 149 images were used to train the system and estimate the models, and the remaining image was used to test the system. This process was repeated 150 times such that each image participated once in testing. The system correctly identified 80 out of 80 endotracheal intubations and 70 out of 70 esophageal intubations. This fully automatic image recognition system was used successfully to discriminate airway carina and non-carina endotracheal tube positioning. The system had a 100% success rate using a mannequin model and therefore further investigation including live tissue model and human research should follow.

Pixel Scaling in Complementary Metal Oxide Silicon Image Sensor with Lateral Overflow Integration Capacitor

Two wide dynamic range (DR) complementary metal oxide silicon (CMOS) image sensors (CIS) with lateral overflow integration capacitor (LOFIC) have been developed in order to scale down the pixel size. A checker-pattern CIS has achieved high area-efficiency for the full well capacity (FWC) by introducing the rectangle structure and placing the color-filters and on-chip microlens along the direction at an angle of 45°. A shared two pixels CIS has achieved small pixel pitch by introducing a lateral overflow gate that overflows over-saturated photoelectrons from the photodiode to the LOFIC directly. These CISs were fabricated using the 0.18-µm 2-polycrystalline 3-metal CMOS technology with buried-pinned-photodiode process and achieved the high FWC, low noise, wide DR and high resolution performances. These structures are effective for obtaining the small pixel size with the advantageous characteristics of LOFIC CIS. In this paper, these structures, operation methods and measurement results of these CISs have been discussed.

Resonance Raman Study on Carbon Nanotubes Formation

Carbon nanotubes can be obtained from variety of the molecular precursors in chemical vapor deposition processes. The low growth temperatures strongly increase the compatibility of carbon nanotubes growth with current complementary metal–oxide–silicon technology for carbon nanotubes-based electronics. Here, we show the low temperature growth of multiwalled carbon nanotubes in acetylene chemical vapor deposition with Fe–Co/MgO. The catalyst mix was active already at 450◦C. The higher temperatures growth (500◦C and 550◦C) were also tested in order to estimate the best thermal condition in respect of the sample quality (via thermogravimetric analyzer) and the sample relative purity (via resonance Raman spectroscopy). High resolution transmission electron microscope was used to determine the morphology of the samples.

Affordable terahertz electronics

Complementary metal oxide silicon (CMOS) technology improvements in its high-frequency capability, have made it possible to consider CMOS as a low-cost alternative for realizing systems that can expand the use of the terahertz spectral range. This article gives an overview of the progress and status of emerging CMOS technology that is needed for the widespread use of the terahertz region. The future and viability of CMOS terahertz electronics are also described and highlighted.

Radiotherapy-induced pacemaker and implantable cardioverter defibrillator malfunction

It is well known that ionizing radiation can interfere with circuits in permanent pacemakers and implantable cardioverter defibrillators. Contemporary implantable cardiac devices use complementary metal-oxide silicon in combination with other very sensitive transistors. These sensitive components are especially susceptible to electromagnetic and ionizing radiation, which can potentially cause permanent damage. Electromagnetic interference is, in general, a transient phenomenon. Radiologic imaging tests have been implicated in rare cases of implantable device dysfunction and these events have been mostly transient. The American Association of Physicists in Medicine last published recommendations regarding irradiation of pacemakers in 1994. This publication is outdated and may not be pertinent for the current technology used both in the field of artificial cardiac pacing and defibrillation and in the field of radiation oncology. Updated guidelines are definitely needed.

Complementary Metal–Oxide–Silicon Field-Effect-Transistors Featuring Atomically Flat Gate Insulator Film/Silicon Interface

In this paper, we demonstrate newly developed process technology to fabricate complementary metal–oxide–silicon field-effect transistors (CMOSFETs) having atomically flat gate insulator film/silicon interface on (100) orientated silicon surface. They include 1,200 °C ultraclean argon ambient annealing technology for surface atomically flattening and radical oxidation technology for device isolation, flatness recovery after ion implantation, and gate insulator formation. The fabricated CMOSFET with atomically flat interface exhibit very high current drivability such as 923 and 538 µA/µm for n-channel MOSFET (nMOS) and p-channel MOSFET (pMOS) at gate length of 100 nm when combined with very low resistance source and drain contacts, four orders of magnitude lower 1/ f noise characteristics when combined with damage free plasma processes, and one decade longer time dependent dielectric breakdown (TDDB) lifetime in comparison to devices with a conventional flatness. The developed technology effectively improves the performance of the silicon-based CMOS large-scale integrated circuits (LSI).

The Correlation of DIFOTI to Clinical and Radiographic Images in Class II Carious Lesions

The authors conducted a study to evaluate the correlation between digital imaging fiber-optic transillumination (DIFOTI) (KaVo Dental, Lake Zurich, Ill.) and clinical and radiographic images in estimating the true clinical axial extension of Class II carious lesions. The authors examined 51 Class II carious lesions visually, imaged them by means of DIFOTI and radiographed them with D-speed film and a complementary metal oxide silicon (CMOS)-based digital radiographic sensor. They validated axial extension of the lesions clinically. They compared the clinical and radiographic depths of the carious lesion with the size of the lesion on the DIFOTI images. The authors detected 84 percent of the lesions with DIFOTI, and 82 percent showed a visible dark shadow under the marginal ridge when examined clinically. DIFOTI correlated significantly with the clinical depth of decay (Pearson r = 0.43189). The combination of a CMOS digital sensor and DIFOTI (R2 = 0.7210) provided readings closer to the clinical measures than did the combination of D-speed film and DIFOTI (R2 = 0.6215). DIFOTI images correlated with clinical depth, especially in smaller lesions, and improved the estimation of lesion size when used in conjunction with the CMOS digital sensor and D-speed images. Using radiographs in combination with DIFOTI images could help clinicians determine the presence and, to some extent, the size of proximal caries, especially in smaller lesions.

HIGH SENSITIVITY AND HIGH DYNAMIC RANGE OPTICAL MICRO-RADIATOR VACUUM SENSOR FABRICTED WITH CMOS TECHNOLOGY

A Complementary Metal Oxide Silicon (CMOS) optical micro-radiator vacuum sensor has been designed, tested and calibrated. The package is comprised of a micromachined radiator and a photodetector. The sensitivity improvement of the system over the conventional Pirani gauge is up to nine magnitudes depending on the operating power of the micro-radiator. To increase sensor's dynamic range, an automated power-switching system has been demonstrated for pressure sensing operated with constant photodetector output. Calibration of the system has been performed by comparison with secondary standards. Experimental results showed that the sensor's measurement range from 10-3 Pa to 105 Pa has been achieved as its relative error is less than 8%.

Complementary metal oxide silicon integrated circuits incorporating monolithically integrated stretchable wavy interconnects

Stretchable complementary metal oxide silicon circuits consisting of ultrathin active devices mechanically and electrically connected by narrow metal lines and polymer bridging structures are presented. This layout—together with designs that locate the neutral mechanical plane near the critical circuit layers—yields strain independent electrical performance and realistic paths to circuit integration. A typical implementation reduces the strain in the silicon to less than ∼0.04% for applied strains of ∼10%. Mechanical and electrical modeling and experimental characterization reveal the underlying physics of these systems.

CMOS driven micro-pixel LEDs integrated with single photon avalanche diodes for time resolved fluorescence measurements

We describe a single chip approach to time resolved fluorescence measurements based on time correlated single photon counting. Using a single complementary metal oxide silicon (CMOS) chip, bump bonded to a 4 × 16 array of AlInGaN UV micro-pixellated light-emitting diodes, a prototype integrated microsystem has been built that demonstrates fluorescence excitation and detection on a nanosecond time scale. Demonstrator on-chip measurements of lifetimes of fluorescence colloidal quantum dot samples are presented.

An ultrahigh vacuum complementary metal oxide silicon compatible nonlithographic system to fabricate nanoparticle-based devices

Nanoparticles of metals and semiconductors are promising for the implementation of a variety of photonic and electronic devices with superior performances and new functionalities. However, their successful implementation has been limited due to the lack of appropriate fabrication processes that are suitable for volume manufacturing. The current techniques for the fabrication of nanoparticles either are solution based, thus requiring complex surface passivation, or have severe constraints over the choice of particle size and material. We have developed an ultrahigh vacuum system for the implementation of a complex nanosystem that is flexible and compatible with the silicon integrated circuit process, thus making it suitable for volume manufacturing. The system also allows the fabrication of Ohmic contacts and isolation dielectrics in an integrated manner, which is a requirement for most electronic and photonic devices. We have demonstrated the power and the flexibility of this new system for the manufacturing of nanoscale devices by implementing a variety of structures incorporating nanoparticles. Descriptions of this new fabrication system together with experimental results are presented in this article. The system explains the method of size-selected deposition of nanoparticles of any metallic, semiconducting, and (or) insulating materials on any substrate, which is very important in fabricating useful nanoparticle-based devices. It has also been shown that at elevated substrate temperature, a selective deposition of the nanoparticles is observed near the grain-boundary regions. However, in these natural systems, there will always be low and favorable energy states present away from the grain-boundary regions, leading to the undesirable deposition of nanoparticles in the far-grain-boundary regions, too.

Deep Trench Isolation for Crosstalk Suppression in Active Pixel Sensors with 1.7 µm Pixel Pitch

A deep trench isolation (DTI) process with a 4 µm deep trench has been developed and successfully applied to 5-megapixel complementary metal oxide silicon (CMOS) image sensors with a 1.7 µm pixel pitch. It was found that from the results of simulations and experiments, DTI is very effective for reducing electrical crosstalk without degrading other pixel characteristics, such as full well capacity, sensitivity, and white spot density. Therefore, DTI could be a solution for obtaining a high performance for CMOS image sensors with a small pixel size of sub-2.0 µm.

Improved CMOS performance via enhanced carrier mobility

The amazing advancements achieved to date in Si complementary metal-oxide-silicon (CMOS) technology have come primarily from scaling, i.e. from reducing the critical dimensions of the transistors. Now that it is increasingly difficult to further reduce critical dimensions, alternative methods of improving transistor performance are also being employed. One important approach is to increase the electron and hole mobility in the transistors. Various approaches for achieving enhanced mobility in CMOS devices are reviewed. Methods for achieving defect-free strained Si structures are discussed.

A novel position and time sensing active pixel sensor with field-assisted electron collection for charged particle tracking and electron microscopy

A new type of active pixel sensors (APSs) to track charged particles for particle physics experiments or to count number of electrons that cross any pixel at the focal plane of electron microscopes is described. The electric field of desirable shape is created inside the active volume of the pixel introducing the drift component in the movement of the signal electrons towards charge collecting electrodes. The electric field results from the flow of ∼100 mA/cm 2 hole currents within individual pixels of the sensor. The proposed sensor is produced using a standard industrially available complementary metal oxide silicon (CMOS) process. There are two main advantages of the proposed detectors when compared to the present (February 2005) state-of-the-art, i.e. field-free APS sensors. The first advantage of a field-assisted transport mechanism is the reduction of the charge collection time and of the sharing of the signal electrons between adjacent pixels by diffusion. The second advantage is the freedom to use both kinds of MOS transistors within each pixel of the sensor. Thus, the full functional power of CMOS circuits can be embedded in situ. As an example, 16-bit scalers will be implemented in each pixel of the sensor for electron microscopy. The reduced collection time combined with the state-of-the-art electronics within each pixel provides the most complete information about the position and the timing of incident charged particles for particle physics experiments. Position resolution of new sensors was computationally simulated to be a few microns, that is, the same as the resolution of standard APSs. Moreover, the active depth of the sensor and the associate electronics is less than about 20 μm and a thinned down sensor together with its beryllium backing can have a total thickness of less than 0.1% of one radiation length. The reduction of the thickness of the detector reduces the amount of multiple scattering within the detector. The determination of the momentum and of the origin of a particle can be improved in particle physics experiments and images from electron microscopes can be sharper.

Fabrication of silicon-on-SiO2/diamondlike-carbon dual insulator using ion cutting and mitigation of self-heating effects

A diamondlike-carbon (DLC) layer was used to substitute for the buried SiO2 layer in silicon on insulator (SOI) to mitigate the self-heating effects in our previous study. However, we discovered drawbacks associated with the inferior Si/DLC interface, inadequate thermal stability as well as carbon-silicon interdiffusion at the Si/DLC interface that could hamper future application of this silicon-on-diamond structure to microelectronic devices. In this work, we introduced a silicon dioxide barrier layer between the Si film and DLC buried layer to form a silicon-on-SiO2∕DLC dual-insulator structure to tackle these problems. Cross-sectional high-resolution transmission electron microscopy reveals that the Si/insulator interface is atomically flat and the top Si layer has nearly perfect crystalline quality. The SiO2∕DLC dual-insulator layer retains excellent insulating properties at typical complementary metal oxide silicon processing temperatures. Numerical simulation reveals that the negative differential resistance and channel temperature are significantly reduced compared with those of the same metal oxide semiconductor field effect transistors fabricated in conventional SiO2-based SOI, suggesting that the silicon-on-dual-insulator structure can alleviate the self-heating penalty effectively.

A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting

This paper presents a standard cell-based frequency synthesizer with dynamic frequency counting (DFC) for multiplying input reference frequency by N times. The dynamic frequency counting loop uses variable time period to estimate and tune the frequency of digitally-controlled oscillator (DCO) which enhances frequency detection's resolution and loop stability. Two ripple counters serve as frequency estimator. Conventional phase-frequency detector (PFD) thus is replaced with a digital arithmetic comparator to yield a divider-free circuit structure. Additionally, a 15 bits DCO with the least significant bit (LSB) resolution 1.55 ps is designed by using the gate capacitance difference of 2-input NOR gate in fine-tuning stage. A modified incremental data weighted averaging (IDWA) circuit is also designed to achieve improved linearity of DCO by dynamic element matching (DEM) skill. Based on the proposed standard cell-based frequency synthesizer, a test chip is designed and verified on 0.35-μm complementary metal oxide silicon (CMOS) process, and has a frequency range of (18--214) MHz at 3.3 V with peak-to-peak (Pk-Pk) jitter of less than 70 ps at 192 MHz/3.3 V.