Silicon Complementary Metal Oxide Research Articles

71‐1: CMOS Backplane Technology and Its Challenge for µLEDoS AR/XR Display

This paper introduces the latest CMOS (Complementary Metal‐Oxide‐Silicon) backplane technology for µLEDoS AR/XR display engines. The backplane supports a display resolution of 1,280RGB x 720 and has been implemented on a 28nm Fully Depleted Silicon on Insular (FD‐SOI) CMOS process in order to meet the requirements such as performance, power, and pixel size. The area of a single pixel is 4.95µm x 4.95µm achieving higher than 5,000 PPI in RGB‐color mode. Each pixel contains 3 independent sub‐pixel drivers and one dependent driver assigned for a red LED. Each sub‐pixel driver includes a 10‐bit video SRAM memory, PWM (Pulse Width Modulation) control logic block, a constant current generator, and LED driver stage to drive red, green, or blue LEDs. The backplane also integrates necessary image processing functions such as De‐mura compensation, dead‐pixel compensation, and digital gamma generation. The top surface of the backplane wafer is also prepared for a wafer‐to‐wafer hybridization bonding between the CMOS wafer and an LED wafer.

Development of an Integrated CMUTs-Based Resonant Biosensor for Label-Free Detection of DNA with Improved Selectivity by Ethylene-Glycol Alkanethiols

Gravimetric resonant-inspired biosensors have attracted increasing attention in industrial and point-of-care applications, enabling label-free detection of biomarkers such as DNA and antibodies. Capacitive micromachined ultrasonic transducers (CMUTs) are promising tools for developing miniaturized high-performance biosensing complementary metal–oxide–silicon (CMOS) platforms. However, their operability is limited by inefficient functionalization, aggregation, crosstalk in the buffer, and the requirement for an external high-voltage (HV) power supply. In this study, we aimed to propose a CMUTs-based resonant biosensor integrated with a CMOS front–end interface coupled with ethylene–glycol alkanethiols to detect single-stranded DNA oligonucleotides with large specificity. The topography of the functionalized surface was characterized by energy-dispersive X-ray microanalysis. Improved selectivity for on-chip hybridization was demonstrated by comparing complementary and non-complementary single-stranded DNA oligonucleotides using fluorescence imaging technology. The sensor array was further characterized using a five-element lumped equivalent model. The 4 mm2 application-specific integrated circuit chip was designed and developed through 0.18 μm HV bipolar-CMOS-double diffused metal–oxide–silicon (DMOS) technology (BCD) to generate on-chip 20 V HV boosting and to track feedback frequency under a standard 1.8 V supply, with a total power consumption of 3.8 mW in a continuous mode. The measured results indicated a detection sensitivity of 7.943 × 10−3 μmol∙L−1∙Hz−1 over a concentration range of 1 to 100 μmol∙L−1. In conclusion, the label-free biosensing of DNA under dry conditions was successfully demonstrated using a microfabricated CMUT array with a 2 MHz frequency on CMOS electronics with an internal HV supplier. Moreover, ethylene–glycol alkanethiols successfully deposited self-assembled monolayers on aluminum electrodes, which has never been attempted thus far on CMUTs, to enhance the selectivity of bio-functionalization. The findings of this study indicate the possibility of full-on-chip DNA biosensing with CMUTs.

Design and Study the Performance of a CMOS-Based Ring Oscillator Architecture for 5G Mobile Communication

Oscillator circuits are used to make accurate and reliable clock signals for systems as simple as a wristwatch and as complicated as satellites, which are important for long-distance communication. There are many ways to build an oscillator circuit, using either passive or active parts. Each option has pros and cons, but at the current level of mobile communication development, the most important things are interoperability and low power use. This need has driven the development of compact, battery-operated electronics, and Very Large-Scale Integration (VLSI)-based ring oscillators provide the ideal solution. These oscillators ought to dissipate less power, have a large tuning range, and be compact. The paper presents a novel Complementary Metal Oxide Silicon (CMOS) ring oscillator that serves as a Voltage Controlled Oscillator. The suggested architecture utilizes the advantages of both a current-starved ring oscillator and a negative-skewed delay by combining their constituent parts. The proposed architecture has a control voltage of 1.15 V and a supply voltage of 2 V, generating a 9.35 GHz dominant frequency with a 13.82% harmonic distortion between the inputs and outputs. The proposed architecture can implement 5G-based applications that require high frequency and low power by carefully selecting the passive components within the design. Doi: 10.28991/ESJ-2024-08-01-020 Full Text: PDF

A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces

A three-level pulse amplitude modulation (PAM-3) transceiver (TRX) with improved simultaneous switching output (SSO) noise and reference voltage margin was studied. PAM-3 signaling with an insertion of 3 bits in 2-unit intervals (UI) was implemented using the upper, under, and ground voltages, achieving 150% pin efficiency. The ground-referenced signaling (GRS) charge pump driver reduced SSO noise and maintained ground as the solitary return current path. Capacitive peaking and middle edge-rate boosting were implemented for transmitter (TX) equalization. With the receiver (RX), the ground level was used as a reference voltage for a single-to-differential (S2D) amplifier. PAM-3 signaling was converted to binary data using the time-domain decision technique in comparators. The decision time of comparators for data and reference voltage was compared. This technique shows the increased voltage margin, the reduced decision time, and the decreased error rate. The reduced decision time improved the performance of the PAM-3 decision feedback equalizer (DFE). A clock disabled the circuit, and a low-power return-to-zero (RZ) to non-RZ (NRZ) converter was configured for the proposed comparator output cases. The prototype TRX was fabricated in a 28-nm complementary metal–oxide silicon (CMOS) process with a surface area of 0.006 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . The total power efficiency was recorded as 1.09 pJ/b at 33 Gb/s/pin. Through the flame retardant-4 (FR-4) 20-mm printed circuit board (PCB) channel and coaxial cable, a bit error rate (BER) of 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-12}$</tex-math> </inline-formula> was measured.

A 211-to-263-GHz Dual-LC-Tank-Based Broadband Power Amplifier With 14.7-dBm P SAT and 16.4-dB Peak Gain in 130-nm SiGe BiCMOS

This article presents a broadband sub-terahertz (THz) power amplifier (PA) with a low-loss four-way power combiner. The proposed power combiner consists of an improved zero-degree combiner (ZDC) and a three-conductor Marchand balun simultaneously achieving broadband matching and power combining. The proposed three-conductor Marchand balun adopts a dual- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> tank technique by merging two resonators, and it can be equivalent to a transformer-based multi-resonating network. The power distribution is realized by one input power splitter generating two pairs of differential signals and two parallel 1-to-2 active power splitters. This hybrid distribution driving network further enhances efficiency and power gain. Based on these improvements, a high-output-power sub-THz PA with superior efficiency has been fabricated in the 130-nm SiGe bipolar complementary metal oxide silicon field effect transistor (BiCMOS) technology. The three-stage PA achieves a peak power gain of 16.4 dB, 3-dB small-signal gain bandwidth of 52 GHz from 211 to 263 GHz, a measured maximum saturated output power of 14.7 dBm at 224 GHz, and a peak power-added efficiency (PAE) of 3.13% at 220 GHz. The folded input splitter and extremely compact power combining methodology lead to a core area of 770 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times \,\,280\,\,\mu \text{m}$ </tex-math></inline-formula> .

CMOS Platform for Everyday Applications Using Submillimeter Electromagnetic Waves

CMOS (Complementary Metal Oxide Silicon) integrated circuits (ICs) technology is emerging as a means for realization of capable and affordable systems that operate at frequencies near 300GHz and higher. This is lowering a key barrier for utilizing the sub-millimeter electromagnetic waves in everyday applications. Despite the fact that the unity maximum available gain frequency, fmax of NMOS transistors (with connections to the tope metal layer) has peaked at 320 GHz, signal generation up to 1.33 THz, coherent detection up to 1.2 THz and incoherent detection up to 10 THz have been demonstrated using CMOS integrated circuits. Furthermore, highly integrated rotational spectroscopy transceivers operating at frequencies up to near 300 GHz, 300-GHz and 400-GHz concurrent transceiver pixels and arrays for high resolution radar imaging, and 300-GHz and 390-GHz transmitters, and 300-GHz receivers for high data-rate communication have been demonstrated in CMOS. The performances of these CMOS circuits are sufficient or close to being sufficient to support electronic smelling using rotational spectroscopy that can detect and quantify concentrations of a wide variety of gases; imaging that can enable operation in a wide range of visually impaired conditions; and high-bandwidth communication. Lastly, techniques for affordable packaging and testing sub-millimeter wave systems are suggested based on experimental demonstrations.

A Switched-Capacitor, Integrator-Multiplexing, Second-Order Delta-Sigma Modulator Featuring a Single Differential Difference Amplifier for Portable EEG Application

We present a novel switched-capacitor, integrator-multiplexing, second-order delta-sigma modulator (DSM) featuring a single differential difference amplifier (DDA). Power consumption is low and resolution is high when this DSM is used for portable electroencephalographic applications. A single DDA (rather than a conventional operational transconductance amplifier) with appropriate switch and capacitor architectures is used to create the second-order switched-capacitor DSM. The configuration ensures that the resolution is high. The modulator was implemented using a standard 180 nm complementary metal–oxide–silicon process. At a supply voltage of 1.8 V, a signal bandwidth of 250 Hz and a sampling frequency of 200 kHz, simulations demonstrated that the modulator achieved an 82 dB peak signal-to-noise–distortion ratio and an effective number of bits of 14.

Grazing-Angle Fiber-to-Waveguide Coupler

The silicon photonics market has grown rapidly over recent decades due to the demand for high bandwidth and high data-transfer capabilities. Silicon photonics leverage well-developed semiconductor fabrication technologies to combine various photonic functionalities on the same chip. Complicated silicon photonic integrated circuits require a mass-producible packaging strategy with broadband, high coupling efficiency, and fiber-array fiber-to-chip couplers, which is a big challenge. In this paper, we propose a new approach to fiber-array fiber-to-chip couplers which have a complementary metal-oxide semiconductor-compatible silicon structure. An ultra-high numerical aperture fiber is polished at a grazing angle and positioned on a taper-in silicon waveguide. Our simulation results demonstrate a coupling efficiency of more than 90% over hundreds of nanometers and broad alignment tolerance ranges, supporting the use of a fiber array for the packaging. We anticipate that the proposed approach will be able to be used in commercialized systems and other photonic integrated circuit platforms, including those made from lithium niobate and silicon nitride.

TID and Heavy-Ion Performance of an RHBD Multichannel Digitizer in 180-nm CMOS

We present the design, fabrication, and radiation testing of a custom 20-channel application-specific integrated circuit (ASIC) for amplification and digitization of microvolt signal levels from space instrumentation (e.g., thermopile sensors) operating in harsh space radiation environments. The ASIC is fabricated in a commercial 180-nm complementary metal oxide silicon (CMOS) process node using a combination of radiation hard by design and discrete-time analog signal processing to mitigate leakage, offset, 1/ f, and thermal noise. The chip has an input-referred integrated noise voltage of 190 nV in a 240-Hz bandwidth. Irradiation with very high total ionizing dose (TID) and high-energy heavy ions was carried out to evaluate the chip's radiation hardness. The chip's postradiation performance evidenced parametric immunity to greater than 50 Mrad (Si) TID and no single-event latch-up up to at least 123.6 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg linear energy transfer.

25‐1: Multi‐bit MIP(Memory‐in‐Pixel)‐based Pixel Circuit of CMOS Backplane for Micro‐LED Display

The Micro‐LED display is getting more attention in AR/MR (Augmented/Mixed Reality) applications. The display size of 0.5 to 0.7‐inch is preferred with 5,000 or higher PPI (Pixel Per Inch). Due to the pixel density and size, a CMOS (Complementary Metal‐Oxide‐Silicon) backplane is a preferred solution for driving the pixelized micro‐LEDs. This paper proposes a multi‐bit MIP‐based pixel circuit with PWM driving for a CMOS backplane in order to minimize power dissipation. it also provides an estimation of the minimum achievable pixel size based on the CMOS process node.

Study of low-peak-power highly coherent broadband supercontinuum generation through a dispersion-engineered Si-rich silicon nitride waveguide.

Since the first observation by Alfano and Shapiro in the 1970s [Phys. Rev. Lett.24, 584 (1970)PRLTAO0031-900710.1103/PhysRevLett.24.584], supercontinuum generation study has become an attractive research area in the field of broadband light source design, including its use in various applications associated with nonlinear optics in recent years. In this work, the numerical demonstration of ultrabroadband supercontinuum generation in the mid-infrared (MIR) region via the use of complementary metal-oxide semiconductor compatible Si-rich silicon nitride as the core in a planar waveguide design employing one of two materials, either LiNbO3 or MgF2 glass, as the top and bottom claddings is explored. A rigorous numerical investigation of broadband source design in the MIR using 2 mm long Si-rich silicon nitride waveguides is carried out in terms of waveguide structural parameter variations, input peak power variation, varying unexpected deformation of the waveguide along the core region during fabrication, and spectral coherence analysis. Among the several waveguide models studied, two promising designs are identified for wideband supercontinuum generation up to the MIR using a relatively low input peak power of 50 W. Simulation results reveal that spectral coverage spanning from 0.8 µm to 4.6 µm can be obtained by using a LiNbO3-cladded waveguide, and similar spectral coverage is also predicted for the other design, a MgF2-cladded waveguide. To the best of our knowledge, this is the widest spectral span in the MIR region employing a Si-rich silicon nitride waveguide so far. In dispersion tuning as well as in supercontinuum generation, the effect of possible unexpected waveguide deformation along the transverse directions during fabrication is also studied. No significant amount of spectral change is observed in the proposed model for a maximum of 10° inside/outside variation along the width. On the other hand, even 1° upward/downward variation along the thickness could cause substantial spectral change at the waveguide output. Finally, the obtained output spectra from the proposed waveguides are found to be highly coherent and can be applied in various MIR region applications such as optical coherence tomography, spectroscopic measurement, and frequency metrology.

Guest Editorial for the special issue on devices and circuits for millimeter‐wave and THz applications

Guest Editorial for the special issue on devices and circuits for millimeter‐wave and THz applications

Compact Simulation of Chip-to-Chip Active Noise Coupling on a System PCB Board

A chip-to-chip active noise coupling demonstrator integrates two identical complementary metal oxide silicon (CMOS) chips on a printed circuit board (PCB), where each chip has the capability of power noise generation by CMOS shift resister array circuits (noise source; NS) and also power noise measurements by on-chip voltage monitoring circuits (OCM). For establishing the noise aware design strategy and methodology, a full-system level noise coupling simulation technique is evaluated on the demonstrator representing a multi-chip mixed-signal PCB. In an experimental scenario, an IC chip (Aggressor IC) operates the NS to generate power noise and the OCM measures the voltage fluctuation of the power delivery network (PDN) within the chip. On the other hand, another IC (Victim IC) holds the NS in no operation while uses the OCM to monitor its PDN voltage fluctuation caused by the conducted noise from the aggressor IC. For the verification of simulation accuracy, two chip power models (CPM), package wire models, discrete de-cap models and a single PCB model are combined into a chip-package-system (CPS) integrated model. The simulation was performed in about 2 hours for CPS integrated noise simulation including S-parameter extraction of the PCB. It is demonstrated that the full-system model with the two CPMs successfully simulates chip-to-chip active noise coupling, namely noise propagation from internal circuits of an aggressor chip to those on a victim chip. The chip-to-chip noise coupling simulation exhibited good agreements with measurements in case studies. The simulation methodology enables conductive noise aware design for multi-chip mixed-signal PCB in its design stage.

Electrical power generation from moderate-temperature radiative thermal sources.

Moderate-temperature thermal sources (100° to 400°C) that radiate waste heat are often the by-product of mechanical work, chemical or nuclear reactions, or information processing. We demonstrate conversion of thermal radiation into electrical power using a bipolar grating-coupled complementary metal-oxide-silicon (CMOS) tunnel diode. A two-step photon-assisted tunneling charge pumping mechanism results in separation of charge carriers in pn-junction wells leading to a large open-circuit voltage developed across a load. Electrical power generation from a broadband blackbody thermal source has been experimentally demonstrated with converted power densities of 27 to 61 microwatts per square centimeter for thermal sources between 250° and 400°C. Scalable, efficient conversion of radiated waste heat into electrical power can be used to reduce energy consumption or to power electronics and sensors.

CMOS Backplane Pixel Circuit With Leakage and Voltage Drop Compensation for an Micro-LED Display Achieving 5000 PPI or Higher

Micro-displays based on micro-LEDs are becoming more and more attractive in AR/MR (Augmented/Mixed Reality) applications. A display size of 0.5 to 0.7-inch is preferred, with 5,000 PPI (Pixel Per Inch) or higher. Due to this pixel density and size, a CMOS (Complementary Metal-Oxide-Silicon) backplane is an ideal solution to drive these pixelized micro-LEDs. As the required pixel size gets smaller, the design of the appropriate pixel circuit becomes more challenging. The simplest 2T1C (2 transistors & 1 capacitor) pixel circuit has potential problems, due to the leakage current of the switch transistor and the voltage drop on the matrix array layout. In this paper, a pixel circuit is proposed as a solution to overcome these two issues. Our simulation results show that the variation of the driving current to the LED is improved by 95 %, and the IR drop error rate is around 2.2 % compared to the 2T1C circuit. The test results also show that the error rate of IPIXEL for the whole region of display is under 2.5 %. This work is verified using a test chip implementation with 180 nm CMOS process technology.

Achieving High-Quality Sn-Pb Perovskite Films on Complementary Metal-Oxide-Semiconductor-Compatible Metal/Silicon Substrates for Efficient Imaging Array.

Although Sn-Pb perovskites sensing near-ultraviolet-visible-near-infrared light could be an attractive alternative to silicon in photodiodes and imaging, there have been no clear studies on such devices constructed on metal/silicon substrates, hindering their direct integration with complementary metal-oxide semiconductor (CMOS) and silicon electronics. Typically, high surface roughness and severe pinholes of Sn-rich binary perovskites make it difficult for them to fulfill the requirements of efficient photodiodes and imaging. These issues cause inherently high dark current and poor (dark and photo-) current uniformity. Herein, we propose and demonstrate the room-temperature crystallization in the Sn-rich binary perovskite system to effectively control film crystallization kinetics. With experimental and theoretical studies of the crystallization mechanism, we successfully tune the density and location of nanocrystals in precursor films to achieve compact nanocrystals, which coalesce into high-quality (smooth, dense, and pinhole-free) perovskites with intensified preferred orientation and decreased trap density. The high-quality perovskites reduce dark current and improve (dark and photo-) current uniformity of perovskite photodiodes on CMOS-compatible metal/silicon substrates. Meanwhile, self-powered devices achieve a high responsivity of 0.2 A/W at 940 nm, a large dynamic range of 100 dB, and a fast fall time of 2.27 μs, exceeding those of most silicon-based imaging sensors. Finally, a 6 × 6 pixel integrated photodiode array is successfully demonstrated to realize the imaging application. The work contributes to understanding the fundamentals of the crystallization of Sn-rich binary perovskites and advancing perovskite integration with Si-based electronics.

Contrast of latch-up induced by pulsed gamma rays in CMOS circuits after neutron irradiation and TID accumulation

We investigate the difference in the probability of latch-up occurrence in complementary metal–oxide–silicon (CMOS) circuits exposed to neutron radiation and total ionizing dose (TID), which are subsequently exposed to pulsed gamma rays. First, we irradiate three types of CMOS circuits in a reactor for neutron exposure and in a Co-60 unit for TID exposure respectively, which are then placed in a pulsed gamma-ray environment. The latch-up induced by pulsed gamma-ray irradiation is studied. Our experimental results indicate that the manifestation of the latch-up phenomenon is different among the devices after neutron irradiation and TID exposure, thereby indicating that the influences of neutron and TID exposures on the latch-up sensitivity are different. To understand how the latch-up sensitivity changes, we study a dynamic model for latch-up occurrence and analyse the influences of neutron and TID exposure using the model. Our results indicate that neutron injection reduces the susceptibility of latch-up occurrence, whereas TID exposure increases the latch-up occurrence susceptibility. Therefore, in the case of CMOS circuits exposed to pulsed gamma-ray irradiation, the latch-up threshold decreases with TID accumulation, but increases with neutron fluence augmentation. Interestingly, the latch-up threshold drops when the neutron fluence is sufficiently large, mainly because concomitant gamma rays in the reactor environment play an important role in affecting the threshold.

Current-Starved Cross-Coupled CMOS Inverter Rings as Versatile Generators of Chaotic and Neural-Like Dynamics Over Multiple Frequency Decades

The generation of chaotic signals is relevant to a multitude of applications across telecommunications, random number generation, control, and the realization of distributed sensing systems; in addition, networks of coupled chaotic oscillators replicate diverse emergent phenomena occurring in considerably larger biological neural systems. However, to date, the generation of chaotic signals by means of complementary metal-oxide-silicon (CMOS) integrated circuits has been hampered largely by the need to implement reactive elements, and by limited flexibility. In this paper, we introduce a pure CMOS implementation of a chaos generator based on three inverter rings having lengths equal to the smallest odd prime numbers, i.e., 3, 5, and 7. These rings are cross-coupled via diodes of diverse strengths enabled through pass-gates, and the inverters in the rings are independently current-starved. Through numerical simulations and experiments, it is shown that this new topology can generate chaotic signals over at least four frequency decades. Furthermore, it is demonstrated that the experimental devices have access to a multitude of qualitatively-different dynamical behaviors as a function of the starving currents. In particular, the generation of spiking and bursting signals reminiscent of action potentials are observed, both with and without slower fluctuations which resemble field potentials. Furthermore, instances of oscillation quenching are found, wherein the circuit acts as a nonlinear amplifier yielding 1/ ${f}$ -like stochastic signals. This compact and flexible topology promises to become a foundational cell in the design of integrated circuits requiring area-efficient, low-power, and controllable chaos generation.

Impact of TID on latch up induced by pulsed irradiation in CMOS circuits

Latch up (LU), an inherent destructive phenomenon owning to P-N-P-N structure in bulk Complementary Metal-Oxide -Silicon (CMOS) circuits, is highly sensitive to pulsed irradiation. A criterion for LU is concluded, and the impact of total ionizing dose (TID) on LU criterion is discussed. In the progress of accumulating TID, generated oxide trapped charges and interface states enhance surface recombination in the base of the parasitic bipolar junction transistor (PBJT), leading to increase of the base recombination current; and the trapped charges in the shallow trench isolation (STI) can also increase leakage current. In spite of hindering effect of the base recombination in PBJTs to LU, the STI leakage current plays a dominant role to gain sensitivity of LU. Experimental results confirm the fact that TID can lower the dose rate threshold for LU. For instance, the threshold in the device with doses 150 krad(Si) is nearly 50% lower than that in the pristine device. Simulations in SPICE and Sentaurus are conducted, and the results agree with that of experiments.

Ultra-High Vacuum Fabrication of Ordered Nanoparticles and Their Device Applications

Nanoparticles are important for the implementation of a variety of photonic and electronic devices with new functionalities and improved performances. While multiple photonic devices using nanoparticles have been successfully implemented, the use of nanoparticles in electronic devices have significantly lagged; one of the primary reasons being the more stringent material and surface purity requirements for such devices. While the feasibility of a variety of electronic devices based on nanoparticles have been demonstrated in the laboratory, such as nanoparticle flash memory and single electron transistors, the fabrication technique employed is electron-beam lithography, which unfortunately is not suitable for large scale manufacturing. For most electronic devices, it is typically required that the nanoparticle dimensions be in the 1 nm to 10 nm range with size variations of 10% or less. Current photolithographic techniques are not suitable for the implementation of such nanoparticles, and nonlithographic techniques are typically used for their fabrication. However, most nonlithographic techniques are based on natural self-organization processes and suffer from a lack of flexibility or a lack of engineering control. Among the various nonlithographic techniques, the predominant ones are solution based, examples of which include sol-gel synthesis, chemical synthesis, and electrochemical synthesis inside self-organized nanoporous templates. While such solution based techniques can produce nanoparticles with the required dimensions and size distributions, they also need complex surface passivation involving capping molecules to prevent aggregation. These capping molecules modify the electrical surface properties of the nanoparticles making charge injection/extraction difficult. In addition, the solution based synthesis techniques are not compatible with the silicon integrated circuit (IC) process, in particular the Complementary Metal Oxide Silicon (CMOS) process, which is the predominant manufacturing process for electronic devices. It is widely believed that the availability of a CMOS compatible nanoparticle fabrication technique can greatly increase the viability of nanoparticle based electronic devices. We have developed a CMOS compatible ultra-high vacuum system for the implementation of nanoparticle based electronic devices that addresses the above issues. The system consists of (i) a nanoparticle unit that provides the capability to deposit nanoparticles of any metal, semiconductor or insulator of diameters as low as 1 nm with less than 5% size variation on an arbitrary substrate, (ii) a 4-pocket electron-beam evaporation unit that allows the in-situ deposition of four different materials (metals or insulators) with less than 5% thickness uniformity, and (iii) a UHV pulsed DC sputter source that allows the in-situ deposition of thick layers of insulators (semiconductors or metals) including isolation dielectrics. The nanoparticle deposition unit, the ohmic contact metallization unit and the isolation dielectric deposition unit are all housed inside an ultra-high vacuum (10-10 torr) chamber to ensure high purity and good surface properties of the nanoparticles. The nanoparticle deposition system is based on sputtering, thus making it possible to deposit nanoparticles of any material that can be sputtered. In addition, nanoparticle deposition can be carried out at room temperature, making it possible to deposit the nanoparticles on a variety of substrates including flexible substrates. Size selection of nanoparticles is achieved by using a quadrupole mass filter with the capability to provide as low as 2% size control. One advantage of the system is that ohmic contacts and isolation dielectrics can be formed in an integrated manner without breaking vacuum, which is important for electrical continuity. In addition, the deposited nanoparticles can be embedded in, or coated with, metallic, semiconducting or insulating layers without breaking vacuum, thus making complex multi-layered structures possible that can have applications in a variety of fields including nanoscale detectors, nano-optics, nano-sensors, field-emitters etc. For nanoparticle based electronic devices to function properly, it is essential that the nanoparticles are physically separated from each other. In addition, if the nanoparticles can be ordered in a periodic manner, it can significantly improve device reliability and performance. To address these issues, we have developed a technique for the electrical ordering of the nanoparticles that can be carried out in-situ without breaking vacuum. The ordering process is rapid, does not require physical contact with nanoparticles and thus prevents contamination. We have used the system and technique for the deposition of a variety of nanoparticles of metals and semiconductors including Ni, Fe, Co, Au, Ag, Cu, Si, CdTe, CdSe, ZnS on a variety of substrates including silicon, silicon dioxide coated Si, metal coated silicon, quartz, sapphire. We have also fabricated complex structures containing nanoparticles for various applications In this presentation, we will provide details of the apparatus, fabrication process, experimental results as well some of the nanoparticle based electronic devices currently being developed.