Complementary Metal Oxide Semiconductor Wafer Research Articles

5 Gs/s 등가 시간 샘플링을 통한 K-Band UWB 레이다 송수신기

In this paper, a K-band complementary metal-oxide-semiconductor (CMOS) ultra-wide-band (UWB) radar is presented. Using an equivalent time sampling technique with a delay-locked loop (DLL), virtual 5 Gs/s high-speed sampling is implemented without using a high-speed analog–digital converter. The receiver comprises a low-noise amplifier, radiofrequency variable amplifier, mixer, and baseband analog, whereas the transmitter comprises switching and driver amplifiers. For the UWB signal, a voltage-controlled oscillator-based impulse generator provides a periodic pulse signal using a switching amplifier controlled by a DLL clock. The proposed UWB radar SoC is fabricated using a 65 nm CMOS wafer, and the measured conversion gain and noise figure of the radar receiver are 79 dB and 7.4 dB, respectively, at 24 GHz. Consequently, we confirm that the measurement of the 11.3 m standard sphere is feasible.

Overview of CMOS Sensors for Future Tracking Detectors

Depleted Complementary Metal-Oxide-Semiconductor (CMOS) sensors are emerging as one of the main candidate technologies for future tracking detectors in high luminosity colliders. Their capability of integrating the sensing diode into the CMOS wafer hosting the front-end electronics allows for reduced noise and higher signal sensitivity, due to the direct collection of the sensor signal by the readout electronics. They are suitable for high radiation environments due to the possibility of applying high depletion voltage and the availability of relatively high resistivity substrates. The use of a CMOS commercial fabrication process leads to their cost reduction and allows faster construction of large area detectors. In this contribution, a general perspective of the state of the art of CMOS detectors for High Energy Physics experiments is given. The main developments carried out with regard to these devices in the framework of the CERN RD50 collaboration are summarized.

Simple and Efficient AlN-Based Piezoelectric Energy Harvesters.

In this work, we demonstrate the simple fabrication process of AlN-based piezoelectric energy harvesters (PEH), which are made of cantilevers consisting of a multilayer ion beam-assisted deposition. The preferentially (001) orientated AlN thin films possess exceptionally high piezoelectric coefficients d33 of (7.33 ± 0.08) pC∙N−1. The fabrication of PEH was completed using just three lithography steps, conventional silicon substrate with full control of the cantilever thickness, in addition to the thickness of the proof mass. As the AlN deposition was conducted at a temperature of ≈330 °C, the process can be implemented into standard complementary metal oxide semiconductor (CMOS) technology, as well as the CMOS wafer post-processing. The PEH cantilever deflection and efficiency were characterized using both laser interferometry, and a vibration shaker, respectively. This technology could become a core feature for future CMOS-based energy harvesters.

(Invited) Adhesive Wafer Bonding for Heterogeneous System Integration

Heterogeneous integration of micro- and nano-electromechanical systems (MEMS, NEMS) and photonic devices on top of integrated circuits (ICs) is an emerging technology that will lead to highly compact devices combining traditional ICs with advanced sensors and actuators. Different components, such as MEMS, photonic devices, and complementary metal oxide semiconductor (CMOS) circuits are fabricated on separate substrates and subsequently joined into one single substrate by wafer bonding [1,2]. This enables the integration of high-performance MEMS, NEMS, and photonic devices made of materials such as mono-crystalline silicon, germanium, III–V materials, piezoelectric materials, shape memory alloys (SMAs), carbon nanotubes (CNT), or nanowires directly on top of ICs, which is otherwise not possible. We review heterogeneous integration approaches for various MEMS, NEMS, and photonics systems based on layer transfer by adhesive wafer bonding. The main advantages of adhesive wafer bonding are the low bonding temperatures (20 - 450°C), its insensitivity to wafer surface topology, the compatibility with standard CMOS wafers, and the ability to join practically any wafer materials [3]. Adhesive wafer bonding does not require special wafer surface treatments, such as planarization or excessive cleaning, and therefore, offers a simple and cost-effective transfer process. Layer transfer by adhesive wafer bonding consists of several steps. First, the donor wafer, containing the layer to be transferred, is aligned to the target wafer (e.g. CMOS wafer) and bonded using an intermediate polymer adhesive. Second, the bulk material (e.g. Si substrate) of the donor wafer is sacrificially etched while the transferred layer remains on the target wafer of top of the polymer layer. The transferred layer can subsequently be further processed using conventional process steps to create the desired devices. Compatible processes include structuring and etching of the transferred layer, material deposition such as chemical and physical vapour deposition (CVD, PVD), ion implantation, and annealing amongst others. These processes can be used to create electrical, mechanical, and photonic devices and electrical interconnections between the transferred layers and the underlying substrate (vias). Using adhesive bonding with an intermediate polymer further offers highly selective and controlled sacrificial release etching capabilities in O2 plasma. This provides a simple approach for realizing free-standing MEMS and NEMS structures without wet etching and critical point drying (CPD), thus increasing manufacturing yield and reducing fabrication complexity. Lastly, the presented heterogeneous integration approach is compatible with pre-structuring of the target substrates, as well as of the transfer layer. Thus, it is possible to integrate not only layers of high-performance materials, but pre-processed devices and systems. We illustrate the versatility of adhesive wafer bonding for heterogeneous integration with different application examples of MEMS and optical systems integrated onto various target substrates. Each example requires a slightly different heterogeneous integration approach. A suspended Si/SiGe quantum-well infrared microbolometer array was integrated on top of a CMOS substrate by adhesive transfer bonding of the Si/SiGe thermistor layer and subsequent patterning of the bolometer array [4]. Since the bolometer pixels needed to be suspended, Ni pillars were formed and the polymer adhesive was sacrificially removed to free-etch the bolometer pixels. The Ni pillars provide both electrical connection to the underlying CMOS circuits and mechanical support for the suspended bolometer pixels. For the integration of nano-electromechanical (NEM) switches for ultra-low power computing applications, TiW vias were used as electrical interconnects. In order to achieve short signal path lengths and thereby increase the performance and energy efficiency of the circuits, an ultra-thin adhesive bonding layer of just 200 nm was used. In optical systems that don’t require electrical interconnections, the polymer adhesive itself can be used as mechanical support. Finally, the capability for multiple layer transfer steps was demonstrated by fabricating hidden hinge micromirror arrays [5]. In this approach, a layer of mono-crystalline silicon was transferred onto the target wafer and the mirror hinges were subsequently patterned in this layer. Pillars extending from the hinge layer to the target substrate were formed, but the polymer adhesive was not removed at this stage. Instead, a second mono-crystalline silicon layer was transferred on top of the hinge layer using adhesive bonding. The mirrors are then formed in this second transferred layer. Pillars connecting the mirrors to the hinges were formed and finally both polymer adhesive layers were sacrificially removed in O2-plasma, thus, creating free-standing micromirrors. In conclusion, the flexibility to precisely control the thickness of the adhesive polymer layers and selectively remove it makes adhesive wafer bonding a highly versatile approach for heterogeneous integration of a large variety of MEMS and photonic applications. Figure 1

A CMOS Compatible MEMS Pirani Vacuum Gauge with Monocrystal Silicon Heaters and Heat Sinks**Supported by the National High Technology Research and Development Program of China under Grant No 2015AA042602.

We present a micro-Pirani vacuum gauge using the low-resistivity monocrystal silicon as the heaters and heat sinks fabricated by the post complementary metal oxide semiconductor (CMOS) microelectromechanical system (MEMS) process. The metal interconnection of the device is fabricated by a 0.5 μm standard CMOS process on 8-inch silicon wafer. Then, a –Si low-temperature fusion bonding is developed to bond the CMOS wafer and the MEMS wafer, with the electrical connection realized by the tungsten through silicon via process. Wafer-level AlGe eutectic bonding is adopted to package the Pirani gauge in a non-hermetic cavity to protect the gauge from being damaged or contaminated in the dicing and assembling process, and to make it suitable for actual applications. To increase the accuracy of the test and restrain negative influence of temperature drift, the Wheatstone bridge structure is introduced. The test results show that before capping, the gauge has an average sensitivity of 1.04 × K· in dynamic range of 0.01–20 Torr. After capping, the sensitivity of the gauge does not decrease but increases to 1.12 × K· .

Heterogeneous integration of GaAs pHEMT and Si CMOS on the same chip

In this work, we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of GaAs pseudomorphic high electron mobility transistors (pHEMTs) and Si complementary metal–oxide semiconductor (CMOS) on the same Silicon substrate. GaAs pHEMTs are vertical stacked at the top of the Si CMOS wafer using a wafer bonding technique, and the best alignment accuracy of 5 μm is obtained. As a circuit example, a wide band GaAs digital controlled switch is fabricated, which features the technologies of a digital control circuit in Si CMOS and a switch circuit in GaAs pHEMT, 15% smaller than the area of normal GaAs and Si CMOS circuits.

Heterogeneous Integration of a 300-mm Silicon Photonics-CMOS Wafer Stack by Direct Oxide Bonding and Via-Last 3-D Interconnection

A fully functional Si photonics and 65-nm complementary metal-oxide semiconductor (CMOS) heterogeneous three-dimensional (3-D) integration is demonstrated for the first time in a 300-mm production environment. Direct oxide wafer bonding was developed to eliminate voids between silicon on insulator photonics and bulk Si CMOS wafers. A via-last, Cu through-oxide via 3-D integration was developed for low capacitance electrical connections with no impact on the CMOS performance. The 3-D yield approaching 100% was demonstrated on >20,000 via chains.

Dry etching for the correction of gap-induced blurring and improved pattern resolution in nanostencil lithography

We present nanostencil lithography as a new and parallel nanopatterning technique for batch fabrication of micro/nanoelectromechanical systems (MEMS/NEMS) with high throughput and resolution. We use nanostencil lithography for the purpose of integrating nanomechanical resonators into complementary metal-oxide semiconductor (CMOS) circuits. When patterning nonflat substrates, which is the case of CMOS wafers, the gap between the nanostencil membrane and the surface induces a pattern blurring that constitutes an intrinsic limitation to the maximum achievable resolution. In our case, the lateral blurring is on the order of 150 nm on each side. We present here a remedy to this limitation that is based on a corrective dry etching step that removes the excess material and which recovers the designed pattern dimensions. As a demonstration, we succeed in the patterning of an entire 100-mm-diam wafer with nanomechanical devices having lateral dimensions in the range of 200 nm.

Characterization of Reduced-pressure Chemical Vapor Deposition Polycrystalline Silicon Germanium Deposited at Temperatures ≤550 °C

This paper investigates the possibility of reducing the deposition temperature of polycrystalline silicon germanium to a level compatible with complementary metal-oxide semiconductor (CMOS) post processing. To achieve this goal, the exact wafer temperature during deposition was experimentally determined and it was found to be 30 °C lower than the reactor setting temperature. The deposition temperature was reduced from 625 to 500 °C. The impact of varying the deposition pressure from 10 to 760 torr and the germanium content from 15% to 100% was investigated. X-ray diffraction spectroscopy and transmission electron microscopy showed that the SixGe1−x films deposited at an actual wafer temperature of 520 °C are polycrystalline for germanium contents as low as 15%. Also, it was shown that the deposition conditions can be adjusted to yield a low tensile stress at an actual wafer temperature of 520 °C, which is suitable for integrating surface micromachined micro-electromechanical systems on top of standard CMOS wafers with Al interconnects.

Control of Surface Concentration of Boron or Phosphorus Employing Ion Shower Doping

An ion shower doping technique has been applied to control the surface concentration of boron or phosphorus on a silicon wafer both for p‐well and n‐well complementary metal oxide semiconductor (CMOS) wafer processes. The dose is controllable in the range from 1012 to and has a proportional relation with the doping time. Both surface impurity concentrations of boron and phosphorus within the range from 1016 to can be obtained, the range required for CMOS wafer processing. Fabricated MOS transistors have shown the characteristics comparable to those obtained from devices fabricated with ion implanters which are conventionally used in the semiconductor industry. As a result, it has been ascertained that ion shower doping can be utilized in the CMOS wafer process.

Effect of Low Temperature (

We report an increase in conductivity of As‐implanted layers achieved by rapid thermal activation of As at temperatures below that of junction anneal (900°C, , furnace, performed prior to RTA). This effect is interpreted in terms of residual inactive As reacting with vacancies generated during the heat‐treatment. We report an increase in the metal to p+contact resistance observed as a result of overheating complementary metal oxide semiconductor wafers in the process of formation in a rapid thermal reactor. Changes in the metal to p+ contact resistance with the actual wafer temperature (estimated from the observed deviation of n+ layer conductivity from the nominal values) allows for an estimate of B diffusivity in .