Complementary Metal Oxide Semiconductor Technology Nodes Research Articles

Memristor-Inspired Digital Logic Circuits and Comparison With 90-/180-nm CMOS Technologies

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1 mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density Y <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> O <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{3}}$</tex-math> </inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

Low-Cost Superconducting Fan-Out With Cell $\text{I}_\text{C}$ Ranking

Superconductor electronics (SCE) promise computer systems with orders of magnitude higher speeds and lower energy consumption than their complementary metal-oxide semiconductor (CMOS) counterparts. At the same time, the scalability and resource utilization of superconducting systems are major concerns. Some of these concerns come from devicelevel challenges and the gap between SCE and CMOS technology nodes, and others come from the way Josephson Junctions (JJs) are used. Towards this end, we notice that a considerable fraction of hardware resources are not involved in logic operations, but rather are used for fan-out and buffering purposes. In this paper, we ask if there is a way to reduce these overheads, propose the use of JJs at the cell boundaries to increase the number of outputs that a single stage can drive, and establish a set of rules to discretize critical currents in a way that is conducive to this assignment. Finally, we explore the design trade-offs that the presented approach opens up and demonstrate its promise through detailed analog simulations and modeling analyses. Our experiments indicate that the introduced method leads to a 48% savings in the JJ count for a tree with a fan-out of 1024, as well as an average of 43% of the JJ count for signal splitting and 32% for clock splitting in ISCAS'85 benchmarks.

Design and Analysis of Nanosheet Field-Effect Transistor for High-Speed Switching Applications

Self-heating effects and short channel effects are unappealing side effects of multigate devices like gate-all-around nanowire-field-effect transistors (FETs) and fin FETs, limiting their performance and posing reliability difficulties. This paper proposes the use of the novel nanosheet FET (NsFET) for complementary metal-oxide semiconductor technology nodes that are changing. Design guidelines and basic measurements for the sub-nm node are displayed alongside a brief introduction to the roadmap to the sub-nm regime and electronic market. The device had an ION/IOFF ratio of more than 105, according to the proposed silicon-based NsFET. For low-power and high-switching applications, the results were verified and achieved quite well. When an NS width increases, although, the threshold voltage (Vth) tends to fall, resulting in a loss in subthreshold effectiveness. Furthermore, the proposed device performance, like subthreshold swing ION/IOFF, was studied with a conventional 2D FET. Hence, the proposed NsFET can be a frontrunner for ultra-low power and high-speed switching applications.

Highly Miniaturized, Low-Power CMOS ASIC Chip for Long-Term Continuous Glucose Monitoring.

The objective of this work is to develop a highly miniaturized, low-power, biosensing platform for continuous glucose monitoring (CGM). This platform is based on an application-specific integrated circuit (ASIC) chip that interfaces with an amperometric glucose-sensing element. To reduce both size and power requirements, this custom ASIC chip was implemented using 65-nm complementary metal oxide semiconductor (CMOS) technology node. Interfacing this chip to a frequency-counting microprocessor with storage capabilities, a miniaturized transcutaneous CGM system can be constructed for small laboratory animals, with long battery life. A 0.45 mm × 1.12 mm custom ASIC chip was first designed and implemented using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS technology node. This ASIC chip was then interfaced with a multi-layer amperometric glucose-sensing element and a frequency-counting microprocessor with storage capabilities. Variation in glucose levels generates a linear increase in frequency response of this ASIC chip. In vivo experiments were conducted in healthy Sprague Dawley rats. This highly miniaturized, 65-nm custom ASIC chip has an overall power consumption of circa 36 µW. In vitro testing shows that this ASIC chip produces a linear (R2 = 99.5) frequency response to varying glucose levels (from 2 to 25 mM), with a sensitivity of 1278 Hz/mM. In vivo testing in unrestrained healthy rats demonstrated long-term CGM (six days/per charge) with rapid glucose response to glycemic variations induced by isoflurane anesthesia and tail vein injection. The miniature footprint of the biosensor platform, together with its low-power consumption, renders this CMOS ASIC chip a versatile platform for a variety of highly miniaturized devices, intended to improve the quality of life of patients with type 1 and type 2 diabetes.

Ultrafast silicon threshold circuitry for chaotic laser time series

Photonic computing has been intensively studied to explore the ultrahigh bandwidth of lightwaves. However, electronic support is indispensable for the post-processing and control of photonic systems owing to the difficulties encountered in all-optical processing. Herein, we demonstrate an ultrafast silicon circuitry capable of conducting thresholding operations on incoming chaotically oscillating high-bandwidth signals. Such circuits are critical elements in ultrafast random-number generators and photonic reinforcement learning that exploit chaotically oscillating time series. The circuit design, including active inductors for bandwidth expansion, and proof-of-principle fabricated device operations are demonstrated using a 180 nm silicon complementary metal–oxide–semiconductor technology node.

Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology

Abstract: This paper presents a relative study among two Ring oscillators architecture (CMOS, NMOS) and current-starved Voltage-controlled oscillator (CS-VCO) on the basis of different parameters like power dissipation ,phase noise etc. All the design has been done in 45- nm CMOS technology node and 2.3 GHz Centre frequency have been taken for the comparison because of their applications in AV Devices and Radio control. An inherent idea of the given performance parameters has been realize by thecomparative study. The comparative data shows that NMOS based Ring oscillator is good option in terms of the phase noise performance. In this study NMOS Ring Oscillator have attain a phase noise -97.94 dBc/Hz at 1 MHz offset frequency from 2.3 GHz center frequency. The related data also shows that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator evacuatea power of 1.73 mW which is quite low. Keywords: Voltage controlled oscillator (VCO), phase noise, power consumption, Complementary metal-oxide-semiconductor (CMOS), Current Starved Voltage-Controlled Oscillator (CS- VCO), Pull up network (PUN), Pull down network (PDN)

Relationship between Atomic Structure, Composition, and Dielectric Constant in Zr–SiO2 Glasses

Computational methods, or computer-aided material design (CAMD), used for the analysis and design of materials have a relatively long history. However, the applicability of CAMD has been limited by the scales of computational resources generally available in the past. The surge in computational power seen in recent years is enabling the applicability of CAMD to unprecedented levels. Here, we focus on the CAMD for materials critical for the continued advancement of the complementary metal oxide semiconductor (CMOS) semiconductor technology. In particular, we apply CAMD to the engineering of high-permittivity dielectric materials. We developed a Reax forcefield that includes Si, O, Zr, and H. We used this forcefield in a series of simulations to compute the static dielectric constant of silica glasses for low Zr concentration using a classical molecular dynamics approach. Our results are compared against experimental values. Not only does our work reveal numerical estimations on ZrO2-doped silica dielectrics, it also provides a foundation and demonstration of how CAMD can enable the engineering of materials of critical importance for advanced CMOS technology nodes.

Effect of Statistical Dopant Fluctuations on Threshold Voltage of Emerging Devices

This paper presents a comparative study on the effect of statistical dopant fluctuations on threshold voltage (Vth) of emerging and conventional metal-oxide-semiconductor (MOS) field-effect (FET) transistors (MOSFETs). In this context, three n-channel MOSFET structures representing three different complementary MOS (CMOS) technologies at the 20 nm node are considered. The structures represent a conventional device with symmetric halo or pocket regions around the n+source-drain formed by a single p-type dopant implantation; a second conventional device with symmetric p-type halo regions around the n+source-drain formed by multiple p-type dopant implantations; and an emerging epitaxial-channel device with symmetric p-type halo regions around the n+source-drain where the halo regions are formed by up-diffusion of multiple p-type buried layers from the bulk-substrate during epitaxy. For these devices, the values of Vth variance and mismatch are computed as a function of device dimensions. The results show that the multiple-halo devices, in general, offer significantly lower Vth variance and mismatch compared to the conventional single-halo devices whereas, the emerging epitaxial-channel multiple-halo MOSFETs offer the lowest Vth variability compared to the conventional devices at the same technology node. And, the value of the mismatch coefficient for the emerging technology is about 0.68 mV × μm compared to that of 1.33 and 1.07 mV × μm for the conventional single-halo and multiple-halo technologies, respectively. This study, clearly, demonstrates the benefit of the emerging epitaxial-channel buried-halo MOSFETs in significantly reducing the effect of statistical dopant fluctuations on Vth at the advanced planar CMOS technology nodes.

Data Converter Interleaving: Current Trends and Future Perspectives

Future generations of optical networks will require optical interfaces that operate beyond 1 Tb/s to keep up with the exploding worldwide Internet data capacity. The data converters, digital- to-analog converter (DAC) and analog-to-digital converter (ADC), significantly define the signal bandwidth that can be transmitted or received with an electro-optic transceiver. The foreseen improvements of complementary metal oxide semiconductor (CMOS) data converters in upcoming CMOS technology nodes do not scale to the expected interface data rates for future communications systems. To address this bandwidth requirement, parallel data converter architectures (i.e., interleaved data converters) are an intriguing solution to enable performance beyond the limits imposed by continuing traditional CMOS approaches. In this article, we discuss the performance requirements for future data converters and provide an overview of the projected evolution of fiber optic networks and the limits imposed by CMOS-only data converters. Interleaved data converter architectures, in both the electrical and optical domains, are described and discussed. Finally, an outlook is given on the future development of next generation DAC and ADC architectures. This article is based on the presentations and discussions in the workshop Super DACs and ADCs -- To or Not to Interleave at the Optical Networking and Communication Conference 2019.

Sweat Biomarker Sensor Incorporating Picowatt, Three-Dimensional Extended Metal Gate Ion Sensitive Field Effect Transistors.

Ion sensitive field effect transistors (ISFETs) form a very attractive solution for wearable sensors due to their capacity for ultra-miniaturization, low power operation, and very high sensitivity, supported by complementary metal oxide semiconductor (CMOS) integration. This paper reports for the first time, a multianalyte sensing platform that incorporates high performance, high yield, high robustness, three-dimensional-extended-metal-gate ISFETs (3D-EMG-ISFETs) realized by the postprocessing of a conventional 0.18 μm CMOS technology node. The detection of four analytes (pH, Na+, K+, and Ca2+) is reported with excellent sensitivities (58 mV/pH, -57 mV/dec(Na+), -48 mV/dec(K+), and -26 mV/dec(Ca2+)) close to the Nernstian limit, and high selectivity, achieved by the use of highly selective ion selective membranes based on postprocessing integration steps aimed at eliminating any significant sensor hysteresis and parasitics. We are reporting simultaneous time-dependent recording of multiple analytes, with high selectivities. In vitro real sweat tests are carried out to prove the validity of our sensors. The reported sensors have the lowest reported power consumption, being capable of operation down to 2 pW/sensor. Due to the ultralow power consumption of our ISFETs, we achieve and report a final four-analyte passive system demonstrator including the readout interface and the remote powering of the ISFET sensors, all powered by an radio frequency (RF) signal.

$2\times\text{VDD}$ 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation

A $2\times\text{VDD}$ output buffer for 40-nm complementary metal–oxide–semiconductor technology nodes is proposed in this investigation featured with a slew rate (SR) auto-adjusted by process, voltage, temperature, and leakage (PVTL) detection and, particularly, the leakage compensation mechanism. The output driving current is boosted by turning on extra charging paths and discharging paths when the SR is detected to be dropping. With the proposed PVTL detection and leakage compensation circuit, the SR is improved with 11.0% and 67.4% by on-silicon measurement results given different VDDIO values (1.8/0.9 V) and temperatures (from 0 °C to 100 °C), respectively. The data rate is 250/500 MHz for VDDIO at 1.8/0.9 V, respectively.

Impact of Total Ionizing Dose on the Data Retention of a 65 nm SONOS-Based NOR Flash

In this paper, the impact of total ionizing dose on the data retention behavior of a silicon-oxide-nitride-oxide-silicon-based NOR flash nonvolatile memory is studied for the first time on a deep sub-micron 65-nm complementary metal-oxide semiconductor technology node. The fundamental nonvolatile single-level cell memory element utilizes uniform Fowler-Nordheim (F-N) tunneling for both program and erase operations. The data retention behavior is investigated on a 4-Mb NOR Flash-based memory array at space-level total ionizing dose (TID) exposures up to 500 krad. Excessive TID exposure reduces the program-erase window but improves the thermal emission coefficient and, hence, improves data retention.

INDEP approach for leakage reduction in nanoscale CMOS circuits

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.

Size Dependence Effect in MgO-Based CoFeB Tunnel Junctions with Perpendicular Magnetic Anisotropy

We examine the effect of junction sizes on the magnetization reversal process and spin-transfer torque switching of the MgO-based CoFeB magnetic tunnel junctions (MTJs) with perpendicular magnetic anisotropy (PMA). From the magnetic field transport measurements, it was found that the miniaturization of MTJs inherently enhances the switching asymmetry and the PMA of the soft layer. Our micromagnetic simulations confirmed that the dipolar field from the hard layer is responsible for the switching asymmetry and the increase in perpendicular shape anisotropy induces improvement of the PMA. It was further revealed that this additional anisotropy gained from the smaller MTJ sizes is not sufficient to sustain the thermal stability to meet the long-term information storage at the state-of-the-art complementary-metal–oxide semiconductor technology node. The pulsed spin-transfer torque measurements showed that a higher current density is needed to switch the magnetization of the soft layer in MTJ with smaller lateral dimensions, which is attributed to the increase in PMA.

Chemical and electrical dopants profile evolution during solid phase epitaxial regrowth

Solid phase epitaxial regrowth (SPER) is a promising method for junction formation of sub-65 nm complementary metal–oxide–semiconductor technology nodes. This is mainly due to a high dopant activation level, easy control over electrical junction depth, excellent abruptness, and limited boron diffusion. In the present research we investigate in detail the activation process and the chemical profile change after SPER junction activation with respect to the regrowth temperature. We also obtain the electrically active profiles. We find that the process window for SPER between T=620 °C and T=740 °C offers the best activation level and has a dopant profile similar to the as-implanted. While increasing the regrowth temperature, we observe the gradual increase of the transient enhanced diffusion effect and formation of B trapping centers in the end-of-range (EOR) region. At temperatures as high as T=800 °C and T=850 °C the dopant activation beyond the original a-Si layer is observed and the high metastable B activation in the junction drops dramatically. All these changes can be associated with release of Si interstitials from the EOR region due to dissolution of 〈311〉 defects.

Physical and Electrical Characterization of ZrO2 Gate Insulators Deposited on Si(100) Using Zr ( O i ­ Pr ) 2 ( thd ) 2 and O 2

The characteristics of ultrathin films deposited using molecular oxygen and the zirconium precursor [where is isopropoxide and thd is 2,2,6,6-tetramethyl-3,5-heptanedionate] were investigated. The organometallic was dissolved as a 0.15 M solution in octane and introduced into the deposition chamber using a liquid injection system. The deposition rate was insensitive to molecular oxygen flow but changed with liquid injection rate and was thermally activated in the range 390-550°C. No evidence of Zr-C and Zr-Si bonds were found in the X-ray photoelectron spectroscopy (XPS), spectra, and carbon concentrations, atom %, the detection limit of the XPS depth profiling measurements, were obtained at the lowest deposition temperatures and deposition rates. High-resolution transmission electron microscopy showed the films to be polycrystalline as deposited, with an amorphous zirconium silicate interfacial layer. The effects of postdeposition annealing were also demonstrated. After proper annealing treatments, promising capacitance-voltage and current-voltage characteristics were achieved. A film with an equivalent oxide thickness of 2.3 nm showed current reductions of approximately two orders of magnitude when compared to but some improvements are required if these films are to be used as a gate-insulator beyond the 100 nm CMOS (complementary metal oxide semiconductor) technology node. © 2002 The Electrochemical Society. All rights reserved.

Complete Suppression of the Transient Enhanced Diffusion of B Implanted in Preamorphized Si by Interstitial Trapping in a Spatially Separated C-Rich Layer

AbstractA method for completely suppressing the transient enhanced diffusion (TED) of boron implanted in preamorphized silicon is demonstrated. Boron is implanted in a molecular beam epitaxy (MBE) grown silicon sample that has been previously amorphized by silicon implantation. The sample is then annealed in order to epitaxially regrow the amorphous layer and electrically activate the dopant. The back-flow of silicon interstitials released by the preamorphization end-of-range (EOR) damage is completely trapped by a carbon-rich silicon layer interposed by MBE between the damage and the implanted boron. No appreciable TED is observed in the samples up to complete dissolution of the EOR damage, and complete electrical activation is obtained. The method might be considered for the realization of ultra shallow junctions for the far future complementary metal-oxide semiconductor technology nodes.

Complete suppression of the transient enhanced diffusion of B implanted in preamorphized Si by interstitial trapping in a spatially separated C-rich layer

A method for completely suppressing the transient enhanced diffusion (TED) of boron implanted in preamorphized silicon is demonstrated. Boron is implanted in a molecular beam epitaxy (MBE) grown silicon sample that has been previously amorphized by silicon implantation. The sample is then annealed in order to epitaxially regrow the amorphous layer and electrically activate the dopant. The backflow of silicon interstitials released by the preamorphization end-of-range (EOR) damage is completely trapped by a carbon-rich silicon layer interposed by MBE between the damage and the implanted boron. No appreciable TED is observed in the samples up to complete dissolution of the EOR damage, and complete electrical activation is obtained. The method might be considered for the realization of ultrashallow junctions for the far future complementary metal–oxide–semiconductor technology nodes.