Complementary Metal Oxide Semiconductor Power Amplifier Research Articles

A Dual-Mode CMOS Power Amplifier with an External Power Amplifier Driver Using 40 nm CMOS for Narrowband Internet-of-Things Applications

The narrowband Internet-of-Things (NB-IoT) has been developed to provide low-power, wide-area IoT applications. The efficiency of a power amplifier (PA) in a transmitter is crucial for a longer battery lifetime, satisfying the requirements for output power and linearity. In addition, the design of an internal complementary metal-oxide semiconductor (CMOS) PA is typically required when considering commercial applications to include the operation of an optional external PA. This paper presents a dual-mode CMOS PA with an external PA driver for NB-IoT applications. The proposed PA supports an external PA mode without degrading the performances of output power, linearity, and stability. In the operation of an external PA mode, the PA provides a sufficient gain to drive an external PA. A parallel-combined transistor method is adopted for a dual-mode operation and a third-order intermodulation distortion (IMD3) cancellation. The proposed CMOS PA with an external PA driver was implemented using 40 nm-CMOS technology. The PA achieves a gain of 20.4 dB, a saturated output power of 28.8 dBm, and a power-added efficiency (PAE) of 57.8% in high-power (HP) mode at 920 MHz. With an NB-IoT signal (200 kHz π/4-differential quadrature phase shift keying (DQPSK)), the proposed PA achieves 24.2 dBm output power (Pout) with a 31.0% PAE, while satisfying −45 dBc adjacent channel leakage ratio (ACLR). More than 80% of the current consumption at 12 dBm Pout could be saved compared to that in HP mode when the proposed PA operates in low-power (LP) mode. The implemented dual-mode CMOS PA provides high linear output power with high efficiency, while supporting an external PA mode. The proposed PA is a good candidate for NB-IoT applications.

Analytical modelling of ultra‐small group delay variation of ultra‐broadband RF power amplifier using NSGA‐II algorithm

AbstractThis paper proposes a ± 9.4 ps ultra‐small group delay (GD) variation of fully integrated 65 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) over 6.5–17 GHz broadband for wireless application. The proposed CMOS PA is realised by using broadband stage, RLC inter‐stage and power stage topologies. The non‐dominated sorting genetic algorithm (NSGA‐II) is employed for PA parameter optimisation to ensure a small GD variation of ±9.4 ps over broadband with an excellent small signal gain flatness of 23.65 ± 1.85 for 6.5–17 GHz. The small GD variation of ±9.4 ps and ± 11.05 ps are attained under two cases of DC supply voltages of 2.4/1.2 V and 1.2/1.2 V, respectively. To the best of author's knowledge, the achieved GD variations are lowest among all CMOS PAs as reported so far. In addition, an analytical modelling of GD is derived to validating the minimum GD variation using zero‐pole compensation. With supply voltages of 2.4/1.2 V at 6.5 GHz, the large signal power gain, Psat and OP1dB are 26 dB, 19.3 dBm and 17.94 dBm, respectively, while peak power added efficiency (PAE) is 38.196%. At reduced supply voltages of 1.2/1.2 V, the PA achieves maximum power gain of 17.7 dB and peak PAE of 35% at 6.5 GHz. The CMOS PA occupies an area of 0.206 mm2.

Ultra-wideband CMOS power amplifier for wireless body area network applications: a review

<span lang="EN-US">A survey on ultra-wideband complementary metal-oxide semiconductor (CMOS) power amplifiers for wireless body area network (WBAN) applications is presented in this paper. Formidable growth in the CMOS integrated circuits technology enhances the development in biomedical manufacture. WBAN is a promising mechanism that collects essential data from wearable sensors connected to the network and transmitted it wirelessly to a central patient monitoring station. The ultra-wideband (UWB) technology exploits the frequency band from 3.1 to 10.6 GHz and provides no interference to other communication systems, low power consumption, low-radiated power, and high data rate. These features permit it to be compatible with medical applications. The demand target is to have one transceiver integrated circuit (IC) for WBAN applications, consequently, UWB is utilized to decrease the hardware complexity. The power amplifier (PA) is the common electronic device that employing in the UWB transmitter to boost the input power to the desired output power and then feed it to the antenna of the transmitter. The advance in the design and implementation of ultra-wideband CMOS power amplifiers enhances the performance of the UWB-transceivers for WBAN applications. A review of recently published CMOS PA designs is reported in this paper with comparison tables listing wideband power amplifiers' performance.</span>

Three-Stacked CMOS Power Amplifier to Increase Output Power With Stability Enhancement for mm-Wave Beamforming Systems

In this study, an mm-wave band complementary metal–oxide–semiconductor (CMOS) power amplifier (PA) with a two-stage differential structure was designed. An analysis of the designed PA is presented and a new structure is proposed to eliminate the possibility of oscillation in the PA, which has high gain and high output power. The designed driver stage consists of a pair of cascode amplifiers and can be advantageously applied in beamforming systems as the PA phase is converted to 0 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> /180 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> with the on/off of a common-gate (CG) bias voltage. The power stage was designed with a three-stacked structure to obtain a high output power. The stability was improved using RC and capacitive feedbacks in the power stage. We implemented the PA using the 65-nm RF CMOS process. The designed PA used supply voltages of 2.0 and 3.3 V for the driver and power stages, respectively, and its saturated output power was measured as 24.7 dBm at 22.0 GHz. In this case, P <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{1\,dB}}$</tex-math> </inline-formula> was 20.6 dBm and the peak power added efficiency (PAE) was 26.0%.

Investigation of the Specification Degradation Mechanism of CMOS Power Amplifier under Thermal Shock Test.

To investigate the critical specifications of a power amplifier (PA) under rapidly changing temperature conditions, we fabricated and tested a 0.3–1.1 GHz complementary metal–oxide–semiconductor (CMOS) PA under thermal shock tests. The results show that high- and low-temperature shocks can accelerate the degradation of critical specifications of PAs and that the critical specifications of PAs degrade with the increasing number of shocks. The main reason for the degradation of critical specifications of PAs with increasing thermal shock tests is the mismatch of thermal expansion coefficients of printed circuit boards (PCB) with FR-4 as a substrate. The results of this paper can provide a reference for the development of temperature-robust PAs design guidelines for the implementation of temperature-robust PAs using low-cost silicon technology.

A fully matched dual stage CMOS power amplifier with integrated passive linearizer attaining 23 db gain, 40% PAE and 28 DBM OIP3

PurposeThe purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA).Design/methodology/approachThe linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability.FindingsWith this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation.Practical implicationsThe proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design.Originality/valueThe proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

A 23.3 dBm CMOS power amplifier with third-order gm cancellation linearization technique achieving OIP3 of 34 dBm

PurposeThe purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE).Design/methodology/approachThe CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (gm3) to be canceled with the main PA’s fixed negative gm3. The gm3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity.FindingsFor driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc.Originality/valueIn this study, a novel cascaded gm3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

One-Chip Integration of RF MEMS Switched Capacitor and Power Amplifier Using CMOS-Compatible Post Fabrication Process

This study presents a single-chip integrated reconfigurable 180-nm complementary metal–oxide–semiconductor (CMOS) power amplifier (PA) with a radio frequency micro-electro-mechanical system (RF MEMS) switched capacitor, which is highly useful for advanced wireless mobile communication systems. The proposed reconfigurable PA prototype was designed to support the 0.9, 1.8, 2.4, and 5.0 GHz quad-bands by varying the capacitance values of the RF MEMS switched capacitor at the output matching network. The RF MEMS switched capacitor was post-fabricated on the same silicon substrate with which the PA circuit was integrated using 180-nm CMOS fabrication technology. The entire fabrication step was performed based on a CMOS-compatible low-temperature post process to avoid the performance degradation of the CMOS PA circuit. The fabricated RF MEMS switched capacitor exhibited capacitances of approximately 1.0 and 3.9 pF at a frequency of 0.9 GHz in its OFF and ON states, respectively. The measured output powers of the integrated quad-band PA were 27.13, 26.63, 26.29, and 23.43 dBm at the frequencies of 0.9, 1.8, 2.4, and 5.0 GHz with the continuous-wave signal, respectively.

Antiphase Method of the CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity

We present the possibility of a complementary metal-oxide semiconductor (CMOS) power amplifier (PA) using a driver stage composed of p-channel metal oxide semiconductor (PMOS) to enhance linearity. The PMOS driver stage is designed as a cascode structure to adapt the antiphase technique to the CMOS PA. By biasing the common-source transistor of the driver stage at the subthreshold region, we obtain a gm3 value with a positive sign to cancel out the negative gm3 of the power stage, thereby enhancing the linearity. We also investigate the effect of the bias of the cascode transistor of the driver stage on third-order intermodulation distortion and amplitude-to-phase distortion. Consequently, we show that the PMOS driver stage itself acts as a pre-distorter of the power stage. To verify the possibility of the PMOS driver stage and the proposed biasing method for the antiphase technique, we design a 2.42 GHz PA using a 180 nm RFCMOS process for wireless local area network applications. We obtain a measured maximum linear output power of 21.5 dBm with a 23.4% power-added efficiency and an error vector magnitude of 3.14%. We use an 802.11 n modulated signal with 64-quadrature amplitude modulation (QAM) (MCS7) at 65 Mb/s.

Fully integrated CMOS power amplifier using resistive current combining technique

This study presents a fully integrated complementary metal oxide semiconductor (CMOS) power amplifier (PA) covering LTE-advanced bands from 825 to 915 MHz for cellular application and the bands of 978 MHz universal access transceiver mode and 1090 MHz extended squitter mode of an automatic dependent surveillance-broadcast transmitter for the unmanned aircraft system. The 3.63 mm × 0.95 mm PA including all on-chip input and output matching networks, fabricated using the 0.18 μm CMOS process exhibits peak output power of 24 dBm, modulated output power of >22 dBm at 978 MHz, the maximum power gain of 27 dB and bandwidth of 290 MHz.

Compact high‐linearity, high‐efficiency complementary metal–oxide–semiconductor power amplifier with post‐distortion lineariser for wireless local area network and Wireless Gigabit Alliance applications

This study proposes a post-distortion linearisation technique for 5 and 60 GHz complementary metal-oxide-semiconductor (CMOS) power amplifiers (PAs). The technique improves the output 1 dB gain compression point (OP 1dB ) and power-added efficiency (PAE) of the PA when the lineariser is turned on. The 5 GHz PA that is fabricated in tsmc TM 0.18 μm CMOS achieves a 16.3 dB gain, a 20 dBm OP 1dB and a 32.6% PAE. The linearised 5 GHz PA improves the OP 1dB and PAE by 2.3 dB and 3.2% as compared to the PA without lineariser. The difference between the OP 1dB and saturated power ( P sat ) is <;0.2 dB. The 60 GHz PA was implemented in a 90 nm CMOS process with a chip area of 0.57 mm 2 . The PA achieves a 14.8 dB gain, a 16.8 dBm OP 1dB with a 16.3% PAE and a 15 GHz 3 dB bandwidth. The power difference between the OP 1dB and P sat is <;0.3 dB. The linearised 60 GHz PA improves the OP 1dB and PAE by 3.2 dB and 5.8% as compared to the PA without lineariser.

CMOS Power Amplifier on Top of Embedded Transformer for Compact Module

A small-sized high-performance complementary metal-oxide-semiconductor (CMOS) power amplifier (PA) module is presented. To reduce insertion loss of the output matching network (OMN), an off-chip transformer is designed on a FR-4 printed circuit board (PCB). To minimize the area of the OMN, the transformer is embedded underneath the PA chip. Coupling between the PA and the transformer is minimized so that the performance is not affected. For the 7.5 dB peak-to-average power ratio, 16-QAM long-term evolution signal, the proposed CMOS PA module achieves a power-added efficiency of 38.5% and an adjacent channel leakage ratio level under ${-}31$ dBc at an average output power of 27.5 dBm. The proposed technique can be used in any wireless Tx applications requiring small form-factor and high performance.

A millimeter-wave CMOS power amplifier design using high-Q slow-wave transmission lines

A three-stage 60-GHz power amplifier (PA) has been implemented in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. High-quality-factor slow-wave coplanar waveguides (S-CPW) were used for input, output and inter-stage matching networks to improve the performance. Being biased for Class-A operation, the PA exhibits a measured power gain G of 18.3 dB at the working frequency, with a 3-dB bandwidth of 8.5 GHz. The measured 1-dB output compression point (OCP1dB) and the maximum saturated output power Psat are 12 dBm and 14.2 dBm, respectively, with a DC power consumption of 156 mW under 1.2 V voltage supply. The measured peak power added efficiency PAE is 16%. The die area is 0.52 mm2 (875 × 600 μm2) including all the pads, whereas the effective area is only 0.24 mm2. In addition, the performance improvement of the PA in terms of G, OCP1dB, Psat, PAE and the figure of merit using S-CPW instead of thin film microstrip have been demonstrated. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2015.

Dual Bias Modulator for Envelope Tracking and Average Power Tracking Modes for CMOS Power Amplifier

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a 0.18-㎜ CMOS process for the 1.75 ㎓ band. For the 16-QAM LTE signal with a peakto-average power ratio of 7.3 ㏈ and a bandwidth of 5 ㎒, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 ㏈, and an adjacent channel leakage power ratio of -30 ㏈c at an average output power of 22 ㏈m, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 ㏈m.

An inductive antenna mismatch recoverable RF power amplifier

An inductive antenna mismatch recovery method is presented. The proposed method uses series LC matching network to maintain a power amplifier (PA) performance under an inductive antenna mismatch condition. This method requires only the voltage amplitude information, which reduces the complexity in implementation. This paper also presents design considerations of integrated recovery system in a complementary metal-oxide semiconductor (CMOS) process. Simulation results show that the proposed CMOS PA maintains its output power as well as efficiency very close to the well-matched 50 ? condition with inductively mismatched antenna impedance up to +j·70 which is corresponding to the voltage standing wave ratio of 2.5.

2.4-GHz Complementary Metal Oxide Semiconductor Power Amplifier Using High-Quality Factor Wafer-Level Bondwire Spiral Inductor

A complementary metal oxide semiconductor (CMOS) power amplifier (PA) using a wafer-level bondwire spiral inductor with high-quality factor (Q) is presented. The inductor is made by three top metal traces connected with bondwire loops above the CMOS chip. The proposed inductor with 2.75-nH inductance achieves a Q of 18, which is three times as much as that of a conventional CMOS standard spiral inductor at 2.4 GHz. The Q of the inductor is over 15 from 2 to 14 GHz, which can cover the frequency band of wireless sensor network and worldwide interoperability for microwave access applications. The output power and power-added efficiency of the PA with the inductor are improved by 1.5 dBm and 7% as compared with those of the fully integrated CMOS PA, respectively.

Parasitics-aware layout design of a low-power fully integrated complementary metal-oxide semiconductor power amplifier

There is a need for efficient fully integrated complementary metal-oxide semiconductor (CMOS) power amplifiers (PAs) for very low power implanted biomedical transceiver systems. However, the parasitics of on-silicon interconnections can cause significant degradation in the performance of radio frequency integrated circuits, in general, and PAs, in particular. In this article, we propose a special layout design approach, which was used to design the layout of a CMOS PA. This approach relies on modeling the interconnection wires in the simulations and optimizing their widths for minimum parasitic effects and hence optimum measured circuit performance. The PA circuit is operating at 2.45GHz and is implemented in a standard 0.18μm CMOS process. Measurement results show that at a supply voltage of 1.4V, the PA delivers an output power of 4.5mW with 28.5% power-added efficiency and a power gain of 21.5dB. Owing to the careful layout design and interconnection optimization, the implemented PA circuit shows good efficiency and demonstrates a good match between the measured and simulated performance characteristics.

A fully integrated 24-dBm CMOS power amplifier for 802.11a WLAN applications

A fully integrated 24-dBm complementary metal oxide semiconductor (CMOS) power amplifier (PA) for 5-GHz WLAN applications is implemented using 0.18-μm CMOS foundry process. It consists of differential three-stage amplifiers and fully integrated input/output matching circuits. The amplifier shows a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> of 21.8 dBm, power added efficiency of 13%, and gain of 21 dB, respectively. The saturated output power is above 24.1 dBm. This shows the highest output power among the reported 5-GHz CMOS PAs as well as completely satisfying IEEE 802.11a transmitter back off requirement.