Complementary Metal Oxide Semiconductor Inverter Research Articles

Precise p-type and n-type doping of two-dimensional semiconductors for monolithic integrated circuits

The controllable fabrication of patterned p-type and n-type channels with precise doping control presents a significant challenge, impeding the realization of complementary metal-oxide-semiconductor (CMOS) logic using a single van der Waals material. However, such an achievement could offer substantial benefits by enabling continued transistor scaling and unprecedented interlayer interconnect technologies. In this study, we devise a precise method for two-dimensional (2D) semiconductor substitutional doping, which allows for the production of wafer-scale 2H-MoTe2 thin films with specific p-type or n-type doping. Notably, we extend this approach to the synthesis of spatially selective doped 2H-MoTe2 thin films via a one-step growth method, facilitating the monolithic integration of p-type and n-type semiconductor channels. Leveraging this advancement, we successfully fabricate a chip-sized 2D CMOS inverter array that demonstrates excellent device performance and yield. Collectively, these findings represent a significant stride towards the practical incorporation of 2D semiconductors in very large-scale integration technology.

Intralayer/Interlayer Codoping Stabilizes Polarity Modulation in 2D Semiconductors for Scalable Electronics.

2D semiconductors show promise as a competitive candidate for developing future integrated circuits due to their immunity to short-channel effects and high carrier mobility at atomic layer thicknesses. The inherent defects and Fermi level pinning effect lead to n-type transport characteristics in most 2D semiconductors, while unstable and unsustainable p-type doping by various strategies hinders their application in many areas, such as complementary metal-oxide-semiconductor (CMOS) devices. In this study, an intralayer/interlayer codoping strategy is introduced that stabilizes p-type doping in 2D semiconductors. By incorporating oppositely charged ions (F and Li) with the intralayer/interlayer of 2D semiconductors, remarkable p-type doping in WSe2 and MoTe2 with air stability up to 9 months is achieved. Notably, the hole mobility presents a 100-fold enhancement (0.7 to 92 cm2 V-1 s-1) with the codoping procedure. Structural and elemental characterizations, combined with theoretical calculations validate the codoping mechanism. Moreover, a CMOS inverter and more complex logic functions such as NOR and XNOR, as well as large-area device arrays are demonstrated to showcase its applications and scalability. These findings suggest that stable and straightforward intralayer/interlayer codoping strategy with charge-space synergy holds the key to unlocking the potential of 2D semiconductors in complex and scalable device applications.

Dielectric Material and Thermal Optimization in Sidewall Spacer Design for Junctionless Nanosheet FETs at Sub- 5 nm Technology Node: An Insight into Device and Circuit Performance

This study focuses on the design and analysis of Junctionless (JL) NSFETs, with an emphasis on the influence of spacer materials and temperature variations. A different number of materials such as Air, SiO2, Si3N4, HfO2, and TiO2 are examined for sidewall spacer compatibility in the JL-NSFET. The same materials are used for dual material spacers with combinations of: Air+HfO2, Air+TiO2, SiO2+HfO2, and SiO2+TiO2. The investigations revealed that the usage of TiO2 material gives better digital and analog performance with reduced leakage currents and subthreshold swing (SS), higher on/off ratio, voltage gain of ∼79.7 dB. Exploring the dual-k spacers produced better analog performance, gate control and reduced leakages for SiO2+TiO2 owing to the usage of higher dielectric material towards the gate. Further, the reduction of temperature from 400 K to 250 K for all the single-k and dual-k spacer materials revealed that the designed JL-NSFET is a suitable candidate at lower temperatures to improve the digital and analog performance whereas not recommended for RF performance improvement. Moreover, the SiO2+HfO2 spacer-based CMOS inverter is noticed to have better gain (∼15 V/V), noise margin, and lower delays (∼5.1 ps) when compared to TiO2 spacer-based complementary metal oxide semiconductor inverter making it suitable for digital IC applications.

Heterogeneous monolithic 3D integration for hybrid vertical CMOS inverter using n-type IGTO TFT on p-type Si FET

In this work, a complementary metal oxide semiconductor (CMOS) vertical inverter using heterogeneous monolithic 3D (M3D) integration with p-type Si field-effect transistor (FET) and n-type indium-gallium-tin-oxide (IGTO) thin film transistor (TFT) was implemented and characterized. This CMOS inverter was attained by vertical stacking n-type IGTO TFT on p-type Si FET. Oxide semiconductor materials such as indium-gallium-zinc-oxide (IGZO), indium-tungsten-oxide (IWO), indium oxide (In2O3) and IGTO are being considered as potential options for channel materials in M3D integration technology due to high electrical characteristics and low temperature process. Among them, IGTO was employed as a channel material to achieve high mobility. We fabricated a n-type IGTO TFT using HfO2 and tungsten as a gate dielectric and electrode, respectively. The post-annealing process was conducted at 200–500 °C with 50 °C intervals. The IGTO TFT exhibits a high field-effect mobility (32.9 cm2/Vs), low sub-threshold swing (0.070 V/dec) and stable reliability behaviour (ΔVth < 0.4 V) against various external gate bias temperature stress tests in a low temperature (<500 °C). The stable heterogeneous vertical inverter performance such as voltage-transfer curve (VM = 1.66 V), voltage gain (30.1 V at VDD = 3 V), and noise margin (NMH = 1.22 V, NML = 1.34 V) were well behaved. This M3D integration-based hybrid CMOS inverter can be an alternative knob toward various device applications.

On the propagation delay of CMOS inverters

This research study delves into the propagation delay analysis in Complementary Metal-Oxide-Semiconductor (CMOS) inverters, aiming to uncover the factors contributing to it and exploring strategies to mitigate its impact. CMOS inverters, as pivotal constituents within digital integrated circuits, play a foundational role, making a thorough understanding of their propagation delay characteristics indispensable for the design of high-performance circuit. The research encompasses a comprehensive examination of propagation delay in CMOS inverters, addressing three key factors affecting it: load capacitance, transconductance parameters, and power supply voltage. Additionally, the study explores techniques for reducing propagation delay, including leveraging alternative materials and adopting specific layout designs. This study can provide insights into the sources of propagation delay in CMOS inverters and provide a comprehensive grasp of methods to alleviate it. By efficiently managing propagation delay, it becomes possible to enhance the overall performance and efficiency of CMOS circuits, thereby facilitating the development of advanced, high-speed digital systems.

Numerical investigation of diamond complementary logic integrated circuits

Silicon complementary metal oxide semiconductor (CMOS) technology drives the integrated circuit industry due to its energy efficiency. The narrow bandgap of silicon has led to the development of wide bandgap semiconductor materials, such as diamond, favored in power electronics, radiofrequency and extreme environment applications. Here we have established a model of the diamond CMOS logic inverter for the first time and successfully simulated the static and dynamic characteristics. The simulated physical model and relevant model parameters are well calibrated with experimental data of diamond p-FET in the literature. The simulation results demonstrate that the all-diamond CMOS inverters possess rail-to-rail operation and excellent inversion characteristics, with the peak gain of 83 V/V, the transition region of 0.25 V, and the noise margins for low and high level of 2.44 V and 2.26 V under VDD = 5 V. Particularly, all-diamond CMOS inverters have improved performance compared to the diamond-GaN inverters, operating at 500 °C with well-preserved inversion characteristics. This thermal reliability indicates that diamond CMOS inverters can be better monolithically integrated for applications in high-temperature environments in the future.

Reduce energy consumption - causes of CMOS inverter switching delay and its influencing factors

This paper offers a comprehensive examination of the Complementary Metal-Oxide-Semiconductor (CMOS) inverter, a quintessential component in contemporary digital integrated circuits, renowned for its minimal power consumption, robust noise resistance, and adaptability. The focus of this investigation is the switching delay of the CMOS inverter, a pivotal attribute that exerts substantial influence on the overall functionality of the circuitry. This discourse undertakes a detailed exploration of the factors contributing to the CMOS inverter switching delay, dissecting the influence of both intrinsic and extrinsic elements. Initially, the analysis delineates the origins of the switching delay in CMOS inverters, categorizing them into internal and external determinants. Subsequently, the study meticulously examines methodologies to modulate these factors, thereby achieving effective control over the delay. By implementing strategic optimizations, this research aims to diminish latency and enhance operational efficiency. Through a theoretical lens, this paper elucidates the complex interplay between these inherent and external factors, culminating in the optimization of the CMOS inverter switching delay. The insights garnered from this analysis are poised to offer a substantive theoretical foundation for the design of more efficient and reliable digital circuits in the current technological milieu.

P/N-Type Conversion of 2D MoTe2 Controlled by Top Gate Engineering for Logic Circuits.

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) are regarded as promising materials for next-generation logic circuits. Top gate field-effect transistors (FETs) have independent gate control ability and can be fabricated directly on TMDC materials without a transfer process. Therefore, it has the merits of device reliability and complementary metal-oxide semiconductor (CMOS) process compatibility, which are demanded in practical circuit-level integration. However, the fabrication of the top gate FET involves depositing an insulating dielectric layer and a gate electrode in sequence on the TMDC channel material, which may affect the device performance. Insightfully investigating the influences of different top-gate-deposition methods on the electrical properties of the TMDC channel and further harnessing these influences to realize a homogeneous CMOS device on an identical 2D TMDC platform are with practice significance. In this work, p/n-type controllable top gate FET arrays based on 2H-MoTe2 are fabricated by using different top-gate-deposition methods. The electron-beam evaporation (EBE) of top metal gate exhibits an obvious n-doping effect on the 2H-MoTe2 channel and converts it from p-type to n-type, whereas the thermal evaporation of top gate affects little to the channel. High-resolution transmission electron microscopy (HR-TEM) analysis reveals that the high-energy metal atoms from the EBE process can penetrate through the 30 nm gate dielectric layers (including 10 nm Al2O3 seeding layer), leading to multiple atomic defects in both MoTe2 and the interface between MoTe2 and Al2O3. Furthermore, by utilizing the top gate engineering, a large-scale double-top-gate MoTe2 homogeneous CMOS inverter array is fabricated. The CMOS inverters exhibit clear logic swing, negligible hysteresis, and high device yield (∼93%), indicating high device reliability and stability. Notably, the fabrication process is facile, free from transfer procedure, and compatible with traditional silicon technology. This work promotes the application of 2D TMDCs in nanoelectronics integration.

Electrical Polarity Modulation in V-Doped Monolayer WS2 for Homogeneous CMOS Inverters.

As demand for higher integration density and smaller devices grows, silicon-based complementary metal-oxide-semiconductor (CMOS) devices will soon reach their ultimate limits. 2D transition metal dichalcogenides (TMDs) semiconductors, known for excellent electrical performance and stable atomic structure, are seen as promising materials for future integrated circuits. However, controlled and reliable doping of 2D TMDs, a key step for creating homogeneous CMOS logic components, remains a challenge. In this study, a continuous electrical polarity modulation of monolayer WS2 from intrinsic n-type to ambipolar, then to p-type, and ultimately to a quasi-metallic state is achieved simply by introducing controllable amounts of vanadium (V) atoms into the WS2 lattice as p-type dopants during chemical vapor deposition (CVD). The achievement of purely p-type field-effect transistors (FETs) is particularly noteworthy based on the 4.7 at% V-doped monolayer WS2, demonstrating a remarkable on/off current ratio of 105. Expanding on this triumph, the first initial prototype of ultrathin homogeneous CMOS inverters based on monolayer WS2 is being constructed. These outcomes validate the feasibility of constructing homogeneous CMOS devices through the atomic doping process of 2D materials, marking a significant milestone for the future development of integrated circuits.

P‐222: Late‐News Poster: Performance of Double Gate P‐ch Cu‐MIC Poly‐Ge TFTs on Flexible Plastic Substrates and Their Feasibility for CMOS Inverter

In this study, p‐ch double‐gate (DG) poly‐Ge thin‐film transistors (TFTs) were fabricated at 385 or 400 °C on flexible plastic bonded to glass substrates. The TFTs were crystallized through metalinduced crystallization using copper (Cu‐MIC). They had an Ion/Ioff ratio of 6 × 103 and a mobility of 8.3 cm2/Vs after the plastic was peeled from the glass substrate. To verify the feasibility of these DG Cu‐MIC poly‐Ge TFTs for complementary metal‐oxide semiconductor (CMOS) on plastic substrates, n‐ch and p‐ch TFTs were fabricated on a glass substrate at 400 °C, which was a suitable temperature for a plastic substrate, and a CMOS inverter was operated after the TFTs were wired.

Flexible Complementary Metal‐Oxide‐Semiconductor Inverter Based on 2D p‐type WSe2 and n‐type MoS2

Transition metal dichalcogenides (TMDCs) are a promising class of two‐dimensional (2D) materials for flexible electronic applications due to their low integration temperature, good electronic properties, and excellent mechanical flexibility. Moreover, TMDCs offer the possibility of co‐integrating both n‐ and p‐type transistors on the same substrate, enabling the realization of complementary metal‐oxide‐semiconductor (CMOS) circuits. In this study, n‐type MoS2 field‐effect transistors (FETs), and p‐type WSe2‐FETs integrated on a flexible foil substrate fabricated by standard thin‐film technology are presented. These devices exhibit high stability in their electronic operation under strain and repeated bending cycles. A CMOS inverter based on these transistors is also successfully demonstrated, which shows excellent switching behaviour with high gain (up to 100), high noise margin (0.87 · VDD), and low average static power consumption (40 pW).

Area and Device Count Efficient Binary Logic Circuits using Anti‐Ambipolar Switch Devices

AbstractThe unique characteristics of an anti‐ambipolar switch (AAS) device exhibit Λ‐shaped transfer responses (namely delta conductance) and present unique opportunities to overcome the limit of silicon‐based, complementary metal‐oxide‐semiconductor (CMOS) logic circuits. It is crucial because a device that only turns on under a certain bias range can be utilized to simplify the logic circuit and reduce the device count and circuit area required to perform logic functions. In this study, a physically scalable AAS device is investigated using ZnO and dinaphtho[2,3‐b:2′,3′‐f]thieno[3,2‐b]thiophene as heterojunction structures to reduce the operating voltage and enhance the peak current and peak‐to‐valley ratio of the AAS device. Moreover, novel logic circuits for AND, OR, XOR, DEMUX, and half‐adder functions are demonstrated using AAS devices. AAS device‐based logic circuits exhibit power‐efficiency characteristics (≈49 times lower than that of the 90‐nm silicon‐based CMOS inverter) and reduce the transistor count and the circuit area by ≈67% and ≈70%, respectively. These results indicate that the use of AAS device‐based logic circuits can be a promising approach to overcome the physical scaling limit of current CMOS technology.

Third generation semiconductor device research: Optimizing CMOS and HEMT designs

The third-generation semiconductor device known as High Electron Mobility Transistors (HEMT) has found extensive applications in high-frequency and high-speed electronic systems. Its widespread usage in critical technologies such as radio telescopes, satellite broadcast receivers, and cellular base stations has established HEMT as a foundational technology underpinning our information and communication society. This paper provides an in-depth exploration of these semiconductor advancements. Firstly, the paper utilizes the CMOS inverter as a representative example to elucidate the fundamental structure of Complementary Metal-Oxide-Semiconductor (CMOS) technology. Additionally, it employs Gallium Arsenide (GaAs) HEMT as an illustrative instance to expound upon the architecture of HEMT devices. Furthermore, the paper delves into the optimization of CMOS technology, focusing on topics such as Multi-Threshold CMOS and the impact of the Width/Length (W/L) ratio. These discussions shed light on ways to enhance the performance of CMOS-based components. Additionally, the paper explores strategies to optimize HEMT devices, including the introduction of carbon doping and the application of the Grey-Wolf optimization technique. These approaches are critical in achieving higher efficiency and performance in HEMT-based applications.

A Study of High-Speed Hamming Distance Detection Circuit Utilizing a Neuron CMOS Inverter

This study tackles the challenge of optimizing associative memory for efficient data retrieval from large databases, crucial in real-time processing. The authors specifically address the issue of increased detection time in the minimum Hamming distance search associative memory, particularly as the number of data bits grows. This memory system utilizes Hamming distance as a key metric to identify the most similar reference data. Our contribution is the development of a new Hamming distance detection circuit employing neuron Complementary Metal Oxide Semiconductor (CMOS) inverters. This proposed circuit significantly outperforms existing models in terms of operational speed. The effectiveness and improved performance of the circuit are validated through simulations using HSPICE, a type of Simulation Program with Integrated Circuit Emphasis (SPICE) demonstrating its potential for more efficient real-time data retrieval applications.

Investigation on Germanium Transistors with HfOx-Based Gate Stacks for CMOS Operations

Germanium (Ge) FinFETs with HfOx-based gate stacks are fabricated to study the CMOS applications. To evaluate the logic circuit operation, the associated CMOS inverters are characterized. Compared to the HfO2, the Hf0.5Zr0.5Ox (HZO) gate stack provides higher drive currents and more symmetric Vth behaviors, which should be associated with the polarization effect. Through cyclic voltage transfer characteristic (VTC) operation and systematical analysis, it is found that both polarization and charge trapping in the gate stack impact the device characteristics. The HZO devices show a negative VTC shift with cycling, while the HfO2 devices reveal a positive shift. This opposite VTC behavior for both gate stack schemes indicates that the interaction of interface states and dipoles significantly influences the device operation. The results revealed in this work present a comprehensive understanding of HfOx-based device optimization.

Matched printed carbon nanotube complementary metal-oxide-semiconductor (CMOS) devices for flexible circuits

The development of matched carbon nanotube (CNT) complementary metal-oxide-semiconductor (CMOS) devices still remains a challenge for flexible and low-power-dissipation circuits. In this study, we found a reliable technique to achieve matched CNT CMOS thin-film transistors (TFTs) for integrated circuits (IC) with low power consumption. The enhancement-mode p-type CNT TFTs were obtained using the low-work-function Al gate electrodes and ultrathin (10 nm) Al2O3 dielectrics, which exhibit the average field-effect mobility(μ) of 6.5 cm2V−1s−1, subthreshold swing (SS) down to 70–85 mV/dec and on/off ratio up to 106 at the low working voltages between −1.5 V and 0.5 V, as well the outstanding stability and mechanical flexibility after 10,000 cycles of bending. Then, by adjusting the aspect ratios of the TFT channels and selectively dropping the electron-doping inks into p-type CNT TFTs’ channels, matched n-type and p-type CNT TFTs were obtained. Finally, flexible printed CMOS inverters with high noise tolerance (84% of 1/2 VDD), high voltage gain (over 32), and low power consumption (down to 32.9 pW) were successfully constructed, owing to the work style of CMOS circuits and electrically symmetrical n-type and p-type TFTs. Furthermore, good-performance NAND and NOR gates have been demonstrated. This work can effectively resolve the leakage current issue of flexible carbon-based electronics with the ultra-thin dielectrics by optimizing the conductive ink formula and printing technology.

Large-Scale Complementary Logic Circuit Enabled by Al2O3 Passivation-Induced Carrier Polarity Modulation in Tungsten Diselenide.

Achieving effective polarity control of n- and p-type transistors based on two-dimensional (2D) materials is a critical challenge in the process of integrating transition metal dichalcogenides (TMDC) into complementary metal-oxide semiconductor (CMOS) logic circuits. Herein, we utilized a proficient and nondestructive method of electron-charge transfer to achieve a complete carrier polarity conversion from p-to n-type by depositing a thin layer of aluminum oxide (Al2O3) onto tungsten diselenide (WSe2). By utilizing the Al2O3 passivation layer, we observed precisely tuned n-type behavior in contrast to transistors fabricated on the as-grown WSe2 film without any passivation layer, which display prominent p-type behavior. The polarity-transformed n-type WSe2 transistor from the pristine p-type shows the maximum ON current of ∼0.1 μA accompanied by a high electron mobility of 7 cm2 V-1 s-1 at a drain voltage (VDS) of 1 V. We successfully showcased a homogeneous CMOS inverter utilizing 2D-TMDC which exhibits an impressive voltage gain of 7 at VDD = 5 V. Moreover, this effective polarity control approach was further expanded upon to successfully demonstrate a range of logic circuits such as AND, OR, NAND, NOR logic gates, and SRAM. The proposed methodology possesses significant promise for facilitating the advancement of high-density circuitry components utilizing 2D-TMDC.

Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

Large‐Scale N‐Type FET and Homogeneous CMOS Inverter Array Based on Few‐Layer MoTe2

Abstract2D MoTe2 is regarded as a favorable candidate for semiconductor nanoelectronics integration. Chemical‐vapor‐deposition‐grown MoTe2 usually presents p‐type characteristics. In order to realize basic electronic units like complementary metal‐oxide‐semiconductor (CMOS) inverter, controllable fabrication of p‐ and n‐type transistors at large scale is of vital importance. Here, large‐scale MoTe2 n‐channel field‐effect transistor (n‐FET) arrays are successfully fabricated with seamless coplanar metallic 1T′‐WTe2 contacts to reduce contact resistance. High‐k HfO2 serves as a gate dielectric and its atomic‐layer‐deposition (ALD) process causes an n‐doping effect on the 2H‐MoTe2 channel. The FETs perform typical n‐type characteristics with average electron density and on/off ratio of ≈1.7 × 1013 cm−2 and 2.1 × 104, respectively. Furthermore, large‐scale homogeneous CMOS inverter arrays are fabricated, showing clear logic swing with low power consumption (≈0.4 nW) and high device yield (≈92%). Notably, their voltage transfer characteristics exhibit small hysteresis, and they work well after being kept in air for 16 months, indicating high device stability. The statistical results show that both the n‐FETs and CMOS inverters have high uniformity and reliability in performance. Significantly, this fabrication method is free from transfer processes and compatible with traditional silicon technology. This work paves the way for the application of few‐layer MoTe2 in semiconductor nanoelectronics integration.

Low Leakage CMOS Design Technique with Stable State Retention

In this research, a new hybrid design technique for low-power complementary metal–oxide semiconductor (CMOS) circuits is proposed which utilizes the advantages of multiple design methodologies such as sleep-transistors, forced-stack, and variable-threshold CMOS (VTCMOS), and is integrated with a buffer circuit. Based on the proposed technique, the CMOS inverter and two-input NAND circuits are simulated in LTspice software using 16 nm high-performance (HP) and low-power (LP) predictive technology models (PTM). Upon comparison with available leakage reduction techniques, the proposed approach demonstrates considerably low power, delay and power delay product (PDP) while maintaining output-logic integrity. The impact of the process parameter, voltage, and temperature (PVT) variations are observed through Monte Carlo simulations, which depict that the proposed model provides uniform sensitivity in terms of the performance metrics within ±3σ statistical variations from the mean. The circuit area of the proposed technique is also estimated and compared with existing methods using the Cadence Virtuoso platform.