Complementary Metal Oxide Semiconductor Field Research Articles

A Novel Design of Low Power & High Speed FinFET Based Binary and Ternary SRAM and 4*4 SRAM Array

The Conventional Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET) design techniques have limitations in designing the Integrated Circuit (ICs), especially with memories of multiple valued logic (MVL) in nanotechnologies. FinFET technologies provide the possibilities of low logic gates and small chip areas with high speed. Memories play an essential role in all types of devices. This paper aims to optimize the power and increase the speed of the SRAM Cell and Array using different techniques in 18nm FinFET technology. The presence of a ternary input provides an additional degree of freedom for the operation of the memory cell. The SRAM cells are also implemented at a Quantum level to improve the results in terms of area, energy, and speed. Simulation and Analysis of the design is done using Cadence Virtuoso Analog Design Environment Tool and Quantum Dot Cellular Automata Designer Tool. The proposed Multi-Threshold Complementary MOS (MTCMOS) based SRAM Array design exhibits an improvement of 4.56% in power consumption and 19.29% in speed as compared to a Conventional CMOS SRAM Array. The proposed ternary implementation of the MTCMOS-based SRAM cell is found to have a 24.9% reduction in power consumption and a 39% improvement in speed as compared to the proposed conventional ternary CMOS SRAM array while SRAM cell latency is 1 clock cycle. It occupies an area of 0.04 µm2 and consists of 33 quantum cells. The average energy dissipation of this SRAM cell is found to be 40% better than the latest existing literature for the design.

Laser Doppler multi-beam differential vibration sensor for real-time continuous visualization of buried objects in multiple frequency bands.

Laser-acoustic detection of buried objects, such as landmines, uses elastic waves in the ground and a laser vibrometer to create a vibration image of the ground surface. A decision on the presence of a buried object is made by analyzing vibration images for multiple vibration frequencies. With traditionally used laser Doppler vibrometers, the vibration imaging data are saved to a computer memory to be analyzed, which increases the detection time. A novel laser multi-beam differential interferometric sensor (LAMBDIS) that provides simultaneous real-time visualization of vibration images for multiple frequencies has been developed. The sensor is capable of displaying vibration images for up to 32 frequency bands simultaneously in real time. The sensor employs a digital line-scan complementary metal-oxide semiconductor camera and field programmable gate arraysbased real-time signal processing and is capable of operating continuously by scanning an object with a linear array of laser beams. Performance of the sensor has been verified experimentally. The ability of the LAMBDIS for real-time continuous vibration imaging of the ground surface in multiple frequency bands for laser-acoustic detection of buried objects has been demonstrated.

Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array

This letter reports a linear multiply-accumulate (MAC) operation conducted on a crossbar memory array based on 28nm high-k metal gate (HKMG) Complementary Metal Oxide Semiconductor (CMOS) and ferroelectric field effect transistor (FeFET). The fabrication is conducted at GlobalFoundries with their standard 28nm technology. The crossbar arrays show a 100% yield in MAC operation on a 300mm wafer. The arrays were divided into <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${8}\times {8}$ </tex-math></inline-formula> segments. The FeFET crossbar arrays were fabricated with access transistors, current-limiter transistors and a current-mode analog-to-digital converter (ADC) on the same wafer. Finally, the data retention characteristics reveal excellent data retention characteristics up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${5}\times {10} ^{{4}}$ </tex-math></inline-formula> seconds, which makes this memory array suitable for carrying out MAC operations in inference engine applications.

(Invited) Achieving Lower Power Logic Using P-Type Metal Oxide Thin Film Transistors

Thin film transistors (TFTs) have enabled the active matrix displays that are a ubiquitous part of everyday life, from mobile phones and tablets through to desktop monitors and home televisions. They are used in the circuit at each pixel over the display as they can be fabricated for relatively low cost with excellent uniformity at low temperatures over large areas on glass substrates. These pixel circuits only require either n-channel or p-channel enhancement mode TFTs. However, there has long been a desire to integrate the display driver electronics onto the display panel as an alternative to connecting silicon-based integrated circuits using complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) to displays. More recently, there has been an increasing interest in producing other logic circuits using TFTs on glass and plastic substrates as this could enable a new generation of products with embedded electronics. However, both of these applications need low power logic circuits. CMOS is an inherently low power technology, but it requires both n-channel and p-channel transistors. Whilst this can be realised in silicon CMOS FETs, it has not yet been achieved using TFTs because it has proved difficult to realise both n-channel and p-channel devices using one material system at low cost. For example, hydrogenated amorphous silicon can be used to make reasonable n-type material but not p-type.Thin film oxide semiconductors such as amorphous indium gallium zinc oxide have been successfully commercialised in the pixel circuits of active matrix displays as they possess high field effect mobility, low threshold voltage, low off-state current and a high switching ratio. There is therefore a lot of interest in finding a suitable complementary p-type metal oxide thin film material to allow CMOS-type logic to be realised using this material system.Cuprous oxide is one such promising candidate material as the top of the valence band is dominated by states which form as a result of hybridisation of the completely filled Cu 3d orbitals and the O 2p orbitals. These hybridised states are less localised and have a higher dispersion with a resulting decrease in the effective mass of holes in these states and a higher carrier mobility. The results of an extensive study of this material shows that the grain structure is of critical importance with [100] oriented films resulting in a higher mobility. Furthermore, the impact of grain boundaries on conduction must be controlled. Although this allows TFTs with reasonable on-state current to be fabricated, it is found that there is a significant residual off-state current which is a result of electron accumulation in the channel. This is consistent with the high off-state current that has been observed widely in TFTs using p-type metal oxide thin film materials.The low off-state current in silicon MOSFETs means that the geometric transistor design in low power CMOS logic circuits only needs to focus on the effect of the on-state current in the p-channel and n-channel transistors. However, in TFTs, the much larger off-state current also becomes important as it can end up being a significant parameter when calculating the power consumption of CMOS logic circuits. An alternative geometric design parameter for TFT logic circuits is presented. This compares the maximum switching current with the static currents allowing optimisation based on both the noise margin and static power consumption. The result is improved performance of TFT-based CMOS logic circuits using the n- and p-type thin film oxide semiconductors that are currently available.

Power and delay analysis of different SRAM cell structures with different technology node

-Now adays Very Large-Scale Integration (VLSI) circuits have good or great demand. Because CMOS circuit design having less power consumption. Transistors on the chip is doubled every two years, according to Moore’s law. So, it means transistor size is decreasing. This leads to increase the chip density and decrease the device size. The write and read depending on the bitline and bitline bar discharging and charging. When design the memory in below 16 nm uses Fin Field effect Transistor (FinFET) technology instead of CMOS (Complementary metal oxide semiconductor field effect transistor). Because to avoid short channel effect. Comparing leakage power, dynamic power and static power at 90 nm technology and write delay, read delay at both 90 nm and 45 nm technology in nine transistors (9 t), eight transistor (8 t) and six transistor (6 t) sram cell.

Leakage reduction technique for nano-scaled devices

PurposeThe purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology.Design/methodology/approachBecause of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices.FindingsThis study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology.Originality/valueAll the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

A new discrete wavelet transform appropriate for hardware implementation

SummaryA new method for computation of discrete wavelet transform is introduced. The impulse response of the finite impulse response (FIR) filter, as the main block in filter bank method, is realized such that orthonormal wavelet transform is achieved without using any multiplier as the most challenging part of the FIR filters. It is proved that the calculated Sobolev regularity of the proposed wavelet is higher than that of Daubechies for the same support width. Compared with most popular known wavelets, simulation results of the newly introduced wavelet for signal denoising prove remarkable advantage of our wavelet especially in terms of complexity and power consumption. The proposed wavelet and well‐known Daubechies wavelet are separately implemented on the Spartan‐6 FPGA (Field Programmable Gate Array) to compare the performance of them. The occupied slices and LUTs (Lookup Table) in realization of the proposed wavelet in comparison with those of Daubechies wavelet are decreased by 50% and 56%, respectively. Its power consumption at 100 MHz is also reduced by 86% in comparison with the Daubechies wavelet, and maximum frequency is increased by 186%. Implementation with standard cells of a 0.18‐μm CMOS (Complementary Metal Oxide Semiconductor Field Effect Transistor) technology shows 75% and 85% reduction in the power and chip area, respectively.

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

Multivalued static random access memory using multivalued FET

ABSTRACTQuaternary logic is very promising logic for multivalued logic implementation. Four state or quaternary static random access memory (SRAM) can be designed using quantum dot gate-quantum dot channel field effect transistor (QDG-QDCFEFT). The presence of quantum dots in the channel region as well as in the gate region of the QDG-QDCFET produces four states in its transfer characteristics. The implementation of quaternary SRAM using QDG-QDCFFET following conventional complementary metal oxide semiconductor field effect transistor architecture is for the first time presented in this paper.

Note: Development of a wideband amplifier for cryogenic scanning tunneling microscopy.

A wideband cryogenic amplifier has been developed for low temperature scanning tunneling microscopy. The amplifier consisting of a wideband complementary metal oxide semiconductor field effect transistors operational amplifier together with a feedback resistor of 100 kΩ and a capacitor is mounted within a 4 K Dewar. This amplifier has a wide bandwidth and is successfully applied to scanning tunneling microscopy applications at low temperatures down to ∼7 K. The quality of the designed amplifier is validated by high resolution imaging. More importantly, the amplifier has also proved to be capable of performing scanning tunneling spectroscopy measurements, showing the detection of the Shockley surface state of the Au(111) surface and the superconducting gap of Nb(110).

Modeling boron dose loss in sidewall spacer stacks of complementary metal oxide semiconductor transistors

The presence of capping materials during annealing (activation for example) can substantially impact the silicon junction profiles of Complementary Metal Oxide Semiconductor Field Effect Transistors (CMOSFET), depending on the nature of these layers. In this paper we specifically investigated the boron out-diffusion from a silicon junction into the silicon oxide in presence of a silicon oxide/silicon nitride capping bi-layer similar to the stacks used to form sidewall spacers. After 120s anneal we observed with secondary ion mass spectrometry (SIMS) substantial boron dose loss in silicon and segregation at the silicon oxide interface related to oxide and nitride material properties, in particular to the hydrogen concentration. We then modeled the boron profiles in both silicon and oxide as a function of the hydrogen static and dynamic in the materials. The exponential-like boron diffusion profiles observed in oxide are reproduced by introducing a long hop mechanism mediated with hydrogen-related defects (HRDs).

Terahertz Real-Time Imaging Uncooled Arrays Based on Antenna-Coupled Bolometers or FET Developed at CEA-Leti

Sensitive and large-format terahertz focal plane arrays (FPAs) integrated in compact and hand-held cameras that deliver real-time terahertz (THz) imaging are required for many application fields, such as non-destructive testing (NDT), security, quality control of food, and agricultural products industry. Two technologies of uncooled THz arrays that are being studied at CEA-Leti, i.e., bolometer and complementary metal oxide semiconductor (CMOS) field effect transistors (FET), are able to meet these requirements. This paper reminds the followed technological approaches and focuses on the latest modeling and performance analysis. The capabilities of application of these arrays to NDT and security are then demonstrated with experimental tests. In particular, high technological maturity of the THz bolometer camera is illustrated with fast scanning of large field of view of opaque scenes achieved in a complete body scanner prototype.

Fabrication of Advanced High-Speed Complementary Metal Oxide Semiconductor Field Effect Transistor

In this study we propose the fabrication of advanced high-speed complementary metal oxide semiconductor field effect transistor (AHCMOS) by combining a P-carbon nanotube with n-metal oxide semiconductor (NMOS) on a single chip. The target is to achieve extremely high speed low-power dissipating miniaturized device with improved functionalities.&nbsp; The technology of conventional metal oxide semiconductor field effect transistor (MOSFET) and nanotechnology are applied in this research. A P-carbon nanotube is complemented with the conventional NMOS all embedded on the same chip.&nbsp; Although it is possible to fabricate both a P and N carbon nanotube to form a complementary pair, and also a PMOS and NMOS to form a complementary pair, however in this research we propose a hybrid structure with carbon nanotube transistor technology and complementary MOSFET technology. This device therefore combines the best characteristics of carbon nanotube technology and CMOS technology to provide enhanced logic functions that are optimized for the high-speed, low-power systems and miniaturized size ideal for very large scale integration (VLSI).

Analysis and experimental verification of DNA single-base polymerization detection using CMOS FET-based redox potential sensor array

We report a method for detecting DNA single-base polymerization using a complementary metal oxide semiconductor (CMOS) field effect transistor (FET)-based redox potential sensor array. The redox potential detection method has the possibility of high-accuracy detection of DNA polymerization compared with other FET-based methods because this method is not affected by buffer conditions. First, we demonstrated pyrophosphate (PPi) detection assuming that DNA polymerization occurred. This result showed a sensitivity of −12.3 mV/decade for a logarithmic concentration of PPi in the range of 0.05–1 mM. To investigate the appropriateness of this measurement result, we conducted a theoretical analysis using the equilibrium constant. Next, we demonstrated DNA single-base polymerization detection. There was a 5.65 mV difference between the reaction solutions with a mismatched deoxynucleotide triphosphate (dNTP) and with a matched dNTP. This voltage difference is reasonable given the PPi detection result, which achieves a sufficient signal-to-noise ratio (SNR) of more than 20 dB.

Label free electrical detection of prostate specific antigen with millimeter grade biomolecule-gated AlGaN/GaN high electron mobility transistors

AlGaN/GaN high electron mobility transistor (HEMT) was successfully fabricated by complementary metal-oxide semiconductor field effect transistor-compatible fabrication method, and the label-free, electrical detection of prostate specific antigen in real time using the biomolecule-gate AlGaN/GaN HEMT sensor was presented. It shows a rapid response when target prostate biomarker in buffer solution was added to the antibody-immobilized sensing area. The linear range for target prostate specific antigen detection has been demonstrated from 0.1 pg/ml to 10.269 ng/ml and a low detection below 0.1 pg/ml level is estimated, which is the best result of AlGaN/GaN HEMT biosensor for prostate specific antigen (PSA) detection till now. The sensitivity of 0.027 % is determined for 0.1 pg/ml prostate specific antigen solution. The electrical result of the biomolecule-gated AlGaN/GaN HEMT biosensor suggested that this biosensor might be a useful tool for the prostate cancer screening.

Macroscopic and nanometer scale stress measurement of Ni(Pt)Si silicide: Impact of thermal treatments ranging from millisecond to several hours

The authors have measured and compared the stress in nickel silicide full sheet layers prepared with added platinum on (001) p-type Si wafers by using either a rapid thermal anneal (RTA) at 390 °C or a millisecond submelt laser dynamic scanning anneal (DSA) at 800 °C. The room temperature tensile stress of the silicide annealed with DSA is 1.65 GPa, whereas that of the silicide annealed with RTA at 390 °C is 800 MPa. Our analysis confirms that the origin of the stress lies in thermal expansion factors. Despite some small variations, the stress remains highly tensile in both layers after a 1 h post-treatment at 400 °C, with values of 1.4 GPa and 850 MPa for the DSA and RTA samples, respectively. The authors also performed strain measurements with dark field electron holography in the source drain region of 28 nm field complementary metal oxide semiconductor field effect transistors, under the silicide dot. They then determined the stress inside the silicide by combining the strain measurement with finite element mechanical simulations; values of 1.5 GPa and 600 MPa were found at the nanometer scale for the DSA and RTA samples, respectively, which are consistent with the macroscopic observations.

Design and Performance Comparison of 6-T SRAM Cell in 32nm CMOS, FinFET and CNTFET Technologies

In most of the digital circuits, CMOS based design is allowed to be used in practice. Generally, CMOS stands for Complementary Metal Oxide Semiconductor Field Effect Transistor, that is, considered to be as combination of both PMOS as well as NMOS. In CMOS based design, symmetry should be followed in circuit operation. Most of the complex circuits are allowed to design in CMOS, however, there are several drawbacks present in this complementary based design. Also, SRAM cell read stability and write-ability are major concerns in nanometer CMOS technologies, due to the progressive increase in intra-die variability and supply voltage scaling. Therefore, it is necessary to find alternative way suitable for particular design, instead of CMOS. Most of the modern design is based on Carbon nanotube FET or FinFET because of its superior properties interms of power consumption, leakage power, delay etc. The objective of this work mainly focus on designing 6-T SRAM cell in 32nm CMOS, CNTFET as well as FinFET and finally, to compare the parameters such as average power, delay and leakage current.

Improvement of metal gate/high-k dielectric CMOSFETs characteristics by neutral beam etching of metal gate

For the metal gate patterning of metal gate/high-k dielectric complementary metal–oxide–semiconductor field effect transistors (CMOSFETs), plasma induced damage (PID) was identified during the etching by a conventional reactive ion etching (RIE) and, a neutral beam etching (NBE) technique. NBE uses reactive radical beam instead of reactive ions for RIE. Improved device characteristics such as the mobility, the transconductance, subthreshold slope, and drain current could be observed. Particularly, the application of the NBE to PMOSFET was more effective than that to NMOSFET. This improvement was related to the decreased interface trap density at the gate dielectric of CMOSFEETs.

Investigation and Integration of Polycrystalline Silicon/TiN/SiON Gate Stack in Silicon on Thin Buried Oxide Complementary Metal Oxide Semiconductor Field Effect Transistors

Investigation and Integration of Polycrystalline Silicon/TiN/SiON Gate Stack in Silicon on Thin Buried Oxide Complementary Metal Oxide Semiconductor Field Effect Transistors