Abstract
The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.
Highlights
A review on the atomic layer deposition (ALD) of metal gate for both NMOSFETs and PMOSFETs based on the state-of-the-art of the ongoing research was presented
The discussion starts with the introduction to the necessities of technical transition from poly-Si/SiO2 to high-κ/Metal gate and the demand for the ALD of metal gates due to the special challenge the 3D device such as FinFETs and GAA-field effect transistors (FETs) has to face
CMOSFETs and the 3D devices such as FinFETs and GAA-FETs are discussed as the starting point of material selection
Summary
Basic principle of FETs was proposed by Julius Edgar Lilienfeld in 1925 [1], in which, an electric field generated by a voltage applied to the gate electrode is used to control the flow of current between the drain and source electrodes. SiO2 as dielectric in the first Si MOSFET technology, together with aluminum (Al) metal gate. Dielectric was used in was induced to replace Al. In 1989, the dual gate technology by doping the poly-Si was employed in induced. In 1989, the dual technology by doping the used poly-Si employed in until 130 nm During these years, switching performance of the devices was continuously improved, theseCMOS years, process. SiO2, the leakagetothrough it islevel, negligible compared to due that to quantum effect increases to large extent and dominates the device leakage [4]. As itsextent thickness is reduced to nanometer level, the tunnel leakage due the prediction of ITRS in 1999, the pure SiO2 could not be used as the gate dielectric after 130 nm node. Be byasis the energy band alignment given asdepends
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